JPS61256482A - Picture processing device - Google Patents

Abstract

PURPOSE:To mutually use an image data processed by respectively the different image density of respective buses by providing picture element density converting circuit capable of bidirectionally converting the picture element density in a reading and writing means. CONSTITUTION:When reading the image data (HD data) of high picture element density of a picture element memory 20 as the image data (LD data) of low picture element density, the HD data read through a data bus 26 is thinned out by a low picture element density reading control circuit 22 and outputted as the LD data to a data bus 25 to carry out the image density conversion from the HD data to the LD data. When the LD data is density converted into the HD data and written in the picture memory, the LD data in the data bus 25 is subjected to the duplication processing of a dot by a low picture element density writing control circuit 23 and outputted as the LD data to the data bus 26. Thus, the image processing of high function can be performed at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus having a dual bus configuration and suitable for bidirectionally processing image data.

PRIOR ART In a conventional 1 image processing device, a system bus for processing W image data is separated into a system bus 2 for processing at low pixel density and a system bus 1 for processing mainly at high pixel density, and each can be processed independently. However, data is transferred from system bus 1 to system bus 2 and CR
When displaying on a T display, first convert the high pixel density image data on the system bus l side to low pixel density image data, and then convert the dual port memory that connects the two system buses. Since the image data is transferred to the system bus 2 via the system bus 2, there is a problem in that it takes time for the data to be displayed.

In order to solve this problem, the present inventor developed an image processing device in which two system buses are connected by a dual port memory in a dual bus configuration, and the dual port memory has a high pixel density to a low pixel density. We have previously proposed a method in which the density conversion function is provided and the density conversion is performed within the dual port memory mentioned above when transferring image data from system bus 1 to system bus 2. No. 59-219481, see I9), thereby.

This makes it possible to reduce the time spent exclusively using the system bus for density conversion and the time required to transfer data.

In this way, in the conventional method, the density conversion is ``one-way'', so the image data on the system bus 2 can only be transferred to the system bus 1 with a low pixel density. Even if you try to use the image data created on the display memory in the CRT display on the system bus l, it cannot be used as is.In fact, the control device of the CRT display contains a high-performance graphic controller, Such demands are high because the above image data is very useful.

An object of the present invention is to respond to such conventional demands by providing a processing system with a dual bus configuration that processes image data with a specific pixel density, in which image data processed with different pixel densities on each bus is processed. An object of the present invention is to provide an image processing device that can mutually use the following.

Configuration In order to achieve the above object, the image processing device of the present invention has the following features:
a first system bus that processes image data of a first pixel density; a second system bus that processes image data of a second pixel density; and one system bus that is connected between the first and second system buses. In an image processing LIT having a writing/reading means capable of writing/reading from the first system bus, a pixel density conversion circuit capable of bidirectionally converting pixel density is provided in the writing/reading means, and the writing/reading is performed from the first system bus. The image data of the first pixel density written in the means is read out by the pixel density conversion circuit as image data of the second pixel density to the second system bus, and from the second system bus, the image data of the first pixel density is read out from the second system bus. The image data of the second pixel density written in the reading means is converted into image data of the first pixel density by the pixel density conversion circuit.
It is characterized by being read out to the system bus.

Hereinafter, the configuration of the present invention will be explained in detail using one embodiment.

11th! 1 is a schematic configuration diagram of an image processing apparatus showing an embodiment of the present invention.

In FIG. 1, 1 is a system bus where image data is processed with high pixel density, 2 is a system bus where image data is processed with low pixel density, 3 and 4 are central processing units, 5 is an image processing unit, and 6 , 7 is an image memory, 8 is a CRT display, 9 is a CRT display control device, and 10 is a dual port memory with a bidirectional pixel density conversion function according to the present invention.

The data transfer operation between the system bus 1 and the system bus 2 will be explained below.

When transferring high pixel density image data that has been subjected to various processing using the image processing unit 52 image memory 6, etc. on the central processing unit 3 on the system bus 1 side to the system bus 2 side, first, bidirectional Dual port memory with pixel density conversion function (hereinafter referred to as dual photo memory) 10
written to.

On the other hand, on the system bus 2 side, dual port memory lO
At the same time as reading the image data written to.

The image data is density-converted and read out as image data with low pixel density. Therefore, immediately.

Since image data can be displayed on the CRT display 8, it can be used as a CRT display control device! ! 9
The low pixel density image data that has been density-converted by the dual port memory IO is transferred to the dual port memory IO.

The CRT display control device 9 converts this image data into C
The data is output to the RT display 8 and displayed on the screen. Also, CRT display control equipment! ! Graphics processing can be performed using the high-performance graphics controller built into 9. In addition, in contrast to the above operation, the low pixel density image data processed within the CRT display control device 9 is further transferred to the central processing unit ffi! via the system bus 2 as necessary. 4 and the image memory 7 and then written into the dual port memory 1o, the density is converted to a high pixel density at the same time as this writing. Therefore, on the system bus 1 side, if this image data is read out from the dual port memory lo, it can be used for processing immediately.

Figure 2 shows a characteristic dual port memory 10 of the present invention.
This is a detailed configuration diagram of the 31st! I is a diagram showing the principle of density conversion according to one embodiment.

Pixel density conversion will be explained below with reference to FIGS. 2 and 3.

In FIG. 2, 20 is an image memory capable of storing one page of high pixel density image data; 21 is an image memory address control circuit that controls the address of a memory area in the image memory 20; 22 is an image memory 20; 23 is a low pixel density readout control circuit that converts high pixel density image data into low pixel density image data and outputs the data; 23 converts low Wx pixel density image data on the system bus 2 side to high pixel density; A low pixel density write control circuit converts the pixel density into image data and writes it into the image memory 20, 24 to 26 are data buses for transferring image data, 27 to 29 are address buses for transferring address data, 30 and 31 are control buses for transferring control signals for controlling each circuit in the dual port memory 10.

First, under the control of the control bus 30 in the system bus 1, when address data is input to the image memory address control circuit 21 through the address bus 27, the image memory address specified from the 1-image memory address control circuit 21 is transferred to the image memory 20. is output to. Next, high pixel density image data is transferred to the image memory 2 through the data bus 24.
Stored at 0. Here, high pixel density image data.

12 dots/lsm, and both image data with low pixel density are 6
Consider it as dot/llll01.

The high pixel density image data (12 dots/arm) in the image memory 20 is replaced with the low pixel density image data (6 dots/+
Itg), as shown in FIG. 3(a), it is necessary to thin out one dot at a time in the main scanning direction and to thin out one line at a time in the sub-scanning direction. Therefore, the contents of the address bus 28 given along with the control of the control bus 31 are converted by the low pixel density readout control circuit 22 into an address necessary for density conversion and output to the address bus 29. When the converted address data in the address bus 29 is input to the image memory address control circuit 21, the WA-defined image memory address is output to the image memory 20, and reading of high pixel density image data is performed. This is done through the data bus 26. The high pixel density image data read out through the data bus 26 is thinned out by the low pixel density read control @M22, and is output to the data bus 25 as low ij4 density image data by one or more operations.
Pixel density conversion is performed from high pixel data to low pixel data.

Low pixel density image data (6 dots/m) on the system bus 2 side and high pixel density image data (12 dots/liI)
When converting the density to m) and writing it into the image memory 20,
31st! As shown in I(b), one dot is used overlappingly in the main scanning direction to generate two dots, and in the sub-scanning direction,
This is further overlapped by one line to generate two lines. Therefore, the contents of the address bus 28 given together with the control of the control bus 31 are also subjected to necessary address conversion by the low pixel density write control circuit 23 and output to the address bus 29, but in the sub-scanning direction. An address conversion operation is performed such that the same data is also written to adjacent addresses. Such address converted address data is sent to the image memory address control circuit 21.
The low pixel density image data in data bus 25 on system bus 2 is input to image memory 20 through
The low pixel density writing system W circuit 23 performs dot duplication processing, and the data is transferred to the data bus 26 as high pixel density data.
is output to. The output high pixel density data is stored at the address location of the image memory 20. Through the above operations, when one page of low pixel density image data is written from the system bus 2 side to the dual port memory 10, one page of high pixel density image data appears on the one image memory 20.

This data can be read out from the system bus 1 as desired.

In this way, in this embodiment, the various processing functions connected to each bus of the dual bus configuration can be mutually and arbitrarily used on both buses.

Effects As explained above, according to the present invention, in a system having a dual bus configuration that processes image data with a specific pixel density, image data processed with different pixel densities on each bus can be mutually used. This allows high-performance image processing to be performed at high speed.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of an image processing device according to an embodiment of the present invention, FIG. 2 is a detailed configuration diagram of a dual port memory with a bidirectional pixel density conversion function characteristic of the present invention, and FIG. FIG. 3 is a diagram showing the principle of density conversion according to this embodiment. l, 2 systems bus, 3.4: central processing unit. 5: H image processing unit, 6.7: Image memory, 8: CR
T display, 9: CRT display control device, l
O2 Dual port memory with bidirectional pixel density conversion function according to the present invention, 20: Image memory. 21: Image memory address control circuit, 22: Low pixel density read control circuit, 23: Low pixel density write control circuit, 2
4-26: Data bus, 27-29 near address bus, 3
0,31: Control bus. Patent applicant Rico Co., Ltd. - t') to O
<Go to K bX □Main scanning direction □Main scanning direction Figure 3 □Main scanning direction □Main scanning direction

Claims (1)

[Claims] (1) A first system bus that processes image data with a first pixel density, a second system bus that processes image data with a second pixel density, and a connection between the first and second system buses. In an image processing apparatus having a writing/reading means capable of writing/reading from both sides, a pixel density conversion circuit capable of converting pixel density from both directions is provided in the writing/reading means, The image data of the first pixel density written in the writing/reading means is read out to the second system bus as image data of the second pixel density by the pixel density conversion circuit, and is then read out from the second system bus as image data of the second pixel density. The image data of the second pixel density written in the writing/reading means is read out to the first system bus as image data of the first pixel density by the pixel density conversion circuit. Processing equipment.