JPH0591306A - Line buffering processing circuit - Google Patents

Abstract

PURPOSE:To provide the line buffering processing circuit which performs the delay processing shorter than one line by (n) picture elements at the same operation speed as a line buffering circuit for one line delay. CONSTITUTION:Input data is inputted to a memory 14 through a three-state buffer 15. Data subjected to the delay processing shorter than one line by (n) picture elements is outputted from the memory 14. The read/write address to the memory 14 is controlled by a counter 13. The counter 13 is connected to an adder 11 and a flip flop 12 for the purpose of reading out data written in the memory n picture elements ahead. Thus, the delay processing shorter than one line by (n) picture elements is quickly executed because a selector to select the counted value from the counter is unnecessary.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line buffering processing circuit used in an image processing apparatus or the like.

[0002]

2. Description of the Related Art When a smoothing filter process shown in FIG. 2 is performed in real time on a raster-scanned serial image data string, a 1-line delay circuit (shown in FIG. 3) is used to extract image data to be referred to. 31a, 31
b), that is, a line buffering processing circuit is required in the configuration. In FIG. 3, reference numerals 32a to 32f are 1-pixel delay elements, and 33 is an arithmetic circuit for performing a weighted average operation according to the filter coefficient shown in FIG. Conventionally, a line buffering processing circuit for accumulating and delaying image data for one line is realized by the configuration shown in FIG. In FIG. 4, reference numeral 41 is a counter for generating an address signal for the memory, and 42 is a RAM having a capacity capable of accumulating one line of an image data string.
(Random access memory), 43 is a three-state memory that controls input data during a write cycle
A buffer 44 is a flip-flop that strobes the read data output from the SRAM 42 during a read cycle. FIG. 5 is a diagram showing a timing example of the image signals handled here. It is assumed that one pixel of data is input in synchronization with the image clock, one line of image data is input in synchronization with the line synchronization signal, and one page of image data is input in synchronization with the page synchronization signal. Therefore, the circuit shown in FIG. 4 performs the line buffering process at the timing shown in FIG. Here, for the sake of explanation, a timing chart when there are seven image data in one line is shown. The input data is input line by line in synchronization with the image clock (CLK) and the line synchronization signal (LSYN). The counter operates using the line synchronization signal as a count operation enable signal in synchronization with CLK. The input data is output on the data bus by the write signal WR, and at the same time, the counter output is written in the memory using the address.

The data written in the memory is read by the RD signal during the next line processing and strobed to the flip-flop. By sequentially performing the above processing for each line, input data delayed by one line can be obtained as output data.

[0004]

However, depending on the contents of the processing, it may be necessary to perform the delay processing with n pixels less than one line. For example, in the binarization processing circuit by the error diffusion method shown in FIG. 14, when the error distribution processing according to the matrix shown in FIG. 15 (diffusion of the errors e1 to e4 with respect to the peripheral 4 pixels with respect to the target pixel) is performed, the delay processing with 3 pixels less than one line is performed. is necessary. Here, in FIG.
41a to e are 1-pixel delay elements for delaying the input image data by 1 pixel, 142a to d are adders for adding the quantization error generated by binarization to neighboring pixels, and 143 is 3 pixels from 1 line. A line buffer for performing a small amount of delay processing, 144 is a binarization circuit for binarizing multivalued data of a target pixel including a binarization error of peripheral pixels, and 145 is a quantization error generated when the target pixel is binarized. Is an error calculation circuit for calculating the value of ## EQU1 ## and an error distribution circuit 146 for calculating a value for distributing the quantization error to peripheral pixels.

FIG. 7 shows the structure of a line buffer that realizes such a circuit. As shown in FIG. 7, there can be considered a method in which a read address signal obtained by adding n to a read address signal within one clock is used as a read address signal to perform delay processing with n pixels less than one line. In FIG. 7, 71 is a counter that generates an address signal for the memory, 72 is an adder that adds n to the counter output, and 73 is a selector that selects the addition result during the read cycle and outputs the counter 71 during the write cycle. Select a result. 74 is an RA having a capacity capable of accumulating one line of an image data string
M (random access memory), 75 is a three-state buffer that controls input data during a write cycle, and 76 is a flip-flop that strobes read data output from the SRAM during a read cycle. FIG. 8 shows a timing chart when n = 2. The input data is input line by line in synchronization with the image clock (CLK) and the line synchronization signal (LSYN). The counter operates using the line synchronization signal as a count operation enable signal in synchronization with CLK. The input data is output on the data bus by the write signal WR,
At the same time it is written to memory. As the counter output, the addition output from the adder 72 is selected in the read cycle by the selection signal R / W, and the counter 71 is selected in the write cycle.
Output from is selected. The data written in the memory is RD using the adder output as an address during the next line processing.
It is read by the signal and strobed to the flip-flop. By sequentially performing the above processing for each line, it is possible to obtain an input signal which is delayed by 2 pixels from one line in the output data.

In this method, however, the address output is delayed by the selector, and the addition processing of the address signal must be performed within one clock, and the number of data bits (for example, when processing an image of 400 DPI of A3 size, the address width is 13 bits). In the line buffer processing, which has a lot of necessity, there is a problem that the processing of the adder takes a long time and the output of the address is delayed and the operation speed is lowered.

As a second method, as shown in FIG. 9, the result of delaying the counter output by n clocks by flip-flop and the counter output are the write address and the write address, respectively.
A method of selecting as the read address can be considered. Figure 9
In the figure, 91 is a counter for generating an address signal to the memory, 92 is n flip-flops for delaying the counter output by n clocks, 93 is a selector for selecting the addition result in the read cycle and the counter output result in the write cycle. select. Reference numeral 94 is a RAM (random access memory) having a capacity capable of storing one line of an image data string, 95 is a three-state buffer that controls input data in a write cycle, and 96 is output from SRAM in a read cycle. It is a flip-flop that strobes the read data that has been read. FIG. 10 shows a timing chart when n = 2. The input data is input line by line in synchronization with the image clock (CLK) and the line synchronization signal (LSYN). The counter operates using the line synchronization signal as a count operation enable signal in synchronization with CLK. The input data is output on the data bus by the write signal WR and simultaneously written in the memory. Counter output is selection signal R /
By W, the result delayed by n clocks is selected in the write cycle, and the counter output is selected in the read cycle. The data written in the memory is read by the RD signal at the time of the next line processing and strobed to the flip-flop. By sequentially performing the above processing for each line, it is possible to obtain an input signal which is delayed by 2 pixels from one line in the output data.

However, even in this case, there is a problem that the address output is delayed by the selector to lower the operation speed, and the number of registers for delaying the address increases and the circuit scale increases as n becomes larger.

The present invention has been made in view of the above problems and does not decrease the operation speed, and further suppresses an increase in the circuit scale, and performs a line buffering process for delaying data having n pixels less than one line. The purpose is to provide a circuit.

[0010]

In order to achieve the above object, the present invention is a line buffering processing circuit for delaying a raster-scanned serial image data sequence by n pixels less than one line. A three-state buffer for controlling, an initial value settable counter for outputting an address signal, an adder for adding the value n to the counter output, a register for strobing the addition result by a line synchronization signal, and the counter output for addressing. RAM (random access memory)
And a register for strobeing the output data of the RAM, and the counter is configured such that the strobeed register value is set as a counter initial value for each line synchronization signal.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a diagram showing an embodiment of a line buffering processing circuit according to the present invention. This line buffering processing circuit is applied to the line buffer 143 of FIG. An adder 11 adds n to the counter output. A flip-flop 12 strobes the addition result at the trailing edge of the line sync signal. 1
A counter 3 operates in synchronization with the image clock with the strobe result as an initial value. Reference numeral 14 is a RAM having a capacity capable of accumulating one line of an image data string.
(Random access memory), 15 three-state control input data during write cycle
The buffer 16 is a flip-flop that strobes the read data output from the SRAM during the read cycle.

Next, the operation of this embodiment will be described with reference to FIG. As described above, the image data includes the image synchronization signal (C
LK) and the line synchronization signal (LSYN) are input serially. Here, for the sake of explanation, the case where the number of pixels in one line is 7 will be described. Counter 1
3 gives LSYN as a count enable signal and an initial value load signal to set the output of the flip-flop 12 as an initial value in a section where LSYN is invalid, and sets the set value as an initial value in a valid section. Count up as a value. When n = 2 and the flip-flop output of the first line is set to 0, the adder outputs 2 during the line. The flip-flop 12 strobes the adder output at the falling edge of LSYN, and the counter is set to the initial value = 2. At the time of processing the second line, the counter counts up with an initial value of 2, and similarly operates with an initial value of 4 on the third line. Below, the counter operates with a value of 2 being accumulated in line units as an initial value. Input data is write signal WR
Is output to the data bus, and at the same time, the counter output is written in the memory using the address. The data written in the memory is read by the RD signal in the next line processing and strobed to the flip-flop 16. Since the address at the time of processing the next line is advanced by 2 clocks, the data written in the previous line is read out by 2 pixels earlier, that is, the delay processing is performed by 2 pixels less than that of 1 line.

According to the embodiment of the present invention, since the counter output is directly connected to the memory without passing through the selector, the memory is accessed at the same operation speed as the 1-line delay line buffering circuit shown in FIG. Things are possible. Further, even when n is a large value, the circuit scale does not increase only by changing the added value.

[Other Embodiments] In the above-described embodiments, the case where one memory is used and the read operation and the write operation are executed by time division has been described. The present invention is not limited to this, and can be implemented in a so-called double buffer configuration in which two memories are used and a read operation and a write operation are simultaneously performed for the purpose of high-speed operation. FIG. 12 shows an embodiment of the double buffer structure. In FIG. 12, 121 is an adder, which adds n to the counter output. A flip-flop 122 strobes the addition result at the falling edge of the line sync signal. Reference numeral 123 is a counter, which operates in synchronization with the image clock with the strobe result as an initial value. Reference numerals 124 and 125 are RAMs (random access memories) having a capacity capable of accumulating one line of image data sequence, 126 and 127 are three-state buffers that control input data during runt cycle, and 128 is read data. Are selected from the outputs of the memory 1 and the memory 2, and a flip-flop 129 strobes the selected read data.

Next, the operation of this embodiment will be described with reference to FIG. As described above, the image data includes the image synchronization signal (C
LK) and the line synchronization signal (LSYN) are input serially. Here, for the sake of explanation, the case where the number of pixels in one line is 7 will be described. Counter 1
Reference numeral 21 applies LSYN as a count enable signal and an initial value load signal to count up the output of the flip-flop 122 as an initial value while LSYN is valid. When n = 2 and the flip-flop output of the first line is set to 0, the adder outputs 2 during the line. The flip-flop 122 strobes the adder output at the falling edge of LSYN, and the counter 123 counts up the processing of the second line with an initial value of 2. As described above, the counter operates with a value obtained by cumulatively adding n to each line as an initial value. Input data is W when processing the first line
Writing to the memory 1 is performed by the R1 signal. During the processing of the second line, the data written from the memory 1 is read by the OE1. The selector 128 selects the memory output in the read state. That is, the output of the memory 1 is selected when OE1 is active. Since the address at the time of processing the second line is advanced by 2 clocks due to the processing of the address initial value, the data written in the first line is read out by 2 pixels earlier, that is, a delay of 2 pixels less than that in 1 line. Processing is performed. Further, the input data of the second line is written into the memory 2 by the WR2 signal at the same time when it is read from the memory 1. With the above processing, even in the processing of the double buffer structure, the delay processing with n pixels less than one line can be realized with the same structure.

Since the counter output is directly connected to the memory without passing through the selector in this embodiment as in the above embodiment, it is possible to access the memory at an operation speed equal to that of the conventional 1-line delay line buffer. Is.

As described above, when the present invention is applied to the double buffer circuit constructed for the purpose of high speed operation, the effect becomes more effective.

Further, by using the line buffering processing circuit shown in FIGS. 1 and 12 in the circuit of the error diffusion method shown in FIG. 14, a high-quality image is obtained for both the character and halftone images. Images can be obtained at high speed.

[0020]

As described above, according to the present invention, the operation speed does not decrease, and the increase in circuit size is suppressed,
It is possible to realize a line buffering processing circuit that delays data that is n pixels less than the line.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a line buffering processing circuit that is a first embodiment of the present invention.

FIG. 2 is a diagram showing a matrix example of a smoothing filter.

FIG. 3 is a diagram showing a configuration of a smoothing filter.

FIG. 4 is a diagram showing an example of a line buffering processing circuit that performs 1-line delay processing.

FIG. 5 is a diagram showing a timing of an image signal.

FIG. 6 is a diagram showing a timing chart of a line buffering processing circuit that performs 1-line delay processing.

FIG. 7 is a diagram showing a first example of a conventional line buffering processing circuit having n pixels less than one line.

FIG. 8 is a diagram showing a timing chart of a first line buffering processing circuit in which n pixels are smaller than the conventional one line by n pixels.

FIG. 9 is a diagram showing a second example of a conventional line buffering processing circuit having n pixels less than one line.

FIG. 10 is a diagram showing a timing chart of a second line buffering processing circuit in which n pixels are smaller than the conventional one line by n pixels.

FIG. 11 is a diagram showing a timing chart of the first line buffering processing circuit in which n pixels are smaller than one line by n pixels according to the present embodiment.

FIG. 12 is a diagram showing a second embodiment of a line buffering processing circuit in which n pixels are smaller than one line by n pixels according to the present embodiment.

FIG. 13 is a diagram showing a timing chart of a second line buffering processing circuit in which n pixels are smaller than one line by n pixels according to the present embodiment.

FIG. 14 is a diagram showing a configuration example of a binarization processing circuit by an error diffusion method that requires a delay process in which n pixels are smaller than one line.

FIG. 15 is a diagram showing an example of a diffusion matrix of the error diffusion method.

[Explanation of symbols]

 11 adder 12 flip-flop 13 counter 14 memory 15 three-state buffer 16 flip-flop

Claims (2)

[Claims] 1. A line buffering processing circuit for delaying a raster-scanned serial image data sequence by n pixels less than one line, wherein a three-state buffer for controlling input image data and an initial value setting for outputting an address signal. A possible counter, an adder that adds the value n to the counter output, a register that strobes the addition result with a line synchronization signal, a RAM (random access memory) that uses the counter output as an address, and output data of the RAM A line buffering processing circuit having a register for strobe. 2. The line buffering processing circuit according to claim 1, wherein the strobeed register value of the counter is set as a counter initial value for each line synchronization signal.