JPS60137171A - Facsimile equipment with picture element density converting mechanism - Google Patents

Facsimile equipment with picture element density converting mechanism

Info

Publication number
JPS60137171A
JPS60137171A JP58249176A JP24917683A JPS60137171A JP S60137171 A JPS60137171 A JP S60137171A JP 58249176 A JP58249176 A JP 58249176A JP 24917683 A JP24917683 A JP 24917683A JP S60137171 A JPS60137171 A JP S60137171A
Authority
JP
Japan
Prior art keywords
pixel
circuit
picture element
image signals
binary image
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58249176A
Other languages
Japanese (ja)
Other versions
JPH0325073B2 (en
Inventor
Shinji Kume
真司 久米
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58249176A priority Critical patent/JPS60137171A/en
Publication of JPS60137171A publication Critical patent/JPS60137171A/en
Publication of JPH0325073B2 publication Critical patent/JPH0325073B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Image Processing (AREA)
  • Editing Of Facsimile Originals (AREA)

Abstract

PURPOSE:To reduce deterioration in picture quality by laying emphasis on correlations among original image signals at four points which surround a converted picture element in a main scanning, a subscanning, and a diagonal direction. CONSTITUTION:Logical values of two binary signals in the main scanning direction as to four original picture elements surrounding the converted picture element, logical values of two binary signals in the subscanning direction, and logical values of two binary signals in the diagonal directions are processed and then ORed. Then it is decided whether the image signal of the converted picture element is at a black or white level according to the OR result is ''0'' or ''1''. Therefore, white is reduced, and an increase in the number of black isolated points is suppressed and the reggedness of a segment due to jitters is reduced.

Description

【発明の詳細な説明】 (技術分野) 本発明は画素密度変換機構を有するファクシミリ装置に
関する。
TECHNICAL FIELD The present invention relates to a facsimile device having a pixel density conversion mechanism.

(従来技術) 従来、画素密度の異なるファクシミリ装置間で通信を行
なう場合、画素密度を相手装置に合せないと、記録画の
縮少、あるいは、拡大が起ってしまう。これを解決すや
方法としては幾つかある。
(Prior Art) Conventionally, when communicating between facsimile apparatuses having different pixel densities, if the pixel density cannot be matched to the other apparatus, the recorded image will be reduced or enlarged. There are several ways to solve this problem.

るいは挿入する方法である。この方法はアルゴリズム及
びハードウェアの構成が簡単であるが白抜け、つぶれが
目立ち画質の劣化が大きい。
The other method is to insert it. Although this method has a simple algorithm and hardware configuration, white spots and blurring are noticeable and the image quality is greatly degraded.

画質の劣化を軽減する方嬉として、オ(リジナル画素の
前ラインあるいは次ラインの情報を考慮して変換画素の
画信号レベルを決定する論理和法、多数決法、OPC法
、SPC法等があるが、一般にアルゴリズムが複雑にな
り、ハードウェアの構成も大きくなる。更にこの方法を
用いてアルゴリズムを単純化する方法が提案されている
が、変換率が大きくなった場合には画質の劣化が目立っ
てのとじて、変換画素に対してオリジナル画素の前ライ
ン及び次ラインの2ライン分の画データの1)°を報を
考慮する方法をとり、簡単なアルゴリズムを適用し、ハ
ードウェアの規模を小さくし、更に画質劣化の要因であ
る白抜げ、黒孤立点、ジッタを軽減する為に、変換画素
を囲む4点のオリジナル画信号の主走査方向及びmll
走査方向及び対角線方向の不目関性に重点を置くことに
より上記欠点を軽減し、画質劣化を小さくする画素密度
変換機構な有するファクシミリ装置を提供するものであ
る。
To reduce the deterioration of image quality, there are the OR method, majority voting method, OPC method, SPC method, etc., which determine the pixel signal level of the converted pixel by considering the information of the previous line or the next line of the original pixel. However, in general, the algorithm becomes complicated and the hardware configuration becomes large.Furthermore, methods have been proposed to simplify the algorithm using this method, but when the conversion rate becomes large, the deterioration of image quality becomes noticeable. As a result, we adopted a method that takes into account 1) degrees of image data for two lines, the previous line and the next line of the original pixel, for the converted pixel, applied a simple algorithm, and reduced the hardware scale. In order to reduce white spots, isolated black points, and jitter, which are causes of image quality deterioration,
The object of the present invention is to provide a facsimile apparatus having a pixel density conversion mechanism that reduces the above-mentioned drawbacks and reduces image quality deterioration by placing emphasis on blindness in the scanning direction and diagonal direction.

(発明の構成) 本発明によると3ライン分の2値画信号を記憶できるメ
モリ回路と前記メモリ回路に記憶した2値画信号の変換
画素を囲む4点のオリジナル画素の主走査方向の2つの
2値画信号の論理積と副走査方向の2つの2値画信号の
論理積と対角線方向の2つの2値画信号の論理積を演算
する回路と、前記演算回路で得られた結果の論理411
を演算する演算回路を含み、前記結果が0か1かにより
変換画素の画信号を黒レベルか白レベルかに決定するこ
とを%畝とする画素密度変換機構を有するファクシミリ
装置が得られる。
(Structure of the Invention) According to the present invention, there is a memory circuit capable of storing three lines of binary image signals, and two pixels in the main scanning direction of four original pixels surrounding a converted pixel of the binary image signal stored in the memory circuit. a circuit for calculating the logical product of binary image signals, the logical product of two binary image signals in the sub-scanning direction, and the logical product of two binary image signals in the diagonal direction; and a logic of the results obtained by the arithmetic circuit. 411
The present invention provides a facsimile apparatus having a pixel density conversion mechanism that includes an arithmetic circuit for calculating , and determines whether the pixel signal of the converted pixel is at a black level or a white level depending on whether the result is 0 or 1.

(実施例) 次に、本発明の実施例について、図面を参照して説明す
る3、第1図は本発明のアルゴリズムを説明するもので
、画素密度を10 pet /fImから3 pel/
mmへ変換する場合である。オリジナル画素より、変換
画素′へ変換する場合の変換画素の画信号レベルを決定
する式を以下に示す。■を各変換画素の画信号(Δ)、
■をオリジナル画素の画信号(0)としたとき、各座標
上における■は、 Vi、j −v+、j ” vj、j Vj + ]、j ”” Vi+1.j ” vLl−
2,jVi、j+i −vi、j+t @ vj、jl
Vl+1.j+x −vLlx、j+x6vi+z、j
+t +vi+x、j+t1vi+l、j+2 +vi
+x 、j+1avi+z、j+2 +v i−+−z
、j+x°vi+1.j+2+vi+2.j+】 0v
i+2.2+z + v1+1.j+2”v1+2.ノ
+2・・・式(1) ここで6・”は論理積の演算子゛′+”は論理和の演算
子を示す。また画信号は黒レベルな0、白レベル1とす
る。式(1)で侍〜れた■の値がOならばその点の画信
号は黒、1ならば白とする。
(Example) Next, an example of the present invention will be described with reference to the drawings. 3. Figure 1 explains the algorithm of the present invention, and the pixel density was changed from 10 pet/fIm to 3 pel/
This is a case of converting to mm. The formula for determining the image signal level of a converted pixel when converting an original pixel to a converted pixel ' is shown below. ■ is the image signal (Δ) of each converted pixel,
When ■ is the image signal (0) of the original pixel, ■ on each coordinate is Vi, j −v+, j ” vj, j Vj + ], j ”” Vi+1.j ” vLl−
2, jVi, j+i -vi, j+t @ vj, jl
Vl+1. j+x −vLlx, j+x6vi+z, j
+t +vi+x, j+t1vi+l, j+2 +vi
+x, j+1avi+z, j+2 +v i-+-z
, j+x°vi+1. j+2+vi+2. j+] 0v
i+2.2+z+v1+1. j+2"v1+2.ノ+2...Equation (1) Here, 6." is a logical product operator, and ``'+'' is a logical sum operator.The image signal has a black level of 0, a white level of 1, and If the value of ■ in equation (1) is O, the image signal at that point is black, and if it is 1, it is white.

弐(1)に示すアルゴリズムは12 pe 1/+mが
ら8pel/xi への比較的、変換率が大きな場合に
おいて、オリジナル画素の主走査方向及び副走査方向及
び対角線方向に2つ以上の黒画信−号が連続して存在す
る赤変換画苑の画1g号を黒1,1号としているので、
白抜けが軽減される。款/こオリジナル画素が黒1点の
場合においては、最近傍の変換画素の画信号は白点とな
るので、黒孤立点の増大をおさえる効果及びジッタなど
による線分のぎざぎざを軽減する効果がある。本演算を
順次適用するこ)−VFh画害字昨勿く玖か勾外6とL
病げ盛1本発明の実′施例を第2図に示す。画イd号1
は、画信号クロック2及び同期信号3で1ライン単位に
同期をとられた後セレン・り回路4を経て1ライン毎に
ラインメモリ回路5へ導かれ3ライン分記憶される。こ
のとき、書込み、アドレスカウンタ回路13及び書き込
み1両回路11及びセレクタ回路10.15によりメモ
リ5への書き込み制御が行なわれる。
The algorithm shown in 2 (1) is based on two or more black image signals in the main scanning direction, sub-scanning direction, and diagonal direction of the original pixel when the conversion rate from 12 pe 1/+m to 8 pel/xi is relatively large. Since the painting No. 1g of the Red Conversion Art Garden where there are consecutive − numbers is Black No. 1, 1,
White spots are reduced. Clause/This: When the original pixel is one black point, the image signal of the nearest converted pixel becomes a white point, so this method has the effect of suppressing the increase in black isolated points and the effect of reducing jaggedness of line segments due to jitter, etc. be. Apply this calculation sequentially) - VFh
FIG. 2 shows an embodiment of the present invention. Picture d No. 1
The signals are synchronized line by line using the image signal clock 2 and the synchronization signal 3, and then led line by line to the line memory circuit 5 via the selenium recirculating circuit 4, where three lines are stored. At this time, writing to the memory 5 is controlled by the write address counter circuit 13, the write one and both circuits 11, and the selector circuits 10 and 15.

3ライン分記憶された後、読み出しアドレスカウンタ回
路工4、読み出し1釧1回路12VCより、ラインメモ
リ5から読み出された画信号6は各ライン単位で1ビツ
トシフト回路7でシフトされた後、演算回路8で式(1
)の演算を行ない、変換画百号9となる。
After 3 lines have been stored, the image signal 6 read out from the line memory 5 by the read address counter circuit 4 and the read 1 block 1 circuit 12 VC is shifted by 1 bit shift circuit 7 for each line, and then subjected to calculation. In circuit 8, the formula (1
) is performed and the converted image 9 is obtained.

また、第3図は画素密q8pel/ramから12pe
lfiaへの変換のアルゴリズムを説明するもので、オ
リジナル画素より変換画素−・変換する場合の変換画素
の画信号レベルを決定する式を以下に示す。Pを変換画
素の両信号、pをオリジナルt(1素の画15号と1、
たと鍍各座角ト匠粘吐ムI)はPilj ”” pil
j ・I)i、jPi+1.j−pl、j ”pi+1
.j+pi+1.j ’ I)i+1.j+1P l+
2+ip i+t + j リi+2+j +l)i+
1.j oPi+t、j−nPi、j+x −Pilj
−pi、j+1.+pi、j+iすi刊、」刊Pi+1
,3+t −pi、j 0−pi+1.j +pi、j
 #pi、j+i +1)i、j ” pi+x、j+
i “ pi+x、j ” p1+1.j+t 十pi
+l、j ” pi、j+1 +pi+1.j+1 ’
 pi、j+1Pi+z、j+1− Pi+1.j a
 pi+2.j + pi+1.j −pi+1.j+
1 +1)i+1.j ” I)i+2.j+1 +P
i+2.j ” pi+z、j+t 十pi+2.j 
” I)i+1.j+1 + pi+1.j+1 @P
I+2.j+IPi、j+2−1)i、j+x°pi、
j+z+pi、j+t°p用、」刊Pi+11j+2−
 pI、j+t ′ pi−H,j+x +pi、j+
t ′ I)i、j+z 十pi、j+x a I)i
+x、j+z +pi+x、j+t a I)i+l、
j+z +Pi+t、j+t # pi、j+2 +p
i、j+26 pi+x、j+2Pi+2. J+2−
 pi+t、j+t @ pi+2.j十t 十pi+
1.j+x l1r)i+x、j−+2+Pi+1.j
+1 ” Pi+2.j+2 +pi+2.j−H” 
pi+2.j+g 十りi+2.j七 l pi+1.
j十z 十pi+z、j+z 十pj+z、j+z・・
・式(2) この時、式(2)で得られたPの値が0ならばその点の
画信号は黒、1ならは白とする。本アルゴリズムの実施
は第2図の回路のうち演算回路8の演算方式(2)に対
応した形にするだけで可能である。
In addition, Figure 3 shows the pixel density from q8pel/ram to 12pe.
This is to explain the algorithm for conversion to lfia, and the formula for determining the pixel level of the converted pixel when converting from the original pixel to the converted pixel is shown below. P is both signals of the converted pixel, p is the original t (1 pixel No. 15 and 1,
Pilj "" pil
j ・I)i, jPi+1. j-pl, j ”pi+1
.. j+pi+1. j' I)i+1. j+1P l+
2+ip i+t + j rii+2+j +l)i+
1. j oPi+t, j−nPi, j+x −Pilj
-pi,j+1. +pi, j+isui publication, 'Published Pi+1
,3+t-pi,j0-pi+1. j + pi, j
#pi,j+i +1)i,j ” pi+x,j+
i “pi+x,j” p1+1. j+t ten pi
+l,j ” pi,j+1 +pi+1.j+1'
pi, j+1Pi+z, j+1- Pi+1. j a
pi+2. j + pi + 1. j-pi+1. j+
1 +1)i+1. j ” I)i+2.j+1 +P
i+2. j ” pi+z, j+t ten pi+2.j
” I) i+1.j+1 + pi+1.j+1 @P
I+2. j+IPi, j+2-1)i, j+x°pi,
For j+z+pi, j+t°p, Published by Pi+11j+2-
pI, j+t' pi-H, j+x +pi, j+
t ′ I)i, j+z tenpi, j+x a I)i
+x,j+z +pi+x,j+t a I)i+l,
j+z +Pi+t, j+t # pi, j+2 +p
i, j+26 pi+x, j+2Pi+2. J+2-
pi+t, j+t @ pi+2. j tent tenpi+
1. j+x l1r) i+x, j-+2+Pi+1. j
+1 ” Pi+2.j+2 +pi+2.j-H”
pi+2. j+g tenri i+2. j7 l pi+1.
j ten z ten pi+z, j+z ten pj+z, j+z...
- Equation (2) At this time, if the value of P obtained from Equation (2) is 0, the image signal at that point is black, and if it is 1, it is white. This algorithm can be implemented by simply modifying the circuit shown in FIG. 2 to correspond to the calculation method (2) of the calculation circuit 8.

(発明の効果) 本発明は以上説明したように各オリジナル画信号の主走
査方向及び副走査方向及び対角線方向に2点以上黒信号
がある場合に変換画素を黒信号にし、孤立点的な黒信号
は白信号としている為に白抜けがなくまた、黒孤立点の
項六、ジッタの増大をおさえることにより画質劣化の軽
減に効果がある。
(Effects of the Invention) As explained above, the present invention converts a converted pixel into a black signal when there are two or more black signals in the main scanning direction, sub-scanning direction, and diagonal direction of each original image signal, and blacks out isolated points. Since the signal is a white signal, there are no white spots, and it is effective in reducing image quality deterioration by suppressing black isolated points (6) and increase in jitter.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は画素密度12peしiから8pel/y*への
変換アルゴリズムを説明する図、第2図は不発1・・・
・・・2値画信号(オリジナル画信号)、2・・・・・
・画信号クロック、3・・・・・・画信号同期信号、4
・・・・・・セレクタ回路、5・・・・・・ラインの2
インメモリ回路・ 6°゛・・・メモリ読出し画信号、
7・・・・・・1ビツトシフトレジスタ回路、8・・・
・・・演算回路、9・・・・・・変換画信号、1o・・
・・・・セレクタ回路、11・・・・・・4f込み制−
回路、12・・・・・・読み出し制7By+回路、13
・・・・・・書込みアドレスカウンタ回路、14・・・
・・・読み出しアドレスカウンタ回路、15・・・・・
・セレクタ回路。 +7+lj’+17.’+7.i+11jiflJQ千
1図 J9ンナI、lす6’21j啼2 第3図
Figure 1 is a diagram explaining the conversion algorithm from pixel density 12 pe i to 8 pel/y*, and Figure 2 is a diagram explaining the conversion algorithm from pixel density 12 pe to 8 pel/y*.
・・・Binary image signal (original image signal), 2...
・Picture signal clock, 3...Picture signal synchronization signal, 4
...Selector circuit, 5 ... Line 2
In-memory circuit・6°゛・・・Memory readout image signal,
7...1-bit shift register circuit, 8...
... Arithmetic circuit, 9... Converted image signal, 1o...
...Selector circuit, 11...4f included system-
Circuit, 12...Reading system 7By+circuit, 13
...Write address counter circuit, 14...
...Read address counter circuit, 15...
・Selector circuit. +7+lj'+17. '+7. i+11jiflJQ111fig J9anna I, lsu6'21j啼2 Fig.3

Claims (1)

【特許請求の範囲】[Claims] 3ライン分の2値画信号を記憶できるメモリ回路と、前
記メモリ回路に記憶した2値画信号の変換画素を囲む4
点のオリジナル画素の主走査方向の2つの2値画信号の
論理積と副走査方向の2つの2値画信号の論理積と、対
角線方向の2つの2値画信号の論理積を演算する回路と
、前記演算回路で得られた結果の論理和を演算する演算
回路を含み、前記結果が0か1かにより変換画素の画信
号を黒レベルか白レベルかに決定することを%敵とする
画素密度変換機構を有するファクシミリ装置。
A memory circuit capable of storing 3 lines of binary image signals, and 4 pixels surrounding conversion pixels of the binary image signals stored in the memory circuit.
A circuit that calculates the logical product of two binary image signals in the main scanning direction, the logical product of two binary image signals in the sub-scanning direction, and the logical product of two binary image signals in the diagonal direction of the original pixel of a point. and an arithmetic circuit that calculates the logical sum of the results obtained by the arithmetic circuit, and determines whether the pixel signal of the converted pixel is a black level or a white level depending on whether the result is 0 or 1. A facsimile machine with a pixel density conversion mechanism.
JP58249176A 1983-12-26 1983-12-26 Facsimile equipment with picture element density converting mechanism Granted JPS60137171A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58249176A JPS60137171A (en) 1983-12-26 1983-12-26 Facsimile equipment with picture element density converting mechanism

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58249176A JPS60137171A (en) 1983-12-26 1983-12-26 Facsimile equipment with picture element density converting mechanism

Publications (2)

Publication Number Publication Date
JPS60137171A true JPS60137171A (en) 1985-07-20
JPH0325073B2 JPH0325073B2 (en) 1991-04-04

Family

ID=17189033

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58249176A Granted JPS60137171A (en) 1983-12-26 1983-12-26 Facsimile equipment with picture element density converting mechanism

Country Status (1)

Country Link
JP (1) JPS60137171A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6067950A (en) * 1996-10-29 2000-05-30 Kawasaki Jukogyo Kabushiki Kaisha Two-cycle engine and personal watercraft having it mounted thereon

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6067950A (en) * 1996-10-29 2000-05-30 Kawasaki Jukogyo Kabushiki Kaisha Two-cycle engine and personal watercraft having it mounted thereon

Also Published As

Publication number Publication date
JPH0325073B2 (en) 1991-04-04

Similar Documents

Publication Publication Date Title
JPS6110360A (en) Picture processing device
US5202670A (en) Image processing apparatus
JPS59156070A (en) Picture processing device
JPS6255137B2 (en)
US4937677A (en) Method of enlarging/reducing dithered images
US4710823A (en) Density conversion in image reproduction
EP0700196B1 (en) Method and apparatus for image scaling using parallel incremental interpolation
JPS60137171A (en) Facsimile equipment with picture element density converting mechanism
JPH01136465A (en) Picture processor
JPH04236568A (en) Edit processing system and equipment in picture reader
JPH04354068A (en) Method and device for interpolating picture data
JP2624262B2 (en) Printing equipment
JP2806043B2 (en) Pipeline image processing circuit
JPS63102467A (en) Converting device for resolution of picture data
JPH0525424B2 (en)
JP3216271B2 (en) Scan converter
JP3007521B2 (en) Halftone data generator
JP2903175B2 (en) Image processing device
JPH027113B2 (en)
JP3089857B2 (en) Image processing method used for halftone image reproduction
JPH0311881A (en) Picture element density converter
JPS61117591A (en) Apparatus for thinning out image data
JPH03225479A (en) Picture element interpolation circuit
JPS60236362A (en) Picture information processing method
JPH0496569A (en) Picture processor