JPH01136465A - Picture processor - Google Patents

Abstract

PURPOSE:To improve the processing speed by applying halftone gradation processing to a picture data at first and applying magnification/reduction processing through duplication or interleaving without storing a binary coded data into a memory subject to halftone gradation processing thereby saving the processing storing the picture data in the memory between the halftone gradation processing and the magnification/reduction processing. CONSTITUTION:A control circuit 7, when magnification is selected, uses a mode selection signal MS to command to mode of the dither value in response to the magnification to a dither pattern swing circuit 4 and commands the start of read of the picture to a picture read means 6. When the magnification is selected, a magnification signal output circuit 3 outputs a magnification signal CKF corresponding to the magnification. A comparator 2 compares a picture data AD with a dither value TH to output the binary data DD subject to halftone gradation tone processing to the latch circuit 5. In this case, the dither value TH is varied with the trailing timing of the magnification signal CKF. Thus, the latch circuit 5 latches the binary data DD at the trailing timing of the magnification signal DKF to output the output picture data PD subject to magnification/reduction processing.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus capable of performing image processing including both image enlargement/reduction processing and halftone processing.

(Prior Art) Recently, in the information age, processing of image data has become important, and image processing devices such as facsimile machines and copying machines have become widespread. In such image processing apparatuses, there has recently been a demand for image enlargement/reduction processing as well as halftone processing for reproducing halftone images such as photographs.

Conventional image processing devices that perform halftone processing as well as image enlarging/reducing processing generally first perform image enlarging or reducing processing, and then temporarily store the enlarged/reduced image data in memory. After that, it is read out from memory and halftone processing is performed using the dither method.

(Problems to be Solved by the Invention) However, in such conventional image processing devices, image data that has been enlarged/reduced is stored in memory and then subjected to halftone processing, which increases the processing time. This method is not only slow, but also requires a large capacity memory for image data that has been enlarged or reduced, which increases the cost of the image processing device.

That is, after image data that has been enlarged/reduced is stored in memory, it is read out from memory again and subjected to halftone processing, so it takes time to write to and read out the memory.
As a result, the processing time for image data was delayed. Also,
Image data obtained by reading a half-tone original is multi-tone data, and requires a memory capacity of 1 byte per pixel even when displayed with 8 bits per pixel. As a result, if enlargement/reduction processing is performed before halftone processing and stored in memory, a large capacity memory will be required and the cost of the image processing apparatus will increase.

(Object of the Invention) Therefore, the present invention first performs halftone processing on image data, and then enlarges and reduces the halftone-processed binarized data by duplicating or thinning out reading without storing the halftone-processed binarized data in memory. This eliminates the need to store image data in memory between halftone processing and enlargement/reduction processing, resulting in faster processing speed.
The purpose is to provide an inexpensive image processing device that does not require a large memory capacity.

(Structure of the Invention) In order to achieve the above object, the present invention includes a binarization means for comparing pixel data with a day value and outputting binary data;
A scaling signal output means for outputting a scaling signal that instructs thinning or redundant reading of specific pixel data according to a scaling ratio, and a scaling signal outputting means for storing a dither value and outputting the dither value to a binarization unit based on the scaling signal. The present invention is characterized by comprising a dither value output means for outputting a dither value, and an enlargement/reduction means for thinning out or redundantly reading the binary data output from the binarization means based on a scaling signal.

Hereinafter, the present invention will be specifically explained based on examples. FIGS. 1 to 8 are diagrams showing one embodiment of the present invention.

FIG. 1 is a diagram showing an image processing apparatus 1, and the image processing apparatus 1 is applied to a facsimile machine, a copying machine, etc. The image processing device 1 includes a comparator 2, a variable magnification signal output circuit 3,
The comparator 2 is provided with a dither pattern swing circuit 4 and a latch circuit 5, and image data (AD) is inputted to the comparator 2 from an image reading means 6 such as a facsimile machine. The image reading means 6 main-scans and sub-scans the original, and outputs a signal sequence of image data obtained by dividing the image of the original into a plurality of pixels as image data AD. Also,
The image reading means 6 can read halftone images such as photographs, and outputs multi-tone image data. Image reading means 6
outputs image data (AD) to the comparator 2 in synchronization with a clock signal (CK) from a control circuit 7 of a facsimile machine or the like. The comparator 2 compares the image data AD input from the image reading means 6 with the dither value (TH) input from the dither pattern swing circuit 4, and
It is converted into value data (DD) and output to the latch circuit 5. That is, the image data AD is subjected to halftone processing in the comparator 2 based on the dither value TH, and the comparator 2 constitutes a binarization means. The dither pattern swing circuit 4 determines a dither value TH based on the scaling signal CKF from the scaling signal output circuit 3 and the mode selection signal (MS) from the control circuit 7, and outputs it to the comparator 2.

The variable magnification signal output circuit 3 (variable magnification signal output means) is determined by the variable magnification input by the operator from the operation unit of a facsimile machine, copying machine, etc., the device conditions of the called terminal (for example, recording paper size), etc. A scaling signal CKF is generated based on the scaling factor and output to the dither pattern swing circuit 4 and latch circuit 5.

As will be described later, this scaling signal CKF is a signal that determines the timing for reading the binary data DD per pixel twice or thinning out the reading, and the dither pattern swing circuit 4 uses this scaling signal GK The dither value (TH) is changed based on , . As shown in FIG. 2, the dither pattern swing circuit 4 includes six shift registers (Lo) to (L,) and six multiplexers (Mo) to
(M,) It consists of an Oyohi counter (CT). Shift registers L0 to L each have a dither value (THAφ
-THHφ) -(THA5-THH5) are provided as modes, and the dither values selected by the mode by the multiplexer M3 from the control circuit 7 are output to the corresponding multiplexers M0-M, respectively. Multiplexer M0~M
, is a multiplexer with 8 manual outputs and 1 output, and this select section (A, B, C) receives a select signal (
QA, QB, QC) are input. The counter CT is a 3-bit up counter, and the scaling signal CK is input to its clock input. The counter CT is shown in Figs. 3 to 5 (Fig. 3 is at the same size, Fig. 4 is when reduced
Figure 5 shows the enlarged image. ), the variable magnification signal CK
The select signal QA changes every time , and the select signal QB changes at half the period of the select signal QA.
Furthermore, the select signal Q is output at half the period of the select signal QB.
C changes. That is, each multiplexer M, -M, as indicated by A-H in FIGS. 3-5.

sequentially outputs the dither values THA-THH inputted every cycle of the variable magnification signal CKF, and the dither pattern swing circuit 4 constitutes a dither value output means. Latch circuit 5
latches and outputs the binary data DD output from the comparator 2 at the rising timing of the scaling signal CKr from the scaling signal output circuit 3, and performs image enlargement/reduction processing. Therefore, the latch circuit 5 uses the binary data DD output from the comparator 2, which is a binarization means, based on the scaling signal.
It constitutes an enlargement/reduction means for thinning out and redundant reading.

Next, the effect will be explained.

The image processing apparatus 1 is applied to a facsimile machine or a copying machine as described above, and whether or not halftone processing is to be performed and the magnification ratio are determined by instructions from the operation unit. The present invention is characterized by processing when both halftone processing and enlargement/reduction processing are performed, and the operation will be described below assuming that halftone processing is selected. The control circuit 7 is
When the magnification ratio is selected, the dither value mode is instructed to the dither pattern swing circuit 4 by the mode selection signal M8 according to the magnification ratio, and the image reading means 6 is instructed to start reading the image. When a scaling factor is selected, the scaling signal output circuit 3 outputs a scaling signal CKr corresponding to the scaling factor. For example, in the same way as shown in FIGS. 3 to 5, the variable magnification signal C shown in each (a) of FIGS. 6 to 8
Output KF.

Figure 6 shows the same magnification, and the magnification change signal CK at this time
r is a signal synchronized with the clock signal CK and having the same period. FIG. 7 shows the magnification, and the magnification change signal CK at this time is the clock signal CK.

A signal with a period twice that of 1 appears every other signal. FIG. 8 shows the time of reduction, and the scaling signal CKr at this time is a signal with half the period of the clock signal CK. When the clock signal CK& is input from the control circuit 7, the image reading means 6 reads the image data AD at the rising timing of the clock signal CK, as shown in each of FIGS. 6 to 8 (b). is output to comparator 2. The image data AD and the dither value TH from the dither pattern/swing circuit 4 are input to the comparator 2, and the comparator 2 compares the image data AD with the dither value TH and transfers the halftone-processed binary data DD to the latch circuit 5. Output to. At this time, as described above, the dither value TH is the variable magnification signal CKF.
It changes at the falling timing of . The latch circuit 5 latches this binary data DD at the falling timing of the scaling signal CKF, and outputs output image data PD that has been subjected to enlargement/reduction processing. In the latch circuit 5, as shown by arrows in FIGS. 6 to 8, the comparator 2
The binarized image data AD (that is, binary data DD) is compared with the dither value TH that changes at the falling timing of KF, and is latched at the rising timing of the scaling signal CK, and output as binary data DD. There is. That is, at the same magnification, as shown in FIG. 6, the comparator 2 compares the sequentially inputted image data AD with the sequentially changing dither value TH and converts it into a binary value, and all of this binary data DD is stored by the latch circuit 5. It is latched and output. During enlargement, as shown in FIG. 7, the comparator 2 compares all of the sequentially inputted image data AD with the dither value TH and outputs it, but the dither value TH is doubled every other pixel of the image data AD. The comparator 2 compares it with this dither value TH and converts it into a binary value, and the latch circuit 5 latches and outputs all of this binary data DD. At the time of reduction, as shown in FIG. 8, the comparator 2 compares all the sequentially inputted image data AD with the dither value TH, but the dither value TH changes at half the cycle of the image data AD, and the comparator 2
is compared with this dither value TH and converted into a binary value, and the latch circuit 5
latches and outputs this binary data DD based on a scaling signal having a half cycle of this image data AD. In this way, the image processing device 1 compares the image data AD with the dither value TH that changes in accordance with the magnification ratio, performs halftone processing to generate binary data DD, and stores this binary data DD in the memory. The image is latched and enlarged/reduced according to the magnification ratio. Therefore, it is not necessary to store image data in memory between halftone processing and enlargement/reduction processing as in the conventional method, and processing speed can be improved. In addition, since there is no need for memory to store multi-tone data that has been enlarged or reduced as in the past, the memory capacity can be reduced, and the cost of memory and, by extension, the cost of the image processing device 1 can be reduced. can.

(Effects) According to the present invention, it is possible to omit the process of accumulating image data in memory between halftone processing and enlargement/reduction processing, thereby improving processing speed and eliminating the need for large memory capacity. First, the image processing device can be made inexpensive.

[Brief explanation of the drawing]

1 to 8 are diagrams showing one embodiment of the image processing apparatus of the present invention, and FIG. 1 is a configuration diagram of the image processing apparatus, and FIG.
The figure is a dither pattern/swing circuit diagram of the image processing device, and Figs. Figure 6~
FIG. 8 is a timing chart of the signals of each part at the time of equal magnification, enlargement, and reduction, respectively. 1... Image processing device, 2... Comparator (binarization means), 3...
... Magnification change signal output circuit (magnification change signal output means), 4...
... Dither pattern/swing circuit (dither value output means), 5... Latch circuit (enlargement/reduction means), 6...
. . . Image reading means, 7 . . . Control circuit.

Claims (3)

[Claims] (1) Binarization means that compares pixel data with a dither value and outputs binary data, and a scaling signal that outputs a scaling signal that instructs thinning or redundant reading of specific pixel data according to the scaling ratio. output means; dither value output means for storing the dither value and outputting the dither value to the binarization means based on the scaling signal; and thinning or thinning of the binary data output by the binarization means based on the scaling signal. An image processing device comprising: enlarging/reducing means for performing double reading. (2) Image processing according to claim 1, wherein the dither value output means has a dither value as a mode pattern, and sequentially changes and outputs the dither value based on the scaling signal. Device. (3) The image according to claim 1 or 2, wherein the enlarging/reducing means latches the binary data output from the binarizing means based on the scaling signal. Processing equipment.