JPS63168785A - Picture processor - Google Patents

Abstract

PURPOSE:To simplify the structure of a data processing means by adding boundary information to an address of the boundary of a processing area by an address generating means, transferring to a picture storing means and transferring data and the boundary information synchronously to the data processing means from the picture storing means at the time of reading picture data by the data processing means. CONSTITUTION:A first boundary information means 18 for transferring the boundary information of the processing area between the address generating means 101 and the picture storing means 104, 106, 108, and a second boundary information transferring means 19 for transferring the boundary information of the processing area between the picture storing means 104, 106, 108 and picture processing means 103, 105, 107 are provided. Namely, when the address generating means 101 generates the address of the data to be processed, information indicating whether the data to be processed is the boundary of an area to be processed or not is transferred to the picture storing means 104, 106, 108 synchronously therewith by the address generating means 101 and when the picture processing means 103, 105, 107 read the data to be processed from the picture storing means 104, 106, 108, the information indicating whether the data to be processed is the boundary of the area to be processed or not is transferred to the picture processing means 103, 105, 107 from the picture storing means 104, 106, 108.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an image processing device that can simplify the configuration of a data processing section.

2. Description of the Related Art Recently, as storage capacity increases, the field of handling uncoded images is rapidly developing.

FIG. 4 is a block diagram of a conventional example of an image processing device. 4
01 is an address generation unit, 402 is a program memory that stores processing content data, and 0 both are connected to the address line 41.
, and data lines 42. 403 is a data processing unit; an image storage unit 4 that stores image data;
The image data in 04 is being processed. Data processing section 40
3 and the image storage section 404 are connected to a data line 44. Similarly, the data processing unit 405
Process the image data within. The data processing section 405 and the image storage section 406 are connected by a data line 45.

Similarly, the data processing unit 407 processes image data in the image storage unit 408. The data processing section 407 and the image storage section 408 are connected by a data line 46. 47 is a control bus. This bus is commonly supplied to the image storage unit and data processing unit, and is a signal indicating whether the information on the address bus is an address for the original image or an address for the result image, or a read address. or a write address, and a synchronization signal.

A series of image storage units 404, 406, 408 and data processing units 403, 405, 407 operate based on this signal. Note that this control signal is sent out in synchronization with address generation.

This device operates as follows.

The address generation unit 401 sends the address of the instruction to be executed to the program memory 402 via the address line 41. As a result, an instruction to be executed is output from the program memory 402 via the data line 42, and this data is sent to the address generator 401, the data processor 403.
05 and 407 at the same time.

The address generation unit 401 includes image storage units 404, 406.
It generates an address for a region to be processed in the image stored in 408 and sends it to image storage units 404, 406 and 408 via address line 43. The data processing unit 403 receives image data corresponding to the address from the image storage unit 404 via the data line 44, performs processing instructed by the execution command, and creates resultant image data. Similarly, the data processing units 405 and 407 include the image storage unit 4
The image data to be processed is received from 06.408 via the data line 45.46, and the same processing as in 403 is performed to obtain the resulting image data.

The above result image data is written to the image storage units 404, 406, and 408 in synchronization with the address of the area where the result image output from the address generation unit 401 is to be stored. The above method is a method in which the address generation section and the data processing section are separated and made independent. This method allows the image storage section to have the same address space, so that one address generation section can be It is possible to add multiple data processing units. The image storage section is generally called a focus map memory, and for ease of explanation, it is assumed that one bit corresponds to one pixel, and the address increases to the right in the horizontal direction and to the bottom in the vertical direction.

Next, more detailed operations when image data is processed by the conventional apparatus shown in FIG. 4 will be explained with reference to FIGS. 5, 6, and 7.

FIG. 5 is a diagram for explaining the original image data stored in the image storage unit and the processing contents. In FIG. 5, 51 is an image storage section. 52 is an area with DX bits horizontally and Dy rows vertically, and the left end is the starting point (BPS).

This is a processing area of original image data whose right end is the end point (B PE). The original image data spans four words, Dy
The case where =9 will be explained as an example. 53a=e is a word boundary, and the image storage unit 51 has 16 bits as one word, is accessed word by word, and is processed horizontally line by line. Note that the starting point (BPS) can be located at any bit within one word, and the address of one word including the starting point and the bit position of the starting point are stored in variables ADDR and BPS, respectively. With the above settings, the operations of the address generation section and the data processing section when performing a process of calculating the number of elements having a value of 1 among the pixels of the original image are as follows.

FIG. 6 is a flowchart of the operation of the conventional address generation unit in the above-mentioned process. At 0601, the number of words (integer part) not including the end point in the horizontal direction is determined and stored in N. 6
In step 02, the end point bit position is found and stored in the BPE.

In step 603, an address is generated and accessed. In step 604, the number of words N is decreased by one.

In 605, it is determined whether the number of words N is O. If not, the address register is incremented by one at 606. Repeat the above operations from 603 to 60 until the incorrect number N becomes O.
Repeat step 6. If N is O in 605, it is determined in 607 whether BPE is 0 or not.

If BPE is not 0, the address register is incremented by 1 in 608 and the image data stored at this address is read in 0609. At 610, Dy is decreased by 1. In 611, it is determined whether Dy is 0 or not. If Dy is not 0, the address register is set to the left end of the next row and the whole operation is repeated until Dy becomes 0.

The processing in the first line of the processing unit 52 in FIG. 5 corresponds to the operation in the above flowchart as follows. That is, 6
Since 01.602 is an initial value setting, it is not directly related to the processing of the can opening of the image data. Address generation for the first word on the first row is performed in step 603. At 604 and 605, it is determined whether the processed word is the rightmost word. Therefore, at 606, the operation returns to 603 again.

From here, the process moves to the generation of the second word address. Similarly, the processes 603 and 604 for the third word are executed. After this, since the fourth word is the rightmost word, the process proceeds to 607 based on the determination in 605. The address of the rightmost word is generated at 608 and 609, and it is determined at 611 whether it is the last line. After this, the process proceeds to step 612 (Q). Here, the process moves to generation of the address for the first word in the second line. Hereinafter, the processing from the second line repeats the operation from the first word of the first line.

FIG. 7 is a flowchart of a conventional data processing section corresponding to the above-described processing. In FIG. 7, in step 701, the number of words (integer part) not including the end point in the horizontal direction is determined and stored in N. In step 702, the end point focus position is determined and stored in the BPE. In step 703, in order not to destroy data on the left side of the BPS, corresponding processing is performed on the left end. In step 704, the number of words N is decreased by one. In 705, it is determined whether the number of words N is 0 or not. If N is not 0, the process proceeds to step 706, where intermediate data in areas that do not include end point information is processed. Thereafter, the operations 704 to 706 are repeated until the number of words N becomes 0. When it is determined in 705 that the number of words N is 0, it is further determined in 707 whether or not the BPE is 0.

If BPE is not 0, proceed to 708, and in 708 BPE
In order not to destroy the data on the right side, process the right side accordingly. In 709, Dy is decreased by 1. 7
In step 10, it is determined whether Dy is O or not. Thereafter, the processes 703 to 710 are repeated until Dy becomes 0.

The above processing corresponds to the processing in the first line of the processing area 52 in FIG. 5 as follows.
After the processing in step 1.702, data processing for the first word in the first row begins. In processing this word, 703.704
．． The process ends after 705. Next, the process moves to data processing for the second word. The processing of this word consists of 706.704.7050 operations. In processing the third word, the work is 706.
Proceed to 707 via 704 and 705. This is 7
This is because in the determination of 05, it can be detected that the next word is the rightmost word. The processing for the fourth word is 707.708.
Proceed like 709.710. With the above, the processing of the first line is completed, and the processing of the second line is started again from 703.

Direct Problems to be Solved by the Invention In the conventional system as described above, both the address generation section and the data processing section hold and process the starting pit position (BPS) and the number of width bits (Dx). I had to. The address generation section uses these variables to calculate the number of words for the width of the image data to be processed, and the data processing section uses these variables to perform processing that does not destroy data outside the image area to be processed. is necessary. In FIGS. 6 and 7, 601.602.701.702 corresponds to this. Conventional methods such as this, in which the same variable is held in two or more locations and subjected to independent calculations, have the problem of complicated control.

The present invention solves the above-mentioned problems of the prior art, and aims to simplify control.

Means for Solving the Problems The present invention provides an address generation means for generating an address necessary for reading and writing image data in an area to be processed from an image storage means, and an address generating means for generating an address necessary for reading and writing image data in an area to be processed from an image storage means, and a method for processing this image data and generating a resultant image. first boundary information means for transferring boundary information of a processing area between the address generating means and the image storage means; The above object is achieved by providing a second boundary information transfer means for transferring the boundary information of the second boundary information.

Operation The present invention provides that when the address generation means generates an address of the data to be processed, the address generation means synchronously generates information as to whether or not the data to be processed is a boundary of an area to be processed. When the data to be processed is transferred to the image storage means and the image processing means reads data to be processed from the image storage means, it is synchronously determined whether the data to be processed is the boundary of the area to be processed or not. By transferring the information from the image storage means to the image processing means,
The process is performed using simple steps.

Embodiment FIG. 1 is a block diagram of an image processing apparatus of the present invention. 1
01 is an address generation unit that generates addresses and boundary information, and 102 is a program memory that stores a program for processing contents.0 Both are an address line 11 and a data line 1.
0103, which is tangent to 2, is a data processing unit that processes image data in the image storage unit 104 that stores image data. Similarly, data processing units 105 and 107 process image data in image storage units 106 and 108, respectively.

Address generation section 101 and image storage section 104.106.1
08 is tangentially connected to address line 13. 17 is a control bus. This bus 17 is commonly supplied from the address generation unit 101 to the image storage units 104, 106, and 108, and displays whether the information on the address bus is an address for an original image or an address for a result image. It consists of a signal, a signal indicating either a read address or a write address, and a synchronization signal. 22, Miyako, 24 each data processing unit 103.10
This control signal is output from 5.107 and is a signal for distinguishing between reading and writing.This control signal is sent out in synchronization with address generation. 14, 15 and 16 are data buses, and image storage units 104, 106
．． 108 and data processing units 103, 105, and 107, respectively. Signal lines 18.19.20.21 are paths for boundary information.

This device operates as follows. The 0 address generating section 101 sends the address of the instruction to be executed to the program memory 102 via the address line 41. As a result, an instruction to be executed is output from the program memo 'J 102 via the data line 12, and this data is transferred to the address generation section 101 and the data processing section 103.
．． 105 and 107 at the same time. The address generating section 101 generates an address of an area to be processed among the images stored in the image storage sections 104, 106, and 108, and sends an address to the image storage section 104.104.
106 and 108.

At this time, if the sent address is for the leftmost or rightmost word of the processing area, the address generator 1
01 outputs special information to the signal line 18. That is, if the sending address is the left end, the right end, or an intermediate word that is neither of these, 10.01 or 00 is output to the signal line 18, respectively. This 10 and 0
1 will be hereinafter referred to as the left end flag and the right end flag, respectively.

Furthermore, both of them will be collectively referred to as boundary flags.

The image storage units 104, 106, and 108 receive this boundary flag at the same time as the address, and store the address and boundary flag in association with each other. After this, the image storage units 104 and 106
．． At the stage of transferring data to be processed from 108 to data processing units 103, 105, and 107, image storage unit 10
4.106.108 synchronously outputs the boundary flag associated with the address for this data and this data, and determines whether the data to be processed is at the boundary of the processing area or not. 107. The data processing unit 103 transfers data from the image storage unit 104 to the data bus 1.
5 and the boundary information bus 19, the image data corresponding to the address and the boundary flag associated with the data are received, and the processing instructed by the execution command is performed depending on whether it is a boundary or not, and the resulting image is Get data. Similarly, data processing units 105 and 107 respectively have image storage units 106 and 107.
The image data to be processed and the boundary flag associated with the data are received from 108 via data buses 15.16 and 20.21, and the same processing as that in the data processing unit 103 is performed, and the resulting image data get.

The resultant image data obtained as a result is outputted in advance from the address generation section 101 and stored in the image storage sections 104, 106.
The resulting image held in 108 is written to the storage address.

Next, more detailed operations when processing image data by the apparatus of this embodiment will be explained using FIG. 5, FIG. 2, and FIG. 3.

FIG. 2 is a flowchart of the operation of the address generation unit 101 in the above-described process. At 0201, the number of words (integer part) not including the end point in the horizontal direction is determined and stored in N. 20
In step 2, the end pit position is found and stored in the BPE. 2
At 03, an address and a left end flag are generated. At 204, memory access is performed. In step 205, the number of words N is decreased by one. In 206, it is determined whether the number of words N is 0 or not.

If not, the address register is incremented by one at 207. At 208, memory is accessed. The above operations are repeated from 204 to 208 until the number of words N becomes 0. If N is 0 in 206, it is determined in 209 whether BPE is 0 or not. If BPE is not O, 2
At 10, the address register is incremented by one. At step 211, this address and the right end flag are generated. At 212, the address is memory accessed. In 213, Dy is reduced by 1. In 214, it is determined whether Dy is O or not. If Dy is not 0, the address register is set to the left end of the next line in step 215, and the entire operation is repeated until Dy becomes 0.

The processing in the first line of the processing area 52 in FIG. 5 corresponds to the operation in the above flowchart as follows. 201
．． Since 202 is an initial value setting, it is not directly related to the detailed processing of image data. Since the first word of the first line is at the left end, the memory is accessed at 0204, which is performed when the address of the first word is generated and the left end flag is generated at 203, and 205
．． At 206, it is determined whether the processed word is at the right end. Accordingly, via 207, operation proceeds to 208. From here, the process moves to the generation of the second word address.

Similarly, 208.204.205 for processing the third word.
processing is executed. After this, since the fourth word is the rightmost word, the determination at 206 is 210.211.2, which proceeds to 209.0 Address generation and rightmost flag generation for the rightmost word are 210.211.2.
12, and it is determined in 214 whether or not this is the last row. After this, the process proceeds to 215. Now, the process moves to generation of the address for the first word in the second line. Hereinafter, the processing from the second line repeats the operation from the first word of the first line.

FIG. 3 shows the data processing unit 103 that corresponds to the above-described processing.
105 or 107 is a flowchart. Third
In the figure, at 301, it is determined whether or not an end point flag is added to the input image data. If the end point flag has been added, the process advances to 302. In 302, it is determined whether the end point flag is the left end flag. If it is the left edge flag, proceed to 303, and in 303, in order to not destroy the data on the left side of the BPS, the left edge is processed accordingly.If it is the right edge flag in 0302, proceed to 304.
In step 304, in order not to destroy the data on the right side of the BPE, corresponding processing is performed on the right end. If the end point flag is not added in 301, proceed to 305 and proceed to 3.
In step 05, intermediate data processing that does not include endpoints is performed. From now on, repeat the above operation every time you input data.

The above processing corresponds to the processing in the first line of the processing area 52 in FIG. 5 as follows.

It is clear from FIG. 5 that the first word in the first row is the leftmost word. Therefore, the processing for this word is 301.30
2. After 303, return to 301 again.0 From here, data processing for the second word begins. Since this word is intermediate data that does not include endpoints, it passes through 301.305 and then returns to 301.
Return to From here, data processing for the third word begins. Similarly, since the third word is also intermediate data, the process returns to 301 via 301 and 305. From here, processing for the fourth word begins. Fourth
Since the word is the rightmost word, it returns to 301 again via 301.302.304. With the above, the processing of the first line is completed, and the processing of the second line is started again from 301.

Effects of the Invention As described above, in the present invention, the address generation means adds boundary information to the address corresponding to the boundary of the processing area, transfers it to the image storage means, and when the data processing means reads the image data, the data and the boundary information are combined. By synchronously transferring the data from the image storage means to the data processing means, the structure of the data processing means can be simplified. That is, there is no need for the data processing means to hold and process the starting point bit position (BPS) and the width bit number (Dx).

Furthermore, since the boundary information output from the address generation means is transferred to the data processing means via the image storage means, the address generation means and the data processing means do not need to operate synchronously, allowing high-speed and flexible processing. can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an image processing device according to an embodiment of the present invention, FIG. 2 is an operation flowchart of an address generation section which is a main part of the device, and FIG. 3 is a data processing diagram which is a main part of the device. FIG. 4 is a block diagram of a conventional image processing device, and FIG. 5 is a flowchart for explaining the original image data stored in the image storage unit and processing contents in the conventional example and an embodiment of the present invention. A conceptual diagram, Fig. 6 is an operation flowchart of the address generation section, which is the main part of the device, and Fig. 7 is a conceptual diagram.
The figure is an operation flowchart of the data processing unit, which is the main part of the device. 101...Address generation unit, 102...Program memory, 103.105.107...Data processing unit,
104.106.108... Image storage unit, 11.13
. . . address line, 12 . . . data line, 14.15.
16...Data bus, 17...Control bus, 18.1
9.20.21...Boundary information bus, 22, Otsu, 24
...Signal line for control signals. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1 Figure 2 Figure 3 Figure 4/40 Figure 5 Figure 6

Claims (1)

[Claims] an image storage means for storing image data; an address generation means for generating an address necessary for reading and writing the image data in an area to be processed; and an image processing means for processing the image data and obtaining a resultant image. , first boundary information transfer means for transferring boundary information of a processing area between the address generation means and the image storage means; and a first boundary information transfer means for transferring boundary information of the processing area between the image storage means and the image processing means. and a second boundary information transfer means for transferring the data, and when the address generation means generates an address of the data to be processed, it synchronously determines whether or not the data to be processed is the boundary of the area to be processed. When the address generation means transfers the information to the image storage means and the image processing means reads the data to be processed from the image storage means, the data to be processed is synchronously transferred. An image processing device that transfers information as to whether or not it is a boundary between regions from the image storage means to the image processing means.