JPH01307877A - Picture data processing system - Google Patents

Abstract

PURPOSE:To increase the picture transfer speed by storing an original picture in a picture memory in a storage means and operating OR between the original picture in a target position which is read out on the way of address generation and the picture in the storage means and writing the result in the picture memory. CONSTITUTION:A partial picture of the original picture in a bit map memory 2 is written as transfer data in a FIFO memory of the storage means while an address is generated through an address counter 5 and an address selector 6. OR between data in the target position of the memory 2 from an input buffer 10 and original picture data held in the FIFO 2 is operated and the result is written in the target position of the memory 2 through an output data buffer 11. Consequently, data is quickly transferred after the completion of address generation to increase the speed of data transfer to a destination area in the bit map memory in comparison with the data transfer speed for non-use of the storage means.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image data processing method, and particularly to an image data processing method for transferring image data within a predetermined area to another area.

[Prior Art] Normally, when transferring source data in an image memory (hereinafter referred to as source) to a destination position in the image memory (hereinafter referred to as destination), the source data is once logically connected to data on the destination side. The process of calculating the sum and writing is performed. That is, the process of reading out the source data, reading out the corresponding data on the destination side, ORing them, and then writing them into the destination position is performed on all the source data.

[Problems to be Solved by the Invention] However, when such processing is performed, a problem arises in that the throughput of the system, particularly the circuit and microprocessor that processes it, decreases.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide an image data processing method that makes it possible to improve the speed of image transfer.

[Means for Solving the Problem] In order to solve this problem, the image data processing method of the present invention has the configuration shown below.

That is, an image data processing method for transferring a source image in an image memory to a destination position, comprising: a memory holding means for reading and storing the source image in a predetermined address direction; an address generating means for generating an address at the target position;
At a first stage while two addresses are being generated, a logical operation means reads out the image at the target position and performs a logical operation on the original image held in the memory holding means; A writing means is provided for writing the result calculated by the calculating means into a position according to the address.

[Operation] In the configuration of the present invention, after the source image is held by the memory holding means, in the first stage while one address is being generated by the address generation means, the logical operation means combines the original image and the target image. It performs logical operations on the image, and in the second step writes the result of the logical operation to the address.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1. Schematic Description of Configuration (FIG. 1)> FIG. 1 is a circuit configuration diagram related to image data transfer in an embodiment. In the embodiment, an image processing apparatus will be described as an example.

In the figure, reference numeral 1 denotes a control unit that controls all of the constituent elements, and is provided with a memory storing therein a program related to the flowchart of FIG. 5, which will be described later. 2 is a bitmap memory for developing image data. 3 is an address bus composed of 20 bits, and 4 is a counter clock. 5 is address bus 3
Latch the address set in and start the counter clock 4.
This is an address counter that sequentially updates and outputs addresses in synchronization with the source and destination addresses. 6 is address counter 5
Either the address information from the address bus 3 or the address information on the address bus 3 is selected and the address information is stored in the bitmap memory 2.
This is an address selector that supplies the A memory controller 7 controls the output of a selection signal to the address selector 6 and a read signal and a write signal to the bitmap memory in synchronization with the counter clock 4 under the control of the control unit 1. 8 is a FIFO memory, 9 is an ALU that performs logical operations bit by bit, 10 is an input buffer for inputting destination data, and 11 is an ALU 9.
This is an output buffer for outputting destination data that is the logical operation result output from. 1
Reference numeral 2 denotes a data bus for exchanging data between various component devices including the bitmap memory 2, and in this embodiment, it is assumed to be composed of 16 bits.

Description of image data transfer (Figs. 2 to 5) In the above-described configuration, in the embodiment, as shown in Fig. 2, the source data in the rectangular area 20 in the bitmap memory 2 is transferred to the rectangular area 21 ( An example of transferring the internal data to destination data will be explained.

First, FIG. 3 shows the relationship between addresses and data. In the embodiment, 16 bits constitute one word, and data is transferred in units of words, but data may be transferred in units of bytes or smaller.

Now, in FIG. 3, it is assumed that both the source data and the destination data have a width of 4 words.

At this time, the leftmost address of the source data is represented by SAo, and the data (16-bit data) is represented by SD. Below, address S A.

SA2. The data for SA3 are S D ,, S D
2. It is expressed as SD.

On the other hand, the left end address of the destination data is represented by D A o and the data is represented by D Do.

Below, the addresses D A r, D A z, D
The data indicated by A s is D D I, D D z
, D D s.

The principle of transferring the source data to the location of the destination data in the embodiment is as shown in the figure, once these data are logically summed, and the data DD,° to DD3° obtained as a result of the logical operation is set as an address. D A
The processing is to store the data in o to D A s.

The details of the process to achieve this process are shown in Figure 1 below.
This will be explained based on the timing chart of FIG. 4 and the flowchart of FIG. 5.

First, the control unit causes the ALU 9 to output a signal to perform a logical sum operation. Although the explanation is confusing, this ALU is the control unit 1
It is possible to instruct various logical operations based on instructions from. Thereafter, the address selector 6 outputs a signal to the memory controller 7 that causes the address selector 6 to select an address from the address counter. Then, output the start address S A o of the source data to the address counter 5,
Counter clock 4 is raised to “H” (step S
2). Then, address counter 3 shows the previous address SA.
, is latched, and its address S A o is output to the bitmap memory 2. In addition, the memory controller 7
A counter clock 4 is supplied to the bitmap memory 2, and this signal is outputted as a read signal (an "L" level signal) to the bitmap memory 2 (step S2).

Now, when the address S A o and the read signal are output to the bitmap memory 2, the corresponding data SD0 is output onto the bus 12. Therefore, by setting the FIFOWR signal, which is a write signal to the FIF○ memory 8, to "L", the data is stored in the FIFO memory 8 (step S3).
By sending out the address, the address given to the bitmap memory 2 is updated to S A +, and the corresponding data SDI is stored in the FIFO memory 8 through similar processing.

Hereafter, in the same procedure, data S D *, S D s
is stored in the FIFO memory 8 (steps 82 to S4
).

In this way, one line of data in the source data is
When stored in the FO memory 8, the control unit 1 performs the following processing.

First, the start address D of the destination data
Output A o onto address bus 3 (step S5)
Then, the counter clock 4 is set to "H" and the address continues to be supplied to the bitmap memory 2. At the same time, the memory controller 7 outputs a read signal to output the corresponding data D Do onto the data bus 12 (step S6). At this time,
The control unit 1 sends an enable signal (
By outputting the "L" level signal), the data DD is latched and the data DD is output to one input side of the ALU 9. At this time, this enable signal is a read signal to PIFO8.
Since it is also a signal, the SDO in the previously stored data will be output to the other side of the ALU 9. As a result, the ALU 9 performs a logical operation (logical sum) according to the previously set logical operation mode, and outputs the result to the output data buffer 11 (step S7). When the bitmap memory 2 is stored (latched), the control unit 1 sends a read signal to the bitmap memory 2 to the memory controller 7 “H”.
In this way, when the data output from the bitmap memory 2 is disabled, the data DDO° latched in the output data buffer 11 is output onto the data bus 12, and this data is transferred to the bitmap memory 2. To store the data, the write signal (WR) is set to "L" (step S8). Thereafter, in preparation for the next data DD,', the counter clock 4 is set to "H" and the next data is stored in the bitmap memory 2. , and performs similar processing WP. Then, this processing is performed as address D A s
The process is repeated until (steps S6 to S9).

When the transfer process for one line of the source data is thus completed, the above-described process is performed until the lowest line of the source data is reached (step 510).

As in the above embodiment, the memory cycle depends approximately on the memory access time, and bit control can be performed in the shortest cycle, but since there is free time in the control section, other tasks can be processed during this time. It doesn't matter at all.

Also, in the above example, the width of the source data is 4 words, but it is not limited to this. In other words, the size of the source data (destination data) can be changed simply by changing the number of counter clocks. It is possible to do so.

Therefore, if the principle of the embodiment is applied to an image editing processing device that performs parallel translation of an image, it becomes possible to create a high-speed device.

Other embodiments (Figs. 6 and 7)> In Fig. 6, the bitmap memory 2 is replaced with a dynamic RAM.
(DRAM) An example of a 2° configuration is shown. In the figure, 25 is a known DRAM controller, 29 is a known DRAM address multiplexer, and 26 is a DRAM 2° RAM.
S signal 27 is a CAS signal of DRAM2'. The address counter shown as a component in the above embodiment is DR.
This is achieved by using a high-speed page mode that is already incorporated into DRAM as one of the general functions of AM. Note that the other structural elements are the same as the first one, so explanations will be omitted.

FIG. 7 shows a timing chart of the second embodiment.

Basically, it is the same as the first embodiment, but DRA
To read data from M2°, first read the start address S.
After applying A o to the address multiplexer 26, W
By setting the R times signal to "H" and outputting the CAS signal while supplying the address of the RAS component of the address S A o to DRAM 2° in the same way as normal DRAM access, the corresponding data SD , is obtained. Hereafter, in this RAS cycle, every time a CAS signal is output,
By incrementing the address one by one, data is output one after another onto the bus 12. During this time, similarly to the first embodiment described above, the data bus 12 Store the above data,
After this, the destination data address DA
With o as the initial value, this time the DRAM is
When the data DD within 2° is read and the logical operation is completed and the data is latched in the output data buffer 11, the WR multiplied signal to the DRAM 2' is set to "L". Similar processing will be performed.

In the second embodiment, in addition to the effects of the first embodiment, it is possible to reduce the number of parts and cost with a simpler structure.

In addition, in the embodiment, explanation was given using an example of an image processing apparatus, but
This can be done in the same way even when a printer having a bitmap memory receives a request to transfer an image once developed to another area.

[Effects of the Invention] As described above, according to the present invention, it is possible to perform image data transfer processing at high speed with a simple configuration.

Furthermore, by processing the transfer of the source image in units of partial images, it becomes possible to transfer the memory efficiently.

[Brief explanation of the drawing]

Fig. 1 is a main block configuration diagram related to image transfer in this implementation, Fig. 2 is a diagram for explaining the principle of image transfer, Fig. 3 is a diagram showing an outline of data processing in image transfer, and Fig. 4 is a diagram for explaining the principle of image transfer. 1 is a timing chart related to image transfer; FIG. 5 is a flowchart for explaining the operation processing of the control unit; FIG. 6 is a block diagram of another embodiment; FIG. 7 is a timing chart in FIG. 6. . 1...Control unit, 2...Bitmap memory, 3...
・Address bus, 4... Counter clock, 5...
Address counter, 6...Address selector, 7...
・Memory controller, 8...FIFO memory, 9・
...ALU1 10...Input buffer, 11...Output buffer, 12...Data bus.

Claims (2)

[Claims] (1) An image data processing method for transferring a source image in an image memory to a destination position, comprising: a memory holding means for reading and storing the source image in a predetermined address direction; , address generating means for generating an address at the target position; and in a first step while the address generating means is generating one address, an image at the target position is read out and stored in the memory holding means. Image data processing comprising: logical operation means for performing a logical operation on the original image; and writing means for writing the result of the operation by the logical operation means in a position according to the address in a second step. method. (2) The image data processing method according to claim 1, wherein the memory holding means stores and holds partial image units constituting the original image.