JPH0433172A - Image generation device with pattern memory - Google Patents

Abstract

PURPOSE:To execute a processing at high speed and to generate multiple synthesis patterns without increasing the types of the patterns by giving an image memory and a pattern memory and executing the parallel processing of an image and the patterns. CONSTITUTION:The image a1 and the pattern b1 are stored in a disk 18. CPU 19 reads the image a1 and the pattern b1 from the disk 18 and stores them in the image memory 11 and the pattern memory 12. A memory control part 13 simultaneously reads bit data from corresponding addresses in the memories 11 and 12 and outputs them to an AND gate 14. The output of the gate 14 is position-adjusted in an image position adjustment circuit 15, is ORed with data stored in a page buffer 17 in an OR circuit 16 and is stored in the buffer 17. Namely, data of the buffer 17 is zero at first and the synthesis pattern obtained by ANDing the image a1 and the pattern b1 is stored.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to an image generating device with a pattern memory,
In particular, the present invention relates to an image generation device with a pattern memory that creates an image different from the image by combining the image and a mask pattern.

(Prior Art) A conventional image generating device is comprised of an image memory 1, an image position adjustment circuit 2, a logic circuit 3, and a page buffer 4, as shown in FIG. 5
is a disk containing various images and patterns, such as the image 81% shown in FIG.
g2% patterns b1, b2, etc. are stored as dot data.

A CPU 6 controls the operations of the disk 5, image memory 1, and image position adjustment circuit 2.

Note that when the image generating device is combined with a printer and creates data to be supplied to the printer, the image generating device shown in FIG. 4 (
The image in a) is called data representing the shape, and the image in the same figure (b)
) patterns are sometimes called data representing so-called ink density. In other words, by appropriately combining the image in Fig. 4(a) and the pattern in Fig. 4(b) and applying AND logic, it is possible to give the density of Fig. 4(b) to the shape in Fig. 4(a). I can do it.

When creating an image as shown in FIG. 5, for example, using the image generating device configured as described above, the following two methods have conventionally been used.

(1) Put pattern C in FIG. 5 on the disk 5 and transfer it to the image memory 1. At this time, the logic circuit 3 is set as an OR circuit. Next, the data of pattern C is read from the image memory 1, and after being appropriately positioned by the image position adjustment circuit 2, it is written into the page buffer 4 via the OR circuit 3.

(2) The disk 5 does not have the pattern C shown in FIG. 5, but has the image al and pattern b1 shown in FIG. 4. First, image a1 is transferred from disk 5 to image memory 1. Next, the logic circuit 3 is set as an OR circuit, the data of pattern a1 is read out from the image memory 1, and the image position adjustment circuit 2 adjusts the position appropriately.
The data is written to page buffer 4 via .

Next, pattern bl is transferred from disk 5 to image memory 1.
Transfer to. At this time, the logic circuit 3 is set to an AND circuit, the data of pattern b1 is read from the image memory 1, and the image position adjustment circuit 2 adjusts the position appropriately, and then
Image 1 is read from page buffer 4, image 1 and button b1 are processed by AND circuit 3, and then written to page buffer 4.

As a result, the page buffer 4 stores a pattern obtained by ANDing the image a1 and the pattern b1. That is, the pattern shown in FIG. 5 is obtained in the page buffer 4.

(Problems to be Solved by the Invention) The method (1) has a problem in that the number of patterns held on the disk 5 increases, and the capacity of the disk 5 occupied by the patterns increases. Furthermore, in order to hold the pattern on the disk 5, it is necessary to create the pattern and store it on the disk 5, which is troublesome.

The problem with method (2) is that the processing speed is twice that of method (1). Furthermore, when trying to create a pattern as shown in FIG. 6 using method (2), there was a problem that it could not be created.

That is, if you first create pattern CI in the page buffer 4 as described above, and then sequentially combine image a2 and pattern b2 of FIG. 4 with it to create the pattern of FIG. After reading a2 and adjusting the position in the image position adjustment circuit 2, it is synthesized with pattern CI using OR logic.Then, the pattern b2 is read from the disk 5, and after the same position adjustment is performed in the image position adjustment circuit 2, AND logic is applied. It is possible to synthesize it with However, in this method, part of C2 and C3 of pattern c1 is deleted, and the pattern shown in FIG. 6 cannot be obtained.

The purpose of the present invention is to eliminate the problems of the conventional device described above,
To provide an image generating device with a pattern memory capable of processing at high speed and creating a large number of composite patterns without increasing the types of patterns prepared on a disk.

(Means and operations for solving the problem) In order to achieve the above object, the present invention provides a storage means for holding a plurality of basic images and patterns, and a storage means for storing the images and patterns read from the storage means. The present invention includes an image memory and a pattern memory, a control means for controlling simultaneous reading of data from the image memory and the pattern memory, and a logic circuit for logically processing the data read from the image memory and the pattern memory. It has characteristics.

According to the invention, selected images and patterns are read from said storage means, each transferred to an image memory and a pattern memory respectively, and then read simultaneously. The read data is synthesized by a logic circuit, such as an AND circuit, and sent to the next stage circuit.

As described above, the present invention is equipped with an image memory and a pattern memory, and can process images and patterns in parallel. Therefore, the processing speed is high, and patterns that cannot be created with conventional devices can be created by compositing processing.

(Example) The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In the figure, 11 is an image memory, 12 is a pattern memory, 13 is a memory control section, and 14 is an AND gate. Further, 15 is an image position adjustment circuit, 16 is an OR circuit, and 17 is a page buffer. Furthermore, 18 is a disk in which the images al, a2, patterns bL, b2, etc. are stored, 19 is a CPU, and 20 is a page buffer control unit.

Next, the operation of creating the pattern shown in FIG. 5 will be explained according to this embodiment.

The CPU 19 reads the image a1 and the pattern b1 from the disk 18 and stores them in the image memory 11.
and stored in the pattern memory 12. When this storage is completed, the memory control unit 13 simultaneously reads bit data from the corresponding addresses of the image memory 11 and pattern memory 12 and outputs them to the AND gate 14.

The output of the AND gate 14 is position-adjusted by an image position adjustment circuit 15, and processed by an OR circuit 16 with the data stored in the page buffer 17, and then stored in the page buffer 17. That is, since the data in the page buffer 17 is initially 0'', the page buffer 17 stores data obtained by ANDing the image a1 and the pattern b1.

As a result, pattern C in FIG. 5 is stored in the page buffer 17 at a predetermined position.

As described above, since this embodiment is equipped with the image memory 11 and the pattern memory 12, it is possible to read out the image a1 and the pattern b1 from these memories simultaneously, and the above-mentioned data can be read out in about half the time compared to the conventional device. It is possible to create pattern C. Furthermore, since the disk 18 does not need to have the pattern C shown in FIG. 5, the storage capacity of the disk 18 can be saved.

Next, the operation of creating the pattern shown in FIG. 6 will be explained according to this embodiment.

After forming the pattern C1 in FIG. 5 or the pattern c1 in FIG. 6 in the page buffer 17 by the above processing,
CPU 19 reads image a2 and pattern b2 from disk 18 and stores them in image memory 11 and pattern memory 12, respectively. When the image a2 and pattern b2 have been stored in the image memory 11 and pattern memory 12, the memory control unit 13 simultaneously reads bit data from the corresponding addresses in the image memory 11 and pattern memory 12, and inputs the bit data to the AND gate 14. Output.

The output of the AND gate 14 is sent to an image position adjustment circuit 15.
The position is adjusted by the OR circuit 16 and the page buffer 17 is
The data is logically summed with the data stored in the page buffer 17 and stored in the page buffer 17 again. As a result, the page buffer 17 has a pattern c as shown in FIG.
A pattern is obtained by combining l and pattern d.

As described above, according to this embodiment, the image a1 and the pattern bl can be logically combined, and the image a2 and the pattern b2 can be logically combined by the logical sum. It is now possible to create a pattern like the one shown in Figure 6, which was previously not possible.

FIG. 2 is a flowchart showing the operation of the embodiment.

In step S1, an image al is stored in the image memory 11.
The operation of writing the pattern bl into the pattern memory 12 is performed. In step S2, data is simultaneously read from the image memory 11 and pattern memory 12 and sent to the AND gate 14.

In step S3, the image position is adjusted, and the logical sum circuit 16 performs logical sum processing with the data stored in the page buffer 17 and writes the result to the page buffer 17.

Next, in step S4, an operation is performed to write the image a2 into the image memory 11 and the pattern b2 into the pattern memory 12. In steps S5 and S6, operations similar to those in steps S2 and S3 are performed.

Through the above operations, a pattern as shown in FIG. 6 can be obtained in the page buffer 17.

In the above embodiment, the outputs of the image and pattern memories 11 and 12 are sent to the AND gate 14, but the present invention is not limited to this, and the AND gate and the OR gate are connected in parallel. They may be provided so that one can be selected, or they may be combined.

(Effects of the Invention) According to the present invention, there is an effect that basic images and patterns can be synthesized at high speed. Furthermore, since only basic images and patterns need to be stored on the disk, the storage area of the disk can be used effectively.

Furthermore, there is an effect that patterns that could not be created using conventional devices can be obtained through the synthesis process.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a flowchart for explaining the operation of the embodiment, Fig. 3 is a block diagram showing an example of a conventional device, and Fig. 4 is a basic Figures 5 and 6, which show examples of images and patterns, show patterns obtained by combining basic images and patterns. 11... Image memory, 12... Pattern memory, 13... Memory control unit, 14... AND gate,
15... Image position M adjustment circuit, 17... Page buffer, 18... Disk, 19... CPU agent Patent attorney Michito Hiraki Outside 18 Diagram dimensions

Claims (1)

[Claims] (1) An image generator with a pattern memory that creates a new pattern by reading and combining arbitrary images and patterns from a storage means that stores a plurality of basic images and patterns, an image memory and a pattern memory in which images and patterns are stored; a control means for controlling simultaneous reading of data from the image memory and the pattern memory; and logic for logically processing the data read from the image memory and the pattern memory. An image generating device with a pattern memory, characterized by comprising a circuit.