JPH09169150A - Developing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a developing circuit that increases time resource of a microprocessor. SOLUTION: Destination data stored in a destination register 26 and a calculation result (raster data) of a calculator 28 are compared with each other. A comparator 30 that outputs a signal of (1) as a conformity signal to a bus- control circuit 23 when the destination data and the raster data are in conformity with each other and the bus control circuit 23 that stops the execution of a write cycle for transferring the raster data to an image memory when receiving the signal of (1) as the conformity signal and advances into the next operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a developing circuit used in a page printer or the like.

[0002]

2. Description of the Related Art Conventionally, a printer combines raster data (finally printed image data) by combining destination data (data already existing at a print position) and source data. -Ta) is being created. This is a process necessary for performing existing print data and overprinting on the existing print data. A printer such as a page printer having a function of creating raster data by combining the destination data and the source data will be described.

The page printer is provided with a microprocessor for controlling the members inside the printer. DRAM is connected to the microprocessor.
This DRAM comprises a working memory for temporarily storing the working data of the microprocessor and an image memory for storing the printing data for the printing position. This D
The print data for the print position is transferred from the font ROM to the image memory of the RAM. Although the image memory is initially empty, when data for a print position is stored, the data already exists at the print position.
Become The data already existing at this printing position will be referred to as destination data hereinafter.

The destination data is then D
Each word width of the RAM is transferred to the destination register of the graphic controller, and temporarily stored there for calculation.

When creating raster data, the graphic controller first executes an operation between the source data held in the graphic controller and the mask data, and further An operation is performed between the operation result and the destination data stored in the destination register. The result of this operation is stored in the raster data register in the graphic controller.

After that, a write cycle for writing back the raster data to the image memory occurs, and the operation result stored in the raster data register is returned to the image memory as raster data again and sent to the graphic controller. It is written in the place where the destination data before storing was stored. That is, the destination data stored in the image memory is transferred to the graphic controller, is operated, and then returns to the image memory again to be written back to the same position. The above series of operations is called "expansion", and the circuit that performs "expansion" is the "expansion circuit".
And

[0007]

In the above conventional expansion circuit, the destination data stored in the image memory before being transferred to the graphic controller and the image data calculated by the graphic controller are used. Even if the raster data returned to the memory is the same data, a write cycle for unconditionally writing the raster data back to the image memory occurs. Therefore, there is a problem that the processing time of the microprocessor is unnecessarily consumed for the time for generating the write cycle.

[0008]

In order to solve the above-mentioned problems, the solving means provided by the present invention calls the data stored in the storage unit, performs a predetermined calculation, and executes the above-mentioned data before the calculation. In the expansion circuit that writes back the data after the operation to the position where the data was stored, the data before the operation and the data after the operation are
Comparing the data before calculation with the data before calculation and outputting the comparison result of whether or not the data after calculation is equal, and the comparison result of the comparison means, the data before calculation When the calculated data is equal to the calculated data, a control means for stopping the operation of writing the calculated data to the position where the pre-calculation data was stored is provided.

After the operation, the pre-operation data is compared with the post-operation data. If they do not match, the control means sets the post-operation data at the position where the pre-operation data was stored. Write the data.

On the other hand, after the calculation, the data before the calculation and the data after the calculation are compared, and if they match, the control means calculates at the position where the data before the calculation was stored. The operation of writing the subsequent data is stopped.

[0011]

Embodiments of the present invention will be described with reference to the drawings. Elements common to the drawings are denoted by the same reference numerals.

FIG. 1 is a block diagram showing a configuration of a graphic controller according to an embodiment of the invention, FIG. 2 is a block diagram showing a control system of a page printer according to the embodiment of the invention, and FIG. 3 is an embodiment of the invention. FIG. 4 is an explanatory view showing an operation designation register in the embodiment of the present invention, FIG. 4 is an explanatory view showing configurations of an arithmetic unit and a comparator in the embodiment of the invention, and FIG. 5 is an explanation showing an image of a bitmap in the embodiment of the invention. It is a figure.

First, the control system of the page printer will be described. In FIG. 2, a microprocessor 3 is built in the control unit 1 shown by a one-dot chain line, and the microprocessor 3 controls the entire printer. A data bus 4 and an address bus 5 are connected to the microprocessor 3. The control unit 1 also executes a calculation according to a request from a font ROM 6 in which fonts are stored, a DRAM 7, and a microprocessor 3, and a result is DR.
A graphic controller 8 for writing on the AM 7 and a host interface 11 for receiving data from a host computer (not shown) are provided. The inside of the DRAM 7 is composed of a working memory 7a having a function of temporarily storing work data, and an image memory 7b for storing print data for a printing position.
Although the image memory 7b is initially empty, when the data for the printing position is stored, the data becomes the data already existing at the printing position. The data already existing at this printing position will be referred to as destination data hereinafter.

The font ROM 6 is a font ROM.
The bus 12a is connected to the data bus 4, and the font ROM bus 12b is connected to the address bus 5. The DRAM 7 is the DRAM bus 13, the graphic controller 8 is the graphic controller bus 14, and the host interface 11 is the host interface bus 1.
5 are connected to the data bus 4 respectively.

A gate 10 is provided between the DRAM 7 and the data bus 4, and the gate 10 causes D
The RAM 7 and the data bus 4 can be separated. The DRAM 7 and the graphic controller 8 are connected by a DRAM bus 13 and a DRAM / graphic controller bus 16.

The DRAM controller 9 has a control signal line 17
Connected to the address bus 5 by the control signal line 1
8 is connected to the DRAM 7. The DRAM controller 9 and the graphic controller 8 are connected by a control signal line 19 so that the graphic controller 8 can directly access the DRAM 7.

The graphic controller 8 is connected to the address bus 5 by a control signal line 20, and the signal of the control signal line 20 causes the graphic controller 8 to acquire the bus right from the microprocessor 3 and to set the font RO.
It becomes possible to directly access M6.

Next, the inside of the graphic controller 8 will be described. In FIG. 1, the graphic controller 8 is provided with a source address register 21 and a write address register 22, and the source address register 21 includes a font ROM 6 and a DRAM.
The address where the bit map data existing in 7 (hereinafter referred to as source data) is stored from the microprocessor 3 is stored. Write address register 2
2 receives the print start position of data from the microprocessor 3 and stores it. A bus control circuit 23 is configured by the source address register 21 and the write address register 22. The bus right is acquired from the microprocessor 3 according to the address of the source address register 21 and the address of the write address register 22, and the font ROM
6 and data read / write to the DRAM 7 are executed.

The graphic controller 8 also includes a source data register 24, a mask register 25, a destination register 26, and an operation designation register 2
7 are provided, and the source data register 24 is
For example, the source data obtained by accessing the address of the font ROM 6 shown in the source address register 21 by the bus control circuit 23 is temporarily stored for calculation. The mask register 25 receives a mask pattern (hereinafter referred to as mask data) for the effect of shading and painting from the microprocessor 3 and temporarily stores it for calculation.

The destination register 26 directly reads the destination data of the address specified by the write address register 22 from the image memory 7b on the DRAM 7 by the bus control circuit 23 and temporarily stores it for calculation. To store. Calculation specification register 27
Receives the operation data between the source data, the mask data and the destination data from the microprocessor 3 and stores them.

The graphic controller 8 further includes an arithmetic unit 28, a raster data register 29, and a comparator 30.
And the arithmetic unit 28 executes the arithmetic operation specified by the operation specifying register 27 among the source data register 24, the mask register 25, and the destination register 26. The result of this operation is stored in the raster data register 29, and the image is sent via the raster data register bus 36, the DRAM / graphic controller bus 16 and the DRAM bus 13 in accordance with the comparison result of the comparator 30 described later. It is stored in the memory 7b.

The comparator 30 stores the contents of the destination register 26 and the calculation result of the calculator 28 (raster data).
When the contents of the destination register 26 and the raster data match, "1" as the match signal "C" passes through the control signal line 31 and the bus control circuit 23.
Output to

FIG. 3 shows an example of the operation designation register 27. The least significant 3 bits (A0, A1, A2) are stored in the source data register 24.
Data is specified by shifting the number of bits to the right from the first bit of the write address and expanded, and the next 2 bits (A3,
A4) specifies the operation between the source data and the mask data, and the next 2 bits (A5, A6) are the operation result and the destination data between the source data and the mask data. −
Specify the calculation between data. The most significant 1 bit (A7) is not used. In FIG. 3, it is specified that the source data is expanded by shifting it by 4 bits to the right from the first bit of the write address, and the operation between the source data and the mask data is performed. It is specified that the AND operation, the operation result between the source data and the mask data, and the operation between the destination data are OR operations.

Next, the internal structure of the arithmetic unit 28 and the comparator 30 will be described.

In FIG. 4, the arithmetic unit 28 is provided with an arithmetic unit for each bit. In the present embodiment,
Since the expansion is executed in 8-bit units, 28a to 2
There are 8 arithmetic units up to 8h. Therefore, if the expansion is executed in 16-bit units, 16 arithmetic units are required.

SSn (n = 0, 1, ... 7) represents each bit of the result obtained by shifting the source data by the amount designated by the shift amount of the operation designation register 27, and Mn (n = n
0, 1, ... 7) represents each bit of the mask register 25, and Dn (n = 0, 1, ... 7) is a destination.
Each bit of the option register 26 is represented. Although the eight computing units 28 are provided from 28a to 28h, the internal configuration of the computing unit 28 is the same for all computing units 28a to 28h. To do.

The arithmetic unit 28a has a source bit SS0.
From the source data register 24 by a shift calculator (not shown) to bits A0, A1, A2 of the calculation designation register 27.
The result obtained by shifting by the number of bits designated by is received, the mask bit M0 is received from the mask register 25, and the destination bit D0 is received from the destination register 26. In addition, the computing unit 28a is
Bits A3, A4, A5, and A6 are assigned to the operation designation register 27
To receive from. Bits SS0 and M0 are AND gates 44
a, an OR gate 45a, and an EXCLUSIVE OR gate
46a. The AND gate 44a, O
The output terminals of the R gate 45a and the exclusive OR gate 46a are connected to the respective input terminals A, B, C of the first selector 47a, and the first selector 47a has its input terminal. Select one from A, B, and C. This selection is made by bit A of the operation designation register 27.
3, determined according to the value of A4. In the present embodiment, bits A3 and A4 of the operation designation register 27 are AN
Since the D operation is designated, the output from the AND gate 44a is input to the first selector 47a, and
The calculation result is output as the source mask bit SM0.

Source mask bit SM0 and destination
The transition bit D0 is inputted to the AND gate 48a, the OR gate 49a, and the exclusive OR gate 50a. The AND gate 48a, OR gate 49a,
The output terminals of the exclusive OR gate 50a are respectively the input terminals A of the second selector 51a,
The second selector 51a, which is connected to B and C, selects one of the input terminals A, B, and C. This selection is determined according to the values of the bits A5 and A6 of the calculation designation register 27. In the present embodiment, the bits A5 and S6 of the operation specifying register 27 specify the OR operation, so that the second selector 51a has the OR gate 4
The output from 9a is input, and the operation result is output as raster bit R0. Further, the destination bit D0 is also output from the calculator 28a.

A3 and A of the calculation designation register 27
The gates can be switched by changing the value of each bit of 4, A5 and A6.

Operation unit 28 (28a, 28b, ... 28)
h) is connected to the raster data register 29 and the comparator 30, and each of the second selectors 51a, 51b, ...
Output from 51h (raster bits R0, R1, ...
R7) is input to the raster data register 29, and is also input to the eight exclusive NOR gates 35a, 35b ... 35h of the eight comparators 30, respectively. This EXCLUSIVE NOR gate 35a,
35b, ..., 35h also include respective computing units 28a, 28
b, ... Destination bit D from 28h
0, D1, ... D7 are also input.

And, this eckle-sive NOR game
35a, 35b, ... 35h output terminals are AND
It is connected to the gate 37. The destination bits D0, D1, ... D7 and the raster bit R
If 0, R1, ..., R7 all match, the comparison result data output from the exclusive-NOR gate 35 to the AND gate 37 is "0xFF", and the destination is If any of the bits D0, D1, ... D7 does not match the raster bits R0, R1, ... R7, the comparison result data output from the exclusive NOR gate 35. Is other than "0xFF".

The AND gate 37 outputs the coincidence signal C, and the exclusive NOR gates 35a, 35b, ... 35 input to the AND gate 37.
Operation bits C0, C1 ... C7 from h are all "1"
, The coincidence signal C from the AND gate 37 is HIGH ("1"), and one or more exclusive NOR gates 35a, 35b, ... 35.
When there is a value other than "1" in the operation bits C0, C1, ... C7 from h, the coincidence signal C from the AND gate 37 becomes LOW ("0").

The comparator 30 is described as receiving the destination data from the arithmetic unit 28 in FIG. 4, and is also received from the destination register 26 in FIG. . However, this is for convenience of description, and the comparator 30 receives the destination data from the arithmetic unit 28.

The reason for shifting the source data is that the characters are left-justified in the font ROM 6 and are shifted by a predetermined amount to be positioned at a desired position. Therefore, this shift amount is not fixed.

Next, the processing for creating the raster data is shown in equation (1).

R = {(S >> 4) & M}: D (1) In the above mathematical expression (1), “>>” represents a shift, “&” represents a logical product, and “:”. ] Represents the logical sum.

Table 1 summarizes the data operation for each row when the source data, the mask data, the destination data, and the raster data are shown in FIG. 5, respectively. The numbers 1 to 8 at the beginning of each line are the source data.
The number of rows of data, mask data, and destination data is represented, and "S", "M", "D" at the beginning of each column,
"R" and "C" respectively represent source data "S", mask data "M", destination data "D", raster data "R", and coincidence signal "C". There is. Note that FIG. 5 shows the image of the bitmap read into each register of the graphic controller 8 and the image of the bitmap after the operation in the form of an 8 × 8 rectangular area for the purpose of explanation. , The source data is "S", the mask data is "M", the destination data is "D", and the raster data which is the operation result is "R".

Also, in this example, the source data is moved to the right by 4
The logical product of the dot-shifted data and the mask data is logically summed with the destination data to obtain raster data.

Next, Table 1 will be described by taking the first and second rows as an example.

[0040]

[Table 1]

In the first line, the source data is "0x42",
Mask data is "0x55", destination data
Since the data is "0x11", first the source data is shifted by 4 bits to become "0x04", and an AND operation is performed with this and the mask data. Then, the result is "0x0
4 ”. This result and the destination data "0
x11 ”and OR operation. Then, the result is "0x1
5 ”and stored in the raster data register 29.
At this time, since "D" and "R" are not equal, the coincidence signal "C" becomes "0".

In the second line, the source data is "0x44",
Mask data is "0xaa", destination data
Since the data is "0x22", the calculation result is "0x22" and is stored in the raster data register 29 when the calculation is performed in the same manner as in the first row. At this time, since "D" and "R" are equal, the coincidence signal "C" becomes "1". Less than,
Similarly, the calculation result of each row is shown in the “R” column, and the coincidence signal “C” is shown in the “C” column.

The microprocessor 3 uses the graphic controller 8 to execute operations between the source data and the mask data, and also execute various operations between the destination data and the destination data. Then, the operation of writing back the resulting raster data to the address of the original position again is performed. The above series of operations is called "expansion", and the circuit for "expansion" is called "expansion circuit".

Next, the data expanding operation in the above configuration will be described with reference to FIGS. First, when the power is turned on, the microprocessor 3 sends the working data of the microprocessor 3 to the working memory 7a via the DRAM bus 13. After that, the microprocessor 3 waits for data from a host (not shown).

Then, the character code to be printed (in this case, character "K") and the mask data are transferred from the host to the microprocessor 3 via the host interface 11. Then, the microprocessor 3
Finds a place where the character "K" is stored in the font ROM 6 and sets the address of the source address register 21 based on the data of the character "K".

Further, the microprocessor 3 stores the mask data transferred from the host in the mask register 25. Further, the microprocessor 3 determines where to print on the paper based on an instruction from the host, and sets the address of the print start position in the write address register 22.

Since the addresses have been set in the source address register 21 and the write address register 22, the bus control circuit 23 causes the microprocessor 3 to operate.
Control will be performed instead of. The expansion operation performed by the bus control circuit 23 will be described below with reference to Table 1 and FIGS. 1, 2, 3, 4, and 5 according to the flow chart shown in FIG. 6 and the time chart shown in FIG. explain. FIG. 6 is a flowchart showing the expanding operation in the embodiment of the invention.
FIG. 7 is a time chart showing the expansion operation in the embodiment of the invention.

In the present embodiment, the fourth and fifth lines will be described as an example. Also, after turning on the power,
The DRAM 7 is stored until the data for the print position is stored.
Since the image memory 7b is empty, all the data transferred from the image memory 7b indicates that there is nothing in the place to be printed. However, in this case, the destination data shown in FIG.
Data exists.

In step S1, the bus control circuit 23 returns
In cycle 1, access the 4th line of the source data of the character "K" searched from the font ROM 6 and select "0x
50 "is transferred to and stored in the source data register 24. At the same time, the bus control circuit 23 sends the destination data, in this case "0x88", to the image memory 7.
b to control signal lines 18 and 19 and DRAM buses 13 and D
Via RAM / Graphics controller 16
The data is transferred to and stored in the destination register 26 for each word width of the DRAM 7.

In step S2, the bus control circuit 23 stores the operation specification data "0x0C" in the operation specification register 27 between the source data, the mask data and the destination data. Here, the mask data has already been stored in the mask register 25 by the microprocessor 3. In step S3, the operation determination cycle 1 is executed and the bus control circuit 23 performs the operation. This arithmetic operation is performed by the arithmetic operation unit 28 by the arithmetic operation designation register 27 based on the above equation (1).

Source data "0x50", mask data "0xaa", destination data "0x88".
When the above equation (1) is applied, the source data is shifted to the right by 4 bits, the source data becomes "0x05", and the operation designation of the source data and the mask data is Since it is an AND operation, the source mask data is "0x00". Since the destination operation designation is an OR operation, the raster data is "0x88" as a result of the OR operation of the source mask data and the destination data. In step S4, "0x88" is stored in the raster data register 29.

In step S5, the comparator 30 sets the destination
Each bit of the motion data and the raster data is compared. For comparison, first, exclusive-NOR operation is performed on the destination data and the raster data. Then, the result of this calculation (comparison result data) is set to the AN by the AND gate 37.
Calculate D. In step S6, it is determined whether "1" is output from the AND gate 37 as the coincidence signal C to the bus control circuit 23 via the control signal line 31. In this case, since all bits of the destination data and the raster data match, the operation result data is "CxF".
F ", and" 1 "as the coincidence signal C is the bus control circuit 2
3 is output. The bus control circuit 23 stops the execution of the write cycle 1 by this signal, and judges whether or not the expansion operation for one character is completed in step S7. Since it is "no", the process proceeds to step S9 and the next line The source data address and the destination data address are changed for access.

Then, the process returns to step S1 and immediately returns.
In cycle 2, the source data and the destination data on the fifth line are accessed.

In the fifth line, the destination data is "0x10" and the raster data is "0x15".
Since the destination bit D0 is not equal to the raster bit R0 and the destination bit D2 is not equal to the raster bit R2, the comparison result data is "0xFA".
Since the comparator 30 does not output "1" as the coincidence signal C to the bus control circuit 23 in the calculation / judgment cycle 2, the process proceeds from step S6 to step S8. Step S
At 8, the bus control circuit 23 executes the write cycle 2 and writes the raster data “0x15” to the write address register 2
Write to 2. Then, the write position of the raster data "0x15" to the image memory 7b is designated by the control signal lines 18 and 19, and the raster data register bus 3 is also designated.
6, DRAM, graphic controller bus 16, D
The raster data "0x15" is transferred to the designated position in the image memory 7b via the RAM bus 13 and stored therein.

When the above operation is repeated and the expanding operation is completed up to the eighth line, the expanding operation for one character is completed in step S7.

Further, in the above-described embodiment, the source data is originally incorporated by the graphic controller 8, but the microprocessor 3 directly supplies the source data.
It may be written in the data register 24.

As shown by the clock signal in FIG. 7, the fourth row requires 3 clock cycles. The first two clock cycles 61 and 62 are read cycle 1, in which the source data is read from the font ROM 6 and the destination data is read from the image memory 7b. The next one clock cycle 63 is a calculation / judgment cycle, in which raster data is created and it is judged whether or not the raster data and the destination data match. The fourth line is raster data and destination data.
Since "1" is output as the coincidence signal C, the write cycle 1 does not occur. Therefore, the expansion operation is completed in 3 clock cycles.

The fifth row requires 5 clock cycles.
The first two clock cycles 64 and 65 are the read cycle 2, and the next one clock cycle 66 is the operation / judgment cycle 2. In the calculation / judgment cycle 2, since the raster data and the destination data match, the next two clock cycles 66 and 67 become the write cycle 2. In this write cycle 2, raster data is stored in the image memory 7b.

In the comparator 30, the exclusive-NOR gate 35 is excluded-ORed.
A gate, and the AND gate 35 is also a NOR gate.
May be used.

In the above embodiment, when the destination data already existing at the print position matches the raster data to be newly written on the destination, the raster data is stored in the image memory 7b. There is no write cycle for transfer to the read cycle, and a read cycle for performing the next expansion operation. As a result, the processing time can be shortened and the time resources of the microprocessor are increased when performing overprinting.

The unit for comparing the destination data and the raster data is the unit in which the bus control circuit 23 accesses the image memory 7b by one access, that is, the reading and writing of the data once. By setting the unit (8 bits in this case) that can be performed in the shortest time, the processing can be performed efficiently.

[0062]

Since the present invention is configured as described above, it has the following effects. Comparing means for comparing the pre-computation data with the post-computation data, and outputting a comparison result as to whether the pre-computation data and the post-computation data are equal to each other; According to the comparison result of the comparing means, when the pre-computation data and the post-computation data are equal to each other, the post-computation data is written in the position where the pre-computation data was stored. By providing the control means for stopping
When performing overprinting on existing print data and the existing print data, the processing time can be shortened and the time resource of the microprocessor increases.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a graphic controller according to an embodiment of the invention.

FIG. 2 is a block diagram showing a control system of the page printer according to the embodiment of the invention.

FIG. 3 is an explanatory diagram showing an operation designation register according to the embodiment of the invention.

FIG. 4 is an explanatory diagram showing a configuration of an arithmetic unit and a comparator according to the embodiment of the invention.

FIG. 5 is an explanatory diagram showing an image of a bitmap according to the embodiment of the invention.

FIG. 6 is a flowchart showing a developing operation in the embodiment of the invention.

FIG. 7 is a time chart showing a developing operation in the embodiment of the invention.

[Explanation of symbols]

 1 Control Section 7 DRAM 7a Working Memory 7b Image Memory 8 Graphic Controller 28 Operation Unit 30 Comparator

Claims (2)

[Claims] 1. An expansion circuit for recalling data stored in a storage unit, performing a predetermined operation, and writing back the data after the operation to a position where the data was stored before the operation. And a comparison means for comparing the pre-computation data with the post-computation data and outputting a comparison result as to whether the pre-computation data is equal to the post-computation data. If the pre-computation data and the post-computation data are equal according to the comparison result of the comparison means, the post-computation data is stored at the position where the pre-computation data was stored. And a control means for stopping the writing operation. 2. The expansion circuit according to claim 1, wherein the data before the operation is compared with the data after the operation for each number of bits that can be accessed by one access.