JPH1021384A - Rendering processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a rendering processor in which the rendering processing of an image or a graphic can be operated at a high speed. SOLUTION: A rendering processor 4 is composed of a processor group in which processors which can process picture elements by plural bit units are arranged in parallel, and each processor is connected with a memory 5 through a bus 2. Each processor has each role, and processors 4-8, 4-9, 4-10, and 4-11 operate Z plane control, and output a mask signal to the other processors. Processors 4-2, 4-3, 4-4, 4-5, 4-6, and 4-7 which receive this mask signal generate picture data based on this mask signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a rendering processor for generating data to be displayed on a display control device such as a CRT display, and more particularly to a rendering processor for generating images and three-dimensional data at high speed.

[0002]

2. Description of the Related Art Conventionally, a number of processing systems have been proposed for a device that executes display control, especially drawing processing.

[0003] For example, an example described in Japanese Patent Application Laid-Open No. 59-229669 is an example in which image rotation processing is performed, and a method for obtaining coordinate values of a destination image corresponding to grid point coordinates of a source image. Is adopted. In this method, it is only necessary to have a linearly developed DDA circuit only for the (X, Y) coordinates of the destination,
Processing performance is determined by the size of the source image,
In addition, there is a problem that pixels of different grid points are written to one grid point of the destination many times, and conversely, pixels are not written.

Japanese Patent Publication No. 57-57715 discloses a method for obtaining the shading of each pixel inside a triangle to which a vertex density value is given. This method describes an embodiment in which the shading of a plane figure is realized by hardware.
Since memory access is performed every time a pixel is generated, there remains a problem in processing performance when a pixel is generated in parallel with a raster, such as a shedding process.

Japanese Patent Application Laid-Open No. 60-252394 discloses color pixels,
In particular, it shows a color image display device in which a memory plane has a variable configuration. This shows a method in which the bus configuration with the CPU can be constant regardless of the number of planes. However, since there is no arithmetic circuit independent for each plane, the performance of operations such as image processing is reduced. The problem remains.

[0006]

The above prior arts are designed to process graphics and images partially at high speed, but are not sufficient to integrate and process them. There is a point.

An object of the present invention is to provide a rendering processor capable of performing high-speed image and graphic rendering processing by connecting a DDA control circuit centering on linear development of graphics and hardware for raster operation of an image. It is in.

[0008]

SUMMARY OF THE INVENTION The object is a rendering processor having a plurality of processors and a plurality of frame memories coupled to each of the plurality of processors via a bus, wherein at least one of the plurality of processors is a processor. Is a processor that generates a mask signal, outputs the generated mask signal to another processor,
This can be achieved by the processor receiving the mask signal generating a destination image from the source image based on the mask signal.

Further, the above object comprises a plurality of processor elements arranged in parallel for processing a signal from a display control processor and reading and writing at least pixel data in a frame memory composed of a plurality of planes. The rendering processor, wherein at least one of the plurality of processor elements is a processor that generates a mask signal, and outputs the generated mask signal to another processor, and the processor that receives the mask signal includes the processor described above. This can be achieved by generating image data based on a mask signal.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a diagram showing a hardware configuration at the center of the present invention, FIG. 2 is a diagram showing a typical example of functions at the center of the present invention, and FIG. 3 is a diagram showing an overall system configuration. ,
FIG. 4 is a configuration diagram of a rendering processing unit that repeatedly uses the same hardware, and FIGS. 5 and subsequent drawings illustrate the configuration of each block in FIG. 1 in detail.

Before describing the hardware configuration that is the main component of the present invention, the position of the present invention in all systems will be described.

FIG. 3 is a diagram showing the overall configuration of a display system utilizing the present invention. 3, a main processor 10, a shared memory 11, a display control processor 12, a rendering processor 4, which performs pixel development, a frame memory 5, and a CRT 1 around a bus 16 as communication means of the main processor 10 and display hardware.
5 are connected as shown in the figure.

When the main processor 10 wants to display a picture on the CRT 15, the operation is performed according to the following operation flow.

First, the main processor 10 writes a picture command to be displayed on the shared memory 11. Thereafter, the main processor 1 is sent to the display control processor 12 via the bus 16.
0 activates.

The display control processor 12 has a shared memory 11
After the command is read and interpreted, the command is decomposed into smaller commands and sent to the rendering processor 4. The rendering processor 4 decomposes the data in pixel units,
The writing to the frame memory 5 is controlled. Since the contents of the frame memory 5 are always read out to the CRT 15,
The written contents are immediately displayed on the CRT.

Since the central part of the present invention is the rendering processor 4 for developing the pixel, the detailed configuration of this part will be described below.

FIG. 2 schematically shows the main functions of the rendering processor, in which (S) shows a source pixel and (D) shows a destination image.

Those having a depth in the image portion are indicated by images having a width.

First, the raster operation is performed on the source,
An operation in which the directions are the same and the size is the same for both destinations, so that a plurality of pixels can be processed at one time.

In the rotation, the source is in the horizontal direction, but the destination is inclined as shown in FIG.
/ M times.

The paint-out process is a process of writing the pattern information of the source by multiplying the source information by the frame information written in the destination.

[0023] The development of the broken line is painted out,
The difference is that the destination has a slope.

The above-described processing can be performed by each rendering processor with 4 bits per pixel.
In particular, the following is possible.

1) For the raster operation, 1
Six pixels can be read and written at once.

2) For the rotation, the source reads out 16 pixels at a time, and for the destination, it calculates and calculates only the continuous pixels up to a maximum of 16 pixels in the horizontal direction.
Finally, the writing process can be performed.

3) With respect to the painting, painting data for 16 pixels is generated and written into the frame memory.

4) In the same manner as in 2), the process of generating continuous pixels up to a maximum of 16 pixels in the horizontal direction of the destination can be performed by writing the data into the frame memory. Hereinafter, the configuration of each rendering processor will be described.

The rendering processor 4 has a pixel 4bi.
Processors capable of processing in units of t are constituted by a group of processors installed in parallel as shown in FIG.

Each processor is connected to the frame memory 5 by the bus 2, and all the processors are connected to the display control processor 12 only by the bus 1.

The rendering processors 4 are decomposed into the same processors 4-i (i = 1-... 11), and their roles are divided as follows.

Work plane control (for painting): 4-1 Red plane control: 4-2, 4-3 Green plane control: 4-4, 4-5 Blue plane control: 4-6, 4-7 Z plane control : 4-8, 4-9, 4-10, 4-11 Each rendering processor has a signal 41 indicating which plane each corresponds to, a data set via the bus 1 to each processor, Alternatively, a signal 42 for enabling the read to operate in synchronization is provided, and the signal 42 is output from the control unit of one master processor.

Next, the internal configuration of each rendering processor will be described with reference to FIG.

The processor calculates a control unit 21, a DDA calculation unit (address DDA 22, density / Z value DDA 23) for calculating the address and density information of each pixel, and calculates data for 16 pixels of one raster in the frame memory. Data control unit 27 (four DCU0 to DCU3 are placed in parallel in order to control four planes by one processor), a Z comparator 26 for comparing Z values, and which of the 16 pixels is written Master control unit 2 that generates a master
It is configured by a frame memory address control unit 24 that generates a frame memory address in units of 5, 16 pixels.

The outline of the operation of the rendering processor is as follows.

Commands and data from the display control processor 12 are transmitted to each rendering processor 4 via the bus 1.
Is set to the register inside. The processor 4 has two stages of registers for pipeline control, so that the next command or data can be set even during operation.

The display control processor 12 first sets necessary data in a register, and then sets a command in a command register.

For example, when developing a straight line of a constant color, the following data is set, and then a straight line developing command is set.

(1) Starting coordinate value of straight line development (Xs, Ys)
Is set in the register in the address DDA.

(2) The increment value (DX, Ds) of (Xs, Ys)
Y) is similarly set in the address DDA register.

(3) The number n of dots for linear development is set in a register in the control unit 21.

(4) Color information I of a straight line is expressed as density and Z value DDA2.
Set in the register in 3.

After the above data set, when a command for linear development is sent, the rendering processor performs the following operation.

(1) Among the coordinate values of (Xs, Ys), Xs
The lower 4 bits (corresponding to the address in 16 pixels of one raster) are decoded, the corresponding mask bit is turned off by the mask controller, and the color information I of the corresponding pixel is set in the register in the data controller. I do.

(2) An operation of Xs = Xs + DX Ys = Ys + DY is performed. When Xs exceeds the boundary of 16 pixels of one raster or the value of the integer component of Ys changes, writing to the raster of 16 pixel units of the frame memory is performed by the pixel information and mask information created in 1. . If the above condition is not met, the process 1 is performed according to the new (Xs, Ys) coordinates. Also, the process is completed when the number of dots n of the linear development is reduced by 1 and becomes 0.

By performing the above control, raster data of a maximum of 16 pixels can be generated in the register in the data control unit and written to the frame memory.

Since the address of the frame memory is the same among the 16 pixels, the value of (Xs, Ys) excluding the lower 4 bits of Xs is sent to the frame memory address control unit 24, and furthermore, the bus 2- 1-1 and sent to the frame memory.

To change the density during linear development,
Since the change DI of the color information is further set in the density DDA 23 by the display control processor, the calculation of I = I + DI is performed in accordance with the coordinate calculation of (Xs, Ys).

Further, in the case of a rendering processor that controls the Z plane, the value of I is used as the Z value, and the Z comparator 26 compares the value of I with the Z value of the frame memory that has been read in advance. If the Z value on the frame memory side is large, the mask control unit 25 controls to turn on the mask of the corresponding pixel.

The above is the outline of the operation of the rendering processor. Hereinafter, the operation of each block will be described in detail.

FIG. 5 is a diagram showing the internal configuration of the address DDA 22. As shown in FIG.

For the (X, Y) coordinates of the destination, if the coordinates are determined based on the longer axis and the longer axis in X and Y by the well-known Presentham DDA algorithm. , A DXYF section 33 for calculating the carry of the minor axis below the decimal point, and a signal 10 from the carry.
DXI unit 32 and DYI unit 34 for calculating the integer part by 3
Is calculated sequentially. DXI part which became the major axis,
The DYI portion is always incremented by +1.

On the other hand, regarding the (X, Y) coordinates of the source, since the source image moves only in the raster direction,
Operation units 30 and 31 for only coordinate values are provided. In order to use the long axis of the destination as a reference, an integer part S is calculated.
An I part 30 and an SF part 31 for calculating a decimal part, and a carry propagation signal 104 from the decimal part to the integer part.
Controls the operation.

The algorithm of DDA is a long axis length SL_BA
When generalized based on SE, it is expressed by the following equation.

A = A ₀ B = B ₀ SL_INT = (B ₁ −B ₀ ) DIV SL_BASE SL_MOD = (B ₁ −B ₀ ) MOD SL_BASE IN_ERR = 0 IN_ERR = IN_ERR + 2 * SL_MOD-SL
_BASE N = SL_BASE WHILE N ≠ 0 DO BEGIN A = A + 1 IN_ERR = IN_ERR + 2 * SL_MOD-2 *
SL_BASE B = B + SL_INT + carry-from-IN_ERR N = N-1 END; These are common to all (X, Y) coordinates of the destination, except that there is no added value SL_INT of the integer part. The DDA circuit of the integer part is shown in FIG.
The configuration is as shown in FIG.

First, the decimal part will be described. Initial values are a major axis length SL_BASE and other axis modulo parts SL_BASE.
MOD and the initial value IN_ERR of the error term are stored in the bus 1
From the display control processor 12 via Registers 112, 111,
110 is a register 114, 113,
Since a dedicated register different from 121 is provided, the value of each register can be set during the operation of the previous command, and each set signal is given by the control signal 100 from the control unit 21.

The value of IN_ERR is 0 in the above equation of the DDA circuit.
When a straight line is cut in the middle, it is not a starting point at the grid point of the straight line but a certain amount of shift occurs. Therefore, this register is used to set a correction value at that time.

Now, the DDA operation currently being executed is completed.
When the display control processor 12 sets a command in the command register, the control unit 21 transmits all the initial value registers 110, 111, and 112 via the bus 100.
Of the current registers 121, 113, 114
Output the signal to be set.

Then, after setting the initial value of the contents of CERR 121, the above DDA operation formula is executed.
Upon receiving the carry signal 103 from the CERR register 121, the control unit 21 continues processing while using the bus 100.

On the other hand, for the integer part, the start point coordinates and the integer part of the bias value to the next point are respectively START.
_ADR register 130, SL_INT register 131
, And after starting, the value of each register becomes the current register CADR register 135 and CSL_
It is set in the INT register 132. Thereafter, the following calculation is performed by the carry signal 103 in synchronization with the operation of the decimal part.

CADR = CADR ± CSL_INT + CIN Whether to perform addition or subtraction is controlled by the signal 100 depending on whether the increasing direction is the decreasing direction.

Regarding the destination coordinates (X, Y), CSL_INT is set to 0 in order to always use the long axis as a reference.
However, the basic operation is the same.

The above is a detailed description of the address DDA circuit 22.

The density and the Z value DDA 23 are basically the same, and, as shown in FIG.
2 to calculate the density value or the Z value with the same hardware as described in the address DDA 22.

Next, the configuration of the data control unit 27 will be described. Four data control units 27-1, 27-2, 27-3, and 2 for controlling four planes in one processor
7-4, since the basic configuration is the same, one of them will be described with reference to FIG.

When a source image is required from the frame memory for affine transformation of an image or the like, the frame memory is read out via the bus 2-1-2, and data for 16 pixels is set in the SBUF register 141. You. The bus 1 is used when data is supplied from the display control processor 12, and in this case, data for one pixel is
This is set in the BUF register 141.

The set data is the address DDA
The lower 4 bits of the X coordinate of the source and the lower 4 bits of the X coordinate of the destination generated by the subtractor 143
Is shifted by the barrel shifter 142 by the value subtracted by This is a process for aligning the position of the source image in units of 16 pixels with the position of the destination image in units of 16 pixels, and placing data on the same 16-bit bus.

The shifted result is set in the DBUF register 145 via the selector 144. DBUF
The following control is performed on the set signal of the register.

(1) When generating data one pixel at a time,
Only a bit obtained by decoding the lower 4 bits of the X coordinate of the destination outputs a set signal to the flip prop.

(2) When n pixels are generated at one time as in the raster operation, a set signal to all the left or right flip-flops is output from the decoded bits of the lower 4 bits of the X coordinate. Which of the left and the right is determined by the relative positional relationship between the source image and the destination image.

That is, when the source pixel is on the left side of the destination image, the images are sequentially processed from the right so as not to break the picture due to the overlapping of the images. Therefore, the right side is set.

Operations for generating an image one pixel at a time are as follows: a) Until there is a carry from the lower 4 bits of SX to the upper
The same SBUF content is used.

B) Pixels are written to the same DBUF until there is a carry from the lower 4 bits of DX to the upper bits or the contents of DY are changed.

By performing the above-described control in the control unit 21 in accordance with a signal from the address DDA circuit, it is possible to perform processing while minimizing the number of accesses to the frame memory, and to increase the speed.

The image data generated in the DBUF is set in the RBUF register 146 under the condition b), and the destination image at this time is stored in the FMDBUF register 151.
After that, the operation is performed by the ALU 152, and the mask data 106 generated by the mask control unit is selected by the selector 153, and the write data to the frame memory 2-1-2 is selected.
And The selection of the mask data is because the recent dual-port memory has a structure in which the mask data and the normal data are received in a time-sharing manner.

On the other hand, the register 1 storing the background color
47 and a register 149 for controlling a mask for each rake
Has one bit for each plane unit, the former is set in the DBUF 145 as data corresponding to 0 by linear expansion or the like, and the latter masks all writing to the plane regardless of the output data from the ALU 152. Control signals for the selectors SEL1 144 and SEL3 153, respectively.

On the other hand, the density information 107 based on the density DDA
Is controlled to be set in the DBUF 145 as data corresponding to 1 such as linear development.

The above is the operation of the data control unit 27. As described above, since the generation of the image data to the DBUF and the access to the frame memory below the RBUF 146 are pipelined, the process of setting the next pixel information in the DBUF register during the frame memory access is performed for 16 pixels. Since the processing can be repeated up to the raster, the processing can be speeded up.

Next, the operation of the mask control unit 25 will be described with reference to FIG.
Explanation will be made using 0.

It is necessary to consider generation of mask data under the following conditions. 1) As a result of the Z comparator, when the Z value in the frame memory is larger, mask data must be generated to inhibit writing. The signal for this is the Z comparison mask 43
It is.

2) It is necessary to prohibit the writing corresponding to the pattern 0 at the time of hatching data development or the straight line development of the broken line. The signal for this is the pattern mask 184.

3) It is necessary to prohibit writing up to the start point or beyond the end point as in the raster operation. The signal for this is the rectangular mask 185.

4) In the data written to the work to be painted at the time of painting, even-numbered 1 to odd-numbered 1 must not be painted because they are not painted. The mask signal for this is 186.

In the above four cases, the generated mask signals are combined by MASKG 183, and the entire mask signal 106 is generated.

Hereinafter, a method for generating each individual mask signal will be described.

1) Z Mask Signal For the Z mask signal, Z plane control processors 4-8, 4-9, 4-10, 4-
11 is a carry signal compared with the frame memory (signal 44 in FIG.
Is the overall comparison result), Z of each rendering processor
By using a mask input signal, a mask signal can be obtained. See ZCOMP26 for how to generate carry signals.
Will be described in the part that explains the contents of the above.

2) Pattern mask signal The pattern information given via the bus 1 is stored in the register 1
It is set to 71 once. The registers 171 and 172 have a two-stage configuration for performing pipeline control, and the contents set in the register 171 are stored in the register 1 at the time of execution.
Set to 72.

From the contents set in the register 172,
The method of setting to the register 177 is similar to the method of generating a source image described in the configuration of the data control unit 27, and performs the following operation.

First, a difference between the lower 4 bits of the X coordinate of the source and destination generated by the address DDA unit is generated by the subtractor 175, and the result is used by the parallel shifter 17.
By controlling 3, the contents of the pattern register 172 are shifted by a plurality of bits and output to the bus 187.

The selector 176 outputs the bus 187 side only for the valid bit position in the bus 187, and selects the output of the MDBUF register 177 for the other bits.
In BUF, only the effective pixel mask data in the result of the barrel shift is set.

By repeating the above processing, mask data of up to 16 pixels per raster is generated in the MDBUF register 177.

The generated mask data is transferred from the DBUF register 145 to the RBUF register 146 by the data control unit 27 at the same timing as the MRBUF.
Set in register 178.

By the above operation, pattern mask data 184 corresponding to one access to the frame memory can be generated.

3) Rectangular mask signal A rectangular mask signal for raster operation must be generated under the following conditions.

I) At the start of the raster operation,
From the lower 4 bits of the destination address,
In order to control not to write to each of the left and right pixels, masking must be performed. For left and right,
It is determined by the positional relationship between the source image and the destination image.

Ii) At the end of the raster operation,
In order to perform control not to write to each pixel on the right or left from the value obtained by adding or subtracting the number of remaining pixels to the lower 4 bits of the destination address,
Must mask. The addition, subtraction, left, and right are determined by the positional relationship between the source image and the destination image.

Iii) When the number of pixels in the raster operation is small, the conditions i) and ii) occur at the same time. Therefore, it is necessary to OR the mask data generated by both to obtain rectangular mask data.

The rectangular mask generator 179 performs the above control based on the lower 4 bits 102 of the destination address and the signal 1 from the controller.

4) Paint Mask Signal The paint mask signal is generated by the rendering processor controlling the work plane as follows.

Information of plane on which paint is drawn 2-
The bits 1 and 2 are read out, the bit set to 1 is searched for, and the contents from the left pixel to the 1 bit are masked by the contents of the CFILL MODE register 181. Alternatively, data is generated so as not to be masked. By repeating this,
The mask data for 16 pixels is generated and output to the bus 45.

On the other hand, the rendering processor of another plane uses the bus 45 as an input signal and outputs the mask signal 45 to the bus 186 as it is.

By the above operation, the masking signal for the squeezing can be generated.

Next, the contents of the Z comparator 26 will be described with reference to FIG.

A carry signal is generated for each plane by the carry propagation signal 112 output from the ALU 152 of the data control unit 27 and the carry input signal 44 from another rendering processor. In order to generate and output a signal, four carry generation units 200 are serially connected as shown in the figure.
Since the configuration inside the carry generation unit is publicly known, it will not be described in detail here. However, in order to compare 16 pixels at a time, all input / output signals are configured with 16 bits.

Finally, the frame memory address control unit 24
Will be described with reference to FIG.

A DBUF register 212 is provided for designating a control mode other than double buffering.

At the time of execution, like the conventional register, C
Copied to DBUF register 213.

First, regarding reading of the source image,
The source address specified by the bus 102-1 is set in the FMADRBUF register 216 via the selector 215. At this time, one of the double buffers can be selected by the signal 211 from the register 213.

The address set in the register 216 is further multiplexed by a selector 217 into a row address and a column address to control the dynamic RAM, and sent to the frame memory via the bus 2-1-1.

On the other hand, for the destination address, the DADRBUF register 2 is used once to perform pipeline processing of the DDA circuit and the raster operation circuit.
The address is set in 14. Subsequent operations are the same as the access by the source address.

The configuration and operation of each unit in the rendering processor have been described above. According to the present embodiment, it is possible to generate a plurality of dots of up to 16 horizontal pixels during one memory access.

[0112]

According to the present invention, since the processing combining the DDA control circuit and the raster operation can be performed at high speed, the affine transformation such as enlargement / reduction of an image and the smooth filling processing can be performed for one pixel per machine cycle. (Approximately several ns), and a screen of about 10 ³ × 10 ³ can be drawn in about 0.1 second.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of one rendering processor according to an embodiment of the present invention.

FIG. 2 is a diagram showing a rendering processing function.

FIG. 3 is an overall configuration diagram.

FIG. 4 is a diagram showing a connection relationship of a rendering processor.

FIG. 5 is a diagram showing details of each block in FIG. 1;

FIG. 6 is a diagram showing details of each block in FIG. 1;

FIG. 7 is a diagram showing details of each block in FIG. 1;

FIG. 8 is a diagram showing details of each block in FIG. 1;

FIG. 9 is a diagram showing details of each block in FIG. 1;

FIG. 10 is a diagram showing details of each block in FIG. 1;

FIG. 11 is a diagram showing details of each block in FIG. 1;

FIG. 12 is a diagram showing details of each block in FIG. 1;

[Description of Signs] 22: DDA for address, 23: DDA for density, Z value, 2
5: mask control unit, 27: data control unit.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Isao Yasuda 5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture Inside the Omika Plant, Hitachi, Ltd. (72) Inventor Takeshi Takeshi 5-5-2 Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 Inside the Omika Plant of Hitachi, Ltd.

Claims (5)

[Claims] 1. A rendering processor comprising: a plurality of processors; and a plurality of frame memories coupled to each of the plurality of processors via a bus, wherein at least one of the plurality of processors outputs a mask signal. A rendering processor that outputs the generated mask signal to another processor, wherein the processor that receives the mask signal generates a destination image from a source image based on the mask signal. Processor. 2. The rendering processor according to claim 1, further comprising a processor for generating a destination image corresponding to at least red, green, and blue display colors among said plurality of processors. 3. Processing signals from a display control processor,
For a frame memory composed of multiple planes,
A rendering processor comprising a plurality of processor elements arranged in parallel for reading and writing at least pixel data, wherein at least one processor among the plurality of processor elements is a processor for generating a mask signal, A rendering processor that outputs the mask signal thus obtained to another processor, and the processor that receives the mask signal generates image data based on the mask signal. 4. The rendering processor according to claim 3, further comprising a plurality of frame memories connected to each of said plurality of processors. 5. The rendering processor according to claim 3, wherein said plurality of processors each control a red plane.
A rendering processor, which controls a green plane and a blue plane.