JP2804028B2 - Rendering processor - Google Patents

Description

The present invention mainly relates to a display control device such as a CRT display.
Rendering processor that generates data for display on
In particular, a process for generating images and three-dimensional data at high speed.
Related to the dulling processor. [Prior Art] Conventionally, devices for performing display control, especially drawing processing, have been proposed.
Many processing systems have been proposed. For example, an example described in JP-A-59-229669
Is an example of rotating an image.
Day staying image corresponding to the grid point coordinates of the image
The method of obtaining the coordinate value of is adopted. In this scheme,
The linear development DDA circuit is used for the (X, Y) seat of day staying.
It is only necessary to have it for the target, but the
Processing performance is determined by the
Image of grid point that is different from one grid point
Problems that are written or not written
have. In Japanese Patent Publication No. 57-57715, the density value at the top is given.
Showing the method for calculating the shading of each pixel inside the triangle
It is. This method uses the hardware
The above describes the mode realized by (a).
In particular, the shading process
Process to generate pixels parallel to the raster
Leaves a problem with performance. JP-A-60-252394 discloses a color image, especially a memory.
Shows a color image display device with a variable plane configuration
I have. This is because the bus configuration with the CPU does not depend on the number of planes.
It shows the method that can be fixed, but each play
There is no independent arithmetic circuit, and image processing starts.
The problem remains in the performance of the operation. [Problems to be Solved by the Invention] The above-mentioned prior arts are graphics and images, respectively.
Considering high-speed processing for some processing of
However, there are insufficient points to integrate and process them.
is there. The purpose of the present invention is to generate the CPU
Graphics processing for processing drawing commands and
Raster operation of images stored in memory
Rendering processor that can integrate with other image processing
To provide services. [Means for Solving the Problems] The feature of the present invention is that at least
The source image is used as the source image, and the coordinates of the source image
Calculate grid point coordinates of corresponding destination image
And has a coordinate calculation unit that converts the image data of the source image into
Render to write to grid coordinates of destination
Graphics generated by the CPU in the
Image consisting of density value and Z value generated based on command
Image data and density values stored in the frame memory,
First to select any one from image data consisting of Z values
And the concentration selected by the first selecting means.
Image data consisting of values and Z values, and a diagram generated by the CPU
From the density value and Z value generated by performing complementary operation from the shape command
Density values and Z values as source images
And a second selecting means for selecting.
The coordinates selected by the second selecting means
Writing a source image consisting of a value and a Z value. [Operation] According to the present invention, as the data of the source image,
Generated based on the drawing command generated
Image data consisting of degree value and Z value, figure generated by CPU
From the density value and Z value generated by performing complementary operation from the shape command
Image data and density stored in the frame memory
First and second selecting means based on image data consisting of values and Z values
The density value and Z value are selected according to the
Since it is written to the grid point coordinates of the
Graphics that process figure drawing commands generated by U
Image processing and image storage in the frame memory.
Integration with image processing such as raster operation is possible
Function and perform various rendering processes.
it can. [Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 to 12.
explain. FIG. 1 shows a hardware configuration which is the main component of the present invention.
FIG. 2 shows a typical example of the main functions of the present invention.
FIG. 3 is a diagram showing the overall system configuration, and FIG.
The figure shows rendering using the same hardware repeatedly
FIG. 5 is a block diagram of the processing unit, and FIG.
FIG. 3 is a diagram illustrating a configuration in detail. First, a description will be given of a hardware configuration that is the main component of the present invention.
Before describing the position of the present invention in all systems,
You. FIG. 3 is an overall configuration of a display system utilizing the present invention.
FIG. In FIG. 3, around the bus 16
Processor 10, main processor 10, and display hardware
Shared memory 11 as communication means, display control
Processor 12, rendering processor that performs pixel expansion
4, frame memory 5, and CRT 15 as shown in the figure
Connected in a simple manner. If the main processor 10 wants to display a picture on the CRT 15,
It is executed according to the following operation flow. First, share the command of the picture you want the main processor 10 to display.
Write on the existing memory 11. After that, the display control processor
The main processor 10 activates 12 via the bus 16. The display control processor 12 issues commands from the shared memory 11.
After reading and interpreting, the rendering processor 4
Break it down into small commands and send them out. Rendering pro
The processor 4 decomposes data in pixel units, and
5 is controlled. The contents of the frame memory 5 are always
Is read to CRT15, the written contents are
Immediately displayed on the CRT. At the center of the present invention is a layer for developing this pixel.
Since this is the processing processor 4,
The detailed configuration of the part is described. Fig. 2 shows the main functions of the rendering processor.
This is a picture of Yeon, where the source image is
3 shows an establishment image. Items with depth in the image area are indicated by images with width.
ing. First of all, the raster operation consists of a source and a day stay.
Both directions are the same and the sizes are the same.
This allows multiple pixels to be processed at once
You. Rotate the source horizontally, but
Chillon has a slope as shown in the figure, and the number of pixels is also multiplied by N / M.
I have. The coloring is written on the day stayation
According to the information, the pattern information of the source
This is the process of writing by multiplying. Although the development of the broken line is painted out,
The difference is that the napkin has a slope. The above processing is performed by each rendering processor.
This can be done by receiving 4 bits of pixels.
It is possible to do something like 1) For raster operation, 16 pixels at a time
Can read and write. 2) For rotation, the source reads 16 pixels at a time,
Maximum 16 pixels for horizontal
The process of calculating and calculating only the continuous pixels up to
Can do business. 3) For painting, painting data for 16 pixels
Data is generated and written to the frame memory. 4) Dashed line development is the same as in 2)
Generated continuous pixels up to 16 pixels in the horizontal direction
Thereafter, a process of writing to the frame memory can be performed. The following describes the configuration of each rendering processor.
I will tell. Rendering processor 4 processes in units of 4 bits of pixels
Possible processors are installed in parallel as shown in FIG.
It consists of a group of processors. Each processor is connected to the frame memory 5 via the bus 2.
And all processors are connected to the display control processor 12 and the bus.
Only one is connected. Each of the rendering processors 4 is the same processor.
4-i (i = 1−... 11)
The charge is as follows. Work plane control (for painting): 4-1 Red plane control: 4-2, 4-3 Green plane control: 4-4, 4-5 Blue plane control: 4-6, 4-7 Z plane control: 4- 8,4-9,4-10,4-11 Each rendering processor has
Signal 41 indicating whether the
Data set or read via bus 1
A signal 42 is provided to enable
From the control unit of one master processor.
No. 42 is output. Next, Fig. 1 shows the internal configuration of each rendering processor.
This will be described with reference to FIG. The processor communicates with the control unit 21 and the address and shading of each pixel.
DDA operation unit for calculating information (Source
Address DDA22, density / Z value calculation DDA23),
For calculating data for 16 pixels of one raster in the frame memory
Data controller 27 (for controlling 4 planes with 1 processor)
Therefore, four DCU0 to DCU3 are placed in parallel), and the Z value is
Write which pixel out of the 26 and 16 pixels of the Z comparator to compare
Mask control unit that generates a mask of 25 or 16 pixels
Frame memory address that generates the frame memory address
The control unit 24 is configured. The outline of the operation of the rendering processor is as follows
I'm sorry. Commands and data from the display control processor 12 are transferred to the bus.
1 through the registers in each rendering processor 4
Is set to Registers are pipelined in processor 4.
It is composed of two stages for in-control and
The following commands and data can be set.
You. The display control processor 12 first registers necessary data.
Command to the command register after setting
Set. For example, when developing a line with a constant color
After setting the following data,
Set. (1) The starting coordinate value (Xs, Ys) of linear development is DDA for address.
Set to internal register. (2) The increment values (DX, DY) of (Xs, Ys) are also for addresses
Set to the register in DDA. (3) The number n of dots in the linear development is stored in a register in the control unit 21.
To cut. (4) Set the linear color information I in the register in the density DDA23
I do. After the above data set, a command for linear development is sent.
Then, the rendering processor operates as follows.
Do. (1) Among the coordinate values of (Xs, Ys), the lower 4 bits of Xs
(Corresponding to the address within 16 pixels of one raster)
And the corresponding mask bit is turned off by the mask control unit.
And the color information I of the corresponding pixel is stored in the data control unit.
Set in the Vista. (2) Perform the operation of Xs = Xs + DX Ys = Ys + DY. Xs crossed the boundary of 16 pixels of one raster
Or, when the value of the integer component of Ys changes, created with 1
16 pixels of frame memory according to pixel information and mask information
Write to the unit raster. Meet the above conditions
If not, perform the processing of 1 according to the new (Xs, Ys) coordinates.
Do. In addition, the number of dots n of the linear expansion is subtracted by 1 and becomes 0.
The process is completed in the state where it is set. By performing the above control, a raster of up to 16 pixels can be
Generates data in a register in the data control unit,
Can be written to memory. The address of the frame memory is the same among the above 16 pixels.
(Xs, Ys) excluding the lower 4 bits of Xs
The value is sent to the frame memory address control unit 24,
The data is sent to the frame memory via the bus 2-1-1. To change the density during linear development, use the density DDA23
In addition, the change DI of the color information is displayed by the display control processor.
Therefore, I = I + DI is calculated in accordance with the coordinate calculation of (Xs, Ys). Furthermore, a rendering processor for controlling the Z plane
In the case of, since the value of I is used as the Z value,
Comparison with the Z value of the frame memory that has been read first
This is performed by the Z comparator 26, and the Z value on the frame memory side is
If larger, control to turn on the mask for the corresponding pixel
Is performed by the mask control unit 25. The above are the elements of the operation of the rendering processor.
Hereinafter, the operation of each block will be described in detail. FIG. 5 is a diagram showing the internal configuration of the address DDA 22.
You. For the (X, Y) coordinates of day staying,
Based on the well-known Presentham DDA algorithm
Of X and Y, the coordinate is based on the longer axis and the longer axis.
DX that calculates the carry of the minor axis after the decimal point
Calculates integer part using YF section 33 and carry signal 103
The calculation is sequentially performed by the DXI unit 32 and the DYI unit 34. Long axis
DXI and DYI sections are always incremented by +1.
Good. On the other hand, for the (X, Y) coordinates of the source,
Moves only in the raster direction.
It has calculators 30 and 31. Specify the major axis of day staying.
In order to make the standard, the SI part 30 that calculates the integer part and the decimal part
It is composed of an SF unit 31 that calculates
The calculation is controlled by the carry propagation signal 104. The DDA algorithm is generalized based on the long axis length SL_BASE.
Then, it is represented by the following equation. A = A ₀ B = B ₀ SL_INT = (B ₁ −B ₀ ) DIV SL_BASE SL_MOD = (B ₁ −B ₀ ) MOD SL_BASE IN_ERR = 0 IN_ERR = IN_ERR + 2 * SL_MOD-SL_BASE N = SL_BASE WHILE N 0 DO BEGIN A = A + 1 IN_ERR = IN_ERR + 2 * SL_MOD-2 * SL_BASE B = B + SL_INT + carry-from-IN_ERR N = N-1 END; , The (X, Y) coordinates of day staying
However, only the integer part SL_INT
The DDA circuits for the decimal part and the integer part are shown in FIGS. 7 and 8.
It becomes the structure shown by. First, to explain the decimal point, the initial value is the major axis length
SL_BASE, other axis modulo section SL_MOD, and the first error term
The period value IN_ERR is transmitted via the bus 1 to the display control processor 12.
Given by Cash register corresponding to each parameter
The registers 112, 111 and 110 are registers 114 and 11 used during operation.
There is a special register different from 3,121
The value of each register is set during the operation of the previous command.
Each set signal can be a control signal from the control unit 21.
Given by 100. IN_ERR is 0 in the above DDA circuit equation.
However, the clipping control cuts the straight line halfway.
Is not the starting point of a straight grid point,
Since the degree of deviation occurs, set the correction value at that time.
Register. By the way, the DDA operation currently being executed ends, and
Display the set of commands to the memory register control processor 12
Is performed, the control unit 21 transmits all the initial
Stores the contents of value registers 110, 111, 112 in current register 1.
A signal to be set is output to 21,131,114. Then, set the initial value of the contents of CERR 121.
The CERR register so that the above DDA equation is executed.
The control unit 21 receives the carry signal 103 from the
The process is continued using the resource 100. On the other hand, also for the integer part, start point coordinates and next point
In the START_ADR register 13
0, by starting the SL_INT register 131 after setting
The value of each register is the current register CADR register
135, set in CSL_INT register 132. Then decimal
In synchronization with the operation of the unit, the following
Is calculated. CADR = CADR ± CSL_INT + CIN Whether to perform addition or subtraction depends on whether the direction is increasing or decreasing.
Is controlled by the signal 100. For day staying coordinates (X, Y), be sure to
CSL_INT is 0 to make the major axis the standard, but the basic
The operation is the same. The above is the detailed description of the address DDA circuit 22. The same is true for the concentration DDA23, and FIG.
As shown in the figure, it is composed of an integer part 41 and a decimal part 42.
With the same hardware as described for dress DDA22,
The density value or the Z value is calculated. Next, the configuration of the data control unit 27 will be described. One
4 data to control 4 planes in the processor
Control units 27-1, 27-2, 27-3, 27-4
Since the configuration is the same, one of them is shown in FIG.
A more detailed description will be given. For affine conversion of images, etc.
If a source image is required, the frame
The memory is read out, and the data for 16 pixels is
Set in register 141. Bus 1 stores data in a table
This is used when given from the display control processor 12 and
In the case of, the data for one pixel is set in the SBUF register 141.
Is done. The set data is generated by the address DDA.
The lower 4 bits of the X coordinate of the source
Value obtained by subtracting the lower 4 bits of the X coordinate of the
Only, it is shifted by the barrel shifter 142. This is a saw
16-pixel unit and day-staging image
16-pixel unit, and store them on the same 16-bit bus.
This is a process for placing data. The shifted result is output via selector 144 to the DBUF register.
Set to tab 145. DBUF register set signal
Then, the following control is performed. (1) When generating data one pixel at a time,
Bits decoded from the lower 4 bits of the X coordinate of the enablement
Set signal to flip-flop only is output.
You. (2) Generate n pixels at a time like raster operation
When decoding, the lower 4 bits of the X coordinate are decoded.
All flip flops to the left or right
A tone signal is output. Left or right is determined by
The relative position of the source images
Can be decided. In other words, the source image is
If it is on the left, it is right so that the picture is not broken by overlapping images
Are processed sequentially, so the right side is set and the opposite
If so, the left side is set. Operations that generate images one pixel at a time
A) The same until there is a carry from the lower 4 bits of SX to the upper
The contents of the SBUF are used. B) whether there is a carry from the lower 4 bits of DX to the upper bit, or
Until the contents of DY are changed, write pixels to the same DBUF
Is performed. The above control is performed by the signal from the address DDA circuit.
Control unit 21 to update the frame memory.
Processing can be performed while minimizing the number of accesses
Speeding up can be achieved. The image data generated in DBUF is RB under the condition of b) above.
Set in the UF register 146,
After reading the image into FMDBUF register 151, ALU15
Performs the calculation in step 2, and then generates the mask generated by the mask controller.
The data 106 is selected by the selector 153, and the
Write data 2-1-2. Selection with mask data
The choice is that recent dual-port memory
A structure that accepts normal data in a time-sharing manner
Because it is. On the other hand, the register 147 or the play
The register 149 that controls the mask for each
It has one bit for each plane unit.
Set to DBUF145 as data corresponding to 0, the latter
Is the plane regardless of the output data from ALU152.
Selector SE to mask all writing to
Control signals for L1 144 and SEL3 153. On the other hand, the density information 107 from the density DDA is a
Set to DBUF 145 as data corresponding to
I will. The above is the operation of the data control unit 27. Thus DBUF
Generation of image data to the frame and frame memo of RBUF 146 or less
Access to the file is pipelined,
During the memory access, the next pixel information is stored in the DBUF register.
The setting process can be repeated up to 16 pixel raster
Therefore, the processing can be speeded up. Next, the operation of the mask control unit 25 will be described with reference to FIG.
I will tell. Mask data is generated under the following conditions.
It is necessary to consider the result. 1) As a result of the Z comparator, the Z value in the frame memory is larger
At times, mask data must be generated to prohibit writing.
Need to be implemented. The signal for this is obtained by the Z comparison mask 43.
is there. 2) When developing straight lines with broken lines and painting hatch data
In areas corresponding to pattern 0, writing must be prohibited.
It is necessary. The signal for this is the pattern mask 184.
You. 3) To the starting point like a raster operation or
Must be write-protected after the end point. For this reason
Is a rectangular mask 185. 4) At the time of smashing, the data written on the smashed work
In the data, even-numbered 1 to odd-numbered 1
It is necessary to prohibit writing in order not to smear.
The mask signal for this is 186. In each of the above four cases, the generated mask signal is
Combined by SKG183, the entire mask signal 106 is generated
You. The method for generating each individual mask signal is described below.
Bell. 1) Z mask signal For the Z mask signal, Z of the rendering processor is used.
By plane control processors 4-8, 4-9, 4-10, 4-11
Signal that has been compared with the frame memory
The signal 44 in FIG.
Comparison result) with the Z mask input of each rendering processor.
A signal can be used as a mask signal. Ki
For the method of generating the Yary signal, the contents of ZCOMP26 are explained.
It will be described in the following. 2) Pattern mask signal Pattern information given via bus 1 is stored in a register
Set once in 171. Registers 171 and 172 are pipeline
It has a two-stage configuration for performing
The contents set in 171 are set in register 172 at execution.
Is done. From the contents set in register 172 to register 177
The setting method is described in the configuration of the data control unit 27.
Similar to the source image generation method,
Perform the operation. First, the source and the data generated by the address DDA
Subtractor 175 subtracts the difference of lower 4 bits of X coordinate of enablement
And control the barrel shifter 173 with the result
Shifts the contents of the pattern register 172 by several bits.
And output to the bus 187. Selector 176 only for valid bit positions in bus 187
Output the bus 187 side, otherwise output the MDBUF register 177
By selecting the output of the MDBUF, the barrel shift
Only the effective pixel mask data in the result is set.
Go. By repeating the above processing, the MDBUF register 177 contains 1
Mask data of up to 16 pixels of the raster is generated. The generated mask data is stored in the data control unit 27 in the DBUF level.
Same as setting from register 145 to RBUF register 146
At the timing, it is set in the MRBUF register 178. With the above operation, one access to the frame memory
Can be generated. 3) Rectangular mask signal The rectangular mask signal of the raster operation is under the following conditions.
Must be generated. i) At the start of the raster operation,
Left or right of the lower 4 bits of the location address
Masking is performed to control not to write to each pixel.
There must be. For left and right, source image and data
It is determined by the positional relationship of the residence image. ii) At the end of the raster operation,
The lower 4 bits of the session address and the number of remaining pixels
Is added to or subtracted from each pixel on the right or left
In order to control not to write to
No. For addition, subtraction, right and left, the source image and
It is determined by the positional relationship of the day staying images. iii) If the number of pixels in the raster operation is small,
Since conditions i) and ii) occur at the same time, both conditions were generated.
Mask data must be ORed to make rectangular mask data
There is. The above control is performed for the lower 4 addresses of the destination address.
The operation performed by using the bit 102 and the signal 1 from the control unit is as follows.
The rectangular mask generation unit 179. 4) Filling mask signal
Generated by the controlling rendering processor as follows:
It is. The plane information 2-1.2 that draws the paintwork
Read out and find the bit that is 1 and CFILL
According to the contents of the MODE register 181, the above 1
Mask up to the bit. Or do not mask
Generate data. By repeating this process, 16 pixels
And outputs the data to the bus 45. On the other hand, other plane rendering processors
Source 45 as the input signal and the mask signal 45 as it is.
It also outputs to the bus 186. With the above operation, the masking signal is generated.
Can be Next, the contents of the Z comparator 26 will be described with reference to FIG.
You. Carry transmission output from ALU152 of data control unit 27
General-purpose signal 112 and a key from another rendering processor.
Carry signal for each plane by the input signal 44
And carry signals for four planes in one processor
Carry generation as shown in the figure to generate and output
Four sections 200 are serially connected. Note that the carrier generation unit
Since the internal configuration is known, it will not be described in detail here.
However, since 16 pixels are compared at once, all input / output signals
It consists of 16 bits. Finally, the configuration of the frame memory address control unit 24 is described.
This will be described with reference to FIG. DBUF level to specify other control modes such as double buffer
It has a resistor 212. During execution, the CDBUF register
Copied to the data 213. First, regarding reading of the source image, the bus 102-
1 via the selector 215
And set it in the FMADRBUF register 216. At this time,
In response to signal 211 from star 213, any of the double buffers
It is possible to choose one. The address set in register 216 is the dynamic
Row RAM and column address.
Multiplexed by the selector 217 and the bus 2-1-1
Is sent to the frame memory. On the other hand, for the destination address,
The pipeline processing of the A circuit and the raster operation circuit
Once the address is stored in DADRBUF register 214,
Set. Subsequent operations depend on the source address.
Same as access. The configuration of each part inside the rendering processor,
And operation have been described. According to the present embodiment, one memory
Generate multiple dots up to 16 horizontal pixels during access
It can be carried out. [Effects of the Invention] According to the present invention, a diagram generated by the CPU such as linear development
Graphics processing for processing shape drawing commands and frame processing
Raster operation of images stored in memory
Integration with image processing such as
Various rendering processes can be performed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram of one rendering processor according to an embodiment of the present invention, FIG. 2 is a diagram showing a rendering processing function, FIG. FIG. 4 is a diagram showing the connection relationship of the rendering processor, and FIGS.
FIG. 2 is a diagram showing details of each block of FIG. 1; 22 ... DDA for source, day address, 2
3 ... DDA for density and Z value, 25 ... Mask control unit, 27 ... Raster operation data control unit.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Isao Yasuda               5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture               Hitachi, Ltd. Omika Factory (72) Inventor Takeshi Kato               5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture               Hitachi, Ltd. Omika Factory                (56) References JP-A-59-229669 (JP, A)                 JP-A-62-7087 (JP, A)                 JP-A-59-106066 (JP, A)

Claims (1)

(57) [Claims] The image data stored in the frame memory is used as a source image, and at least a coordinate operation unit that calculates grid point coordinates of the destination image corresponding to the coordinates of the source image is provided. In the rendering processor that writes the coordinates of the grid points, the image data composed of the density value and the Z value generated based on the graphic drawing command generated by the CPU and the image data composed of the density value and the Z value stored in the frame memory are used. A first selection unit for selecting one of the above, the image data composed of the density value and the Z value selected by the first selection unit, and a graphic command generated by the CPU to generate a complement. Second selection for selecting a density value and a Z value as a source image from image data consisting of a density value and a Z value And a stage, the lattice point coordinates of the destination, the density value selected by the second selection means, the rendering processor and writes the source image consisting of Z values.