JP2766478B2 - Image processing system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing system for displaying a grayscale image on a display, and more particularly to an image processing system for displaying an image having different brightness for each pixel due to the influence of illumination or the like. The present invention relates to an image processing system for displaying images on a display at high speed. [Prior Art] Japanese Patent Application No. 59-30278 for high-speed processing of color images
No., as disclosed in "Access Device for Image Memory", a computing unit is provided for each plane of the frame memory,
The method of processing in parallel is shown. [Problems to be Solved by the Invention] The above-mentioned prior art does not consider a wide calculation system of a grayscale image, and therefore, when performing a density conversion process of a grayscale image, the host processor (CPU) It was necessary to recalculate the image at the time, and the display could not be changed in real time. The application requirements for clarifying this problem will be described in more detail with reference to the drawings. As shown in FIG. 2, the left image data A is defined to have shading on a two-dimensional plane. When the image B is formed by performing a texture mapping process in which the image B is attached to one surface of a rectangular parallelepiped as shown on the right, a mapping is performed such that a density difference is generated between the rear and the front of the surface (or the rear and the front as viewed from the view side). Without image conversion, it doesn't look like a real event. Therefore, for example, the front is darkened and the rear is thinned. To realize this processing, for example, for a pixel mapped backward, mapping is performed by multiplying the value of each pixel of the grayscale image on the secondary plane by 0.6, and for a pixel mapped forward, 1.0
It is necessary to take the intermediate value of (0.6-1.0) times during the mapping. As a result, the rear portion becomes thinner than the original density on the two-dimensional plane. Conventionally, density conversion in such processing has been performed by a host processor, and real-time processing has not been easy. SUMMARY OF THE INVENTION It is an object of the present invention to provide an image processing system in which brightness information of each gray scale pixel is obtained as a different gray scale image on a display screen by arithmetic processing. [Means for Solving the Problems] The present invention relates to an arithmetic unit for calculating brightness information by linear interpolation, and an arithmetic unit such as a multiplier for calculating density information on the surface for each pixel according to the arithmetic result. And a container. [Operation] The linear interpolation calculation device calculates the brightness values one after another by giving a difference value for each calculation to the initial brightness value. The multiplier multiplies the brightness value obtained by this operation for each pixel of the original image. As a result, light and shade information to be displayed on the display can be obtained. Since this density information includes necessary pixels, a target image can be obtained by writing only necessary pixels in the frame memory. Embodiment FIG. 3 is a diagram showing an example of a display system according to the present invention. FIG. 1 is an embodiment diagram of a DDA circuit section which is the most characteristic of the present invention. In FIG. 3, a CPU 1 is a hoft processor, and instructs a display control processor 2 to convert an image or draw a graphic via a bus 5. The display control processor 2 divides the contents instructed via the bus 5 into units which can be processed by the DDA circuit unit 3, and
Command to the DDA circuit unit 3 via. The DDA circuit unit 3 calculates the gray value of each pixel, and
To the frame memory (FM) 4 via The contents of FM4 are always refreshed on the display (not shown). Therefore, the operator can always see the created image in real time. The above processing example of FIG. 3 will be briefly described based on the graphic example of FIG. FIG. 4 shows an example of converting the left A figure into the right B figure. The A figure is a two-dimensional figure and the B figure is a three-dimensional figure, and a process of attaching the A figure to one side of the B figure is performed. In this process, first, the CPU 1 instructs a mapping process on the left A image so as to constitute a part of the B graphic as shown on the right. This instruction is sent to the display control processor 2 via the bus 5. The display control processor 2 raster scans the image A. For each raster scanning line, as shown by the scanning line 1 in FIG. 4, a starting point (SX, SY) of the scanning line 1 is designated, and a destination corresponding to the starting point (SX, SY) is designated. (DX, DY) and brightness information I (0 ≦ I ≦ 1)
And the displacement ΔSX, Δ from the next point of SX, DX, DY, I
X, ΔY, ΔI are indicated. Here, the coordinates (DX, DY) of the destination are the corresponding values of the coordinates of the A figure on the B figure, and the point next to SX, DX, DY, I is the horizontal direction on the scanning line l. The next scan point in the (X direction) (for example, if the start point is the current scan point, the scan point is the next scan point after the start point. Generally, the scan pitch in the X direction is constant). The reason why ΔSX and ΔSY are unnecessary is that there is no change in the Y coordinate for one scanning line l. DX and DY exist because the scanning line l becomes a straight line r on the B figure. On the straight line r, not only the value of X but also the value of Y changes. The end point a is a1 and the start point b is b1. Further, the scanning line 1 changes from the upper part of the figure to the lower part of the figure with a constant Y coordinate displacement. The number is predetermined. The display control processor 2 stores the above data SX, SY, I, D
X, DY, ΔSX, ΔX, ΔX, ΔI are sent by the DDA circuit unit 3. The DDA circuit unit 3 calculates the coordinates and the density on the straight line r for each pixel based on these data. When the coordinates and density thus obtained are stored in the frame memory 4 and then displayed, a figure is obtained in a state of being attached to one side on the figure B in FIG. The embodiment of FIG. 1 will be described. DDA31: This DDA31 used a symmetric DDA. Symmetric D
FIG. 5 shows a functional diagram of the DA. Small values Δ are added one after another starting from a certain numerical value, and the integer part is output one after another for each added value. This output integer value is a converted value from the start point to the end point. FIG. 5 shows the function. A small value Δ is added to the decimal part and embedded in place of the previous decimal value. The integer value at that time is output for each embedding. still,
There are cases where the integer part is updated by embedding and cases where it is not updated. The case of being updated means that the decimal part
Is obtained as the result of adding
The case where it is not updated is a case where it does not reach an integer value of 1 even if Δ is added to the decimal part. The former is an example in which the carrier is generated, and the latter is an example in which the carrier is not generated. Here, the starting point refers to each value of SX, DX, DY, I, and the minute value Δ refers to each value of ΔSX, ΔX, ΔY, ΔI. For SY, there is no change for one arbitrary scan line l, Δ = 0, and the above operation is unnecessary. SX, DX,
The processing in FIG. 5 is individually performed on the five data of DY and I, and the data update to the end point is individually performed on each of the five data. Register 32: n plane registers 321, 322 to 32n
Consisting of Each of the registers 321 to 32n is a FIFO type register. Each of the registers 321 to 32n has a capacity of 16 bits × m. Here, n is the number of bits forming one pixel,
16 bits is the number of bits transmitted at one time, and m
Is the number of individual registers as FIFO. Therefore, m
Is a value that determines the capacity as a FIFO register. n is
There are many examples of taking 4, 8, or 16, etc. The greater the number n, the greater the number of gradations. 8 bits instead of 16 bits
Some examples are 32-bit. Image data is input to the register 32 via the bus 6. The selector 33 is composed of n selectors 331 to 33n. The selector 33 controls the output of the register 32 or the frame memory (FM) 4
Select one of the read data from. This selection is performed by a selection signal. This selection signal is (SX, SY)
Select the FO output of the register 32 when the address indicates the address of the main memory, and select the output of the frame memory (via the bus 7-2) when the address of (SX, SY) indicates the address of the frame memory. FM DATA). The selectors 331 to 33n of the selector 33
~ 32n. The selectors 331 to 33n are connected to the bus 7-2.
Corresponding to 16 × n of FM DATA output from. Source registers 34, 35 ... n registers 341 each
~ 34n and 351-35n. These two source registers 3
Reference numerals 4 and 35 are for 32 pixels, and perform buffering of 16 pixels each. The reason why the number of pixels is 32 is to generate data shifted by 16 pixels. So first register 34
Then, the data is sent to the register 35 for latching, and the register 34 is operated to latch new data. Parel shifter 36… n parallel shifters 361 to 36n
Consisting of The barrel shifter 36 has a function of shifting a plurality of bits at a time. Multiplier 37 is composed of 16 multipliers 371 to 37-16. Each of the multipliers 371 to 37-16 corresponds to one pixel.
The multiplication is performed between the information I and each pixel data. Write data buffer 38... N buffers 381 to 38n
Consisting of This write control is performed based on the decoding result of the lower 4 bits of DX. This decoding is performed by the decoder 70. Computing unit 39... Comprising n computing units (ALU). Control circuit 71... Performs DDA control. The designation L of the number of loops in the function shown in FIG. 5 and the start command COM are set. If COM is started, the DDA operation is continued until L = 0, and if the FM is read / written by FM read / write. If there is F
Read from M or write to FM. Here, the condition of FM writing is (the integer part of DY has changed) (DY
Has exceeded the memory boundary). Further, the fact that the value of DX has crossed the memory boundary means that a carry has occurred from the lower 4 bits to the 5th bit of DX, and that a unit of 16 pixels is at the boundary of the frame memory. A destination register (DSTREG) 40 is composed of n registers 401 to 40n. In the configuration of FIG. 1, the components 32, 33, 34, 35, 36, 38,
The reason why the planes 39 and 40 are composed of n planes is that when an image is composed of n bits of one pixel, the plane of n bits can be commonly processed in plane units. Thereby, parallel processing is performed. However, with respect to the multiplier 37, a multiplier is individually provided for each pixel in order to generate a carrier propagation between planes. The operation of FIG. 1 will be described. The parameters (SX, SY, D
X, DY, I, ΔX, ΔY, ΔSX, ΔI) are set in registers in the DDA circuit 31. When a raster starting with (SX, SY) is present on the frame memory 4, the address of SX, SY is output as an address for the frame memory 4 via the bus 7-1 by the selector 54, and FM4 is output. to access. Read data from within this address from FM4 is sent via bus 7-2,
The selector 33 selects and takes in the read data on the bus 7-2. On the other hand, if the raster starting with SX, SY is in the main memory of the CPU 1, the read data is sequentially written to the FIFO register 32 via the bus 6, and the selector 33
The data in 32 is taken in according to the FO method. The data obtained via the selector 33 is data of 16 pixels. Since each pixel has an n-bit configuration, 16-pixel data is 16 × n-bit data. The data selected by the selector 33 is stored in the source register (SORCE
REG) 34 and then sent to register 35. The registers 34 and 35 latch information of 2.times.16.times.n bits. The parallel shifter 36 shifts the data received from the registers 34 and 35 in accordance with the contents of the lower 4 bits (indicating the position of the 16-bit bus width) in the SX register in the DDA. The result is multiplied by the multiplier 37 with the stored value I of the brightness information in the DDA for each pixel. The result of this multiplication is once stored in the line data buffer 38. Stores data for 16 pixels at a time. Generally, since FM4 and the like are addresses in word units, a shift of α bits (0 ≦ α ≦ 15, 1 word 16 bits) occurs between the source data and the corresponding destination data. . The circuit that matches this is element 3
4,35,36. That is, the shifter 36 shifts the .alpha. Bit, and the registers 34 and 35 hold two words of source data so that one word of data can be generated even when the .alpha. Bit is shifted. On the other hand, the frame memory address to be written is DX, DY DDA
31, the address is output by selector 54 as address 7-1 to FM4 to access FM4, and the data read by this access is transmitted to bus The data is set in the destination register 40 via 7-2 (16 pixels). The final write data is obtained by calculating the contents of the write data buffer 38 and the destination register 40 simultaneously by the arithmetic unit 39 for 16 pixels.
This result is written to FM4 via bus 7-2. Regarding the writing of the above operation result to FM4, the writing pattern of the source data is basically a bit boundary, whereas the writing of FM4 is performed on a word-by-word basis. I will break.
Therefore, it is necessary to perform a process of merging the register 40 for reading the original data of the destination and the data 38 to be written. An arithmetic unit for this is the arithmetic unit 39. Note that the processing in DDA31 has been described above.
The following calculation is executed for each command. DX ← DX + ΔX DY ← DY + ΔY I ← I + ΔI SX ← SX + ΔSX SY ... Constant value By this, the address and brightness information of the next pixel to be written and the address of the source pixel to be written can be calculated in pixel units. According to the present embodiment, since multiplication can be performed up to 16 pixels at a time, when the size of the source image and the destination image is unchanged and the brightness information is constant, the calculation is performed at a time of 16 pixels. And speeding up can be achieved. Note that 16 pixels are merely an example, and that 8 pixels, 32 pixels, and the like can be handled. [Effects of the Invention] As described above, according to the present invention, image data having grayscale information can be converted by sequentially calculated brightness information, so that the brightness varies with the brightness on the display display. Image to be displayed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram of an embodiment of the present invention, FIG. 2 is a diagram of an example of a conventional graphic conversion process, FIG.
FIG. 5 is a diagram showing an example of a graphic conversion process according to the present invention, and FIG. 31 ... DDA, 36 ... Parallel shifter, 37 ... Multiplier.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Takeshi Kato 5-2-1 Omikacho, Hitachi City Inside the Omika Plant, Hitachi, Ltd. (56) References JP-A-61-237171 (JP, A) Sho 61-90275 (JP, A) JP-A Sho 60-250479 (JP, A) Matsushiro et al. "Processor dedicated to 3D color graphic display processing HPRG", Proceedings of Graphics and CAD Symposium, Japan Society for Information Processing, December 7, 1984, pp. 73-80 (58) Fields investigated (Int. Cl. ⁶ , DB name) G06T 15/50 JICST

Claims (1)

(57) [Claims] In an image processing system for converting a two-dimensional image into a three-dimensional figure and displaying the two-dimensional image in a designated partial area on the surface of the three-dimensional figure, a plurality of multipliers read out the two-dimensional image from a memory holding the two-dimensional image. The image to be obtained is obtained from the density information of the two-dimensional image and the brightness information of each pixel, the density image information converted for the three-dimensional figure is written in the memory, and is displayed in the partial area of the three-dimensional figure. An image processing system comprising a conversion unit. 2. 2. The method according to claim 1, wherein the multiplier 1 is 1
An image processing system, wherein the image processing system is provided for each pixel and performs parallel processing. 3. In an image processing system that converts a two-dimensional image into a three-dimensional figure and displays the three-dimensional figure on a designated partial area of the surface, the two-dimensional image is converted into a three-dimensional figure and A CPU that issues an instruction to display the partial area, and a plurality of multipliers that receive the instruction from the CPU and read out the density information of the two-dimensional image read from the memory that holds the two-dimensional image and the brightness information of each pixel. An image processing system comprising: image conversion means for obtaining grayscale image information converted for the three-dimensional figure, writing the grayscale image information in the memory, and displaying the grayscale image information in the partial region of the three-dimensional figure. 4. In an image processing system that converts a two-dimensional image into a three-dimensional figure and displays the three-dimensional figure on a designated partial area of the surface, the two-dimensional image is converted into a three-dimensional figure and A CPU that issues an instruction to display the partial area, and a plurality of multipliers that receive the instruction from the CPU and read out the density information of the two-dimensional image read from the memory that holds the two-dimensional image and the brightness information of each pixel. Image conversion means for obtaining grayscale image information converted for the three-dimensional figure and writing the grayscale image information to the memory; and the part of the three-dimensional graphic by converting the grayscale image information written to the memory by the image conversion means. An image processing system, comprising: display means for displaying in an area. 5. In an image processing system that converts a two-dimensional image into a three-dimensional figure and displays the three-dimensional figure on a designated partial area of the surface, the two-dimensional image is converted into a three-dimensional figure and A CPU for issuing an instruction to display the partial area, density information of the two-dimensional image read from a first memory holding the two-dimensional image by a plurality of multipliers receiving the instruction from the CPU, and each pixel Image conversion means for obtaining grayscale image information converted for the three-dimensional figure from each brightness information, writing the grayscale image information in a second memory, and displaying the grayscale image information in the partial area of the three-dimensional figure. Image processing system. 6. In an image processing system that converts a two-dimensional image into a three-dimensional figure and displays the three-dimensional figure on a designated partial area of the surface, the two-dimensional image is converted into a three-dimensional figure and A CPU that outputs information to be displayed in the partial area; and a density information of the two-dimensional image read from a memory that holds the two-dimensional image by a plurality of multipliers, and the information output from the CPU. A density conversion image is obtained from the brightness information of the partial area of the three-dimensional graphic, and the information output from the CPU corresponds to the surface coordinate value of the partial area of the three-dimensional graphic. Image conversion means for obtaining an address of a memory, storing the density-converted image in the memory in accordance with the address, and displaying the density-converted image in the partial area of the three-dimensional figure. Image processing system. 7. 7. The surface coordinate value output from the CPU according to claim 6, wherein the surface coordinate value is an end point of the partial area on the surface of the three-dimensional figure, and the image conversion unit performs an interpolation operation on the coordinates of the end point. An image processing system for obtaining an address of the memory. 8. In Claim 6 or 7,
The brightness information output from the CPU is brightness information of an end point of the partial area on the surface of the three-dimensional figure, and the image conversion unit performs an interpolation operation on the brightness information of the end point to calculate the two-dimensional image. An image processing system for determining a density conversion value of all pixels. 9. An image processing system that converts a two-dimensional image into a three-dimensional figure and displays the two-dimensional image in a designated partial area on the surface of the three-dimensional figure; a first memory that stores the two-dimensional image before the conversion; A second memory for storing the converted image at an address corresponding to a display screen and displaying the converted image on the partial area of the surface of the three-dimensional graphic, and a read address of the two-dimensional image read from the first memory; A conversion process is performed between the converted image and the write address of the converted image when the converted image is stored in the second memory.
And a CPU for instructing the image conversion means on the image conversion means based on the information of the three-dimensional figure, the write address of the second memory and the brightness information for the image conversion means. An image processing system characterized by the following. 10. In claim 9, the write address specified by the CPU to the image conversion means is an address corresponding to a coordinate of an end point of the partial area on the surface of a three-dimensional figure, and the image conversion means includes An image processing system, wherein an interpolation operation is performed on an address corresponding to an end point to obtain the write address. 11. In claim 9 or claim 10, the brightness information instructed by the CPU to the image conversion means,
The image information is brightness information of an end point of the partial area on the surface of the three-dimensional figure, and the image conversion means obtains a density conversion value of all pixels of the converted image by performing an interpolation operation on the brightness information of the end point. Processing system.