JPS59188761A - Write system of picture memory - Google Patents

Write system of picture memory

Info

Publication number
JPS59188761A
JPS59188761A JP58061769A JP6176983A JPS59188761A JP S59188761 A JPS59188761 A JP S59188761A JP 58061769 A JP58061769 A JP 58061769A JP 6176983 A JP6176983 A JP 6176983A JP S59188761 A JPS59188761 A JP S59188761A
Authority
JP
Japan
Prior art keywords
address
memory
straight line
point group
image memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58061769A
Other languages
Japanese (ja)
Inventor
Shinichi Kubota
伸一 窪田
Akira Sato
章 佐藤
Yasukatsu Oka
岡 安克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58061769A priority Critical patent/JPS59188761A/en
Publication of JPS59188761A publication Critical patent/JPS59188761A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To apply smearing-out at high speed by obtaining in advance an address of a start point group and an end point group of plural straight lines so as to provide the corresponding address of the start point and the end point sequentially to a straight line drawing circuit in smearing out an area by plural straight lines. CONSTITUTION:A CPU1 calculates the address of both end points A and B of the start point group of a smear-out area from a data read out of a memory 2 and outputs the result to a register 6. A straight line drawing circuit (DDA)3 calculates an address of each dot on a straight line AB based on the data in the register 6 and stores the result in a memory 5. This is performed similarly as to the end point group, and an address of each dot on a straight line CD is stored also in the memory 5. Then, the CPU1 extracts the address of the start point and the end point corresponding thereto from the memory 5 and gives the address to the register 6, and a data is written on a picture memory 4 via the DDA3. The CPU1 sets the address of the next start point and end point to the register 6 during the operation of the DDA3.

Description

【発明の詳細な説明】 (A)発明の技術分野 本発明は画像メモリの書き込み方式に係り、特に画像デ
ータを高速に塗り潰すことのできる画像メモリの書き込
み方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field of the Invention The present invention relates to a writing method for an image memory, and more particularly to a writing method for an image memory that can fill out image data at high speed.

(B)従来技術と問題点 第1図は従来の画像メモリの書き込み方式を説明するた
めのブロック図である。図面において1はCPU、2は
メモリ、4は直線描画回路。(以下DDAと称す)、4
は画像メモリである。
(B) Prior Art and Problems FIG. 1 is a block diagram for explaining a conventional image memory writing method. In the drawing, 1 is a CPU, 2 is a memory, and 4 is a linear drawing circuit. (hereinafter referred to as DDA), 4
is the image memory.

また第2図は画像メモリ4内の塗り潰し領域を説明する
ための図である。4は画像メモリ、5は始点、6は終点
、斜線部で示す7は塗り潰し領域である。従来2画像メ
モリ4の中を塗り潰すためには、メモリ2により読み出
したデータにより塗り潰し領域の1ライン(ラスタ)の
始点5と終点6をCPUIによって計算し、この計算結
果をDDA3に通知して第2図に示す画像メモリ4内の
斜線部の塗り潰し領域7のようにデータを書き込んでい
た。この場合、DDA3による画像メモリへの書き込み
は非雷に高速なため、処理時間はCPUIにおける始点
5と終点6の計算時間に依存するようになる。しかし高
速な計算を実行するためには高価なマイクロプロセッサ
が必要になり。
Further, FIG. 2 is a diagram for explaining a filled area in the image memory 4. As shown in FIG. 4 is an image memory, 5 is a starting point, 6 is an end point, and 7, which is indicated by diagonal lines, is a filled area. Conventionally, in order to fill in the inside of the 2-image memory 4, the CPU calculates the starting point 5 and end point 6 of one line (raster) of the filling area using the data read out from the memory 2, and notifies the DDA 3 of this calculation result. Data was written in the shaded area 7 in the image memory 4 shown in FIG. In this case, since writing to the image memory by the DDA 3 is extremely fast, the processing time depends on the calculation time of the starting point 5 and ending point 6 in the CPUI. However, in order to perform high-speed calculations, expensive microprocessors are required.

かつこのような高価なマイクロプロセッサであっても十
分な速度を得るのは困難であった。
Even with such an expensive microprocessor, it was difficult to obtain sufficient speed.

(C)発明の目的 本発明の目的は上記従来の欠点に鑑み、高速でかつ安価
に画像メモリを塗り潰すことのできる画像メモリの書き
込み方式を提供することにある。
(C) Object of the Invention In view of the above-mentioned conventional drawbacks, an object of the present invention is to provide a writing method for an image memory that can fill the image memory at high speed and at low cost.

(D)発明の構成 そして、この発明の目的はヒントマツプ状に画像データ
を格納する画像メモリと、2点のアドレスを与えること
によって該2点間の直線を表わすドツトのアドレスを発
生する直線描画回路とを備え、該画像メモリ内に塗り潰
された図形を表わすデータを書き込む画像メモリの書き
込み方式であって、予め前記塗り潰された図形を構成す
る始点群と終点群のアドレスを求めるアドレス発生手段
を備え、該アドレス発生手段により求められた該始点群
と該終点群のアドレスのうち対応する1組の始点と終点
のアドレスを順次前記直線描画回路にセントして、前記
画像メモリ内に該塗り潰された図形を表わすデータを書
き込みことを特徴とする画像メモリの書き込み方式を提
供することによって達成される。
(D) Structure of the Invention The purpose of the invention is to provide an image memory that stores image data in the form of a hint map, and a straight line drawing circuit that generates the address of a dot representing a straight line between the two points by giving the address of two points. An image memory writing method for writing data representing a filled-in figure into the image memory, the method further comprising address generation means for obtaining addresses of a starting point group and an ending point group constituting the filled-in figure in advance. , A corresponding set of addresses of the starting point and the ending point among the addresses of the starting point group and the ending point group obtained by the address generating means are sequentially sent to the straight line drawing circuit, and the filled image is stored in the image memory. This is achieved by providing an image memory writing method characterized by writing data representing a figure.

(E)発明の実施例 以下1本発明の一実施例を図面を用いて詳細に説明する
(E) Embodiments of the Invention One embodiment of the present invention will be described below in detail with reference to the drawings.

第3図は本発明の一実施例を説明するためのブロック図
であり、第4図はその時のCPtJの操作手順を説明す
るための図である。図面において第1図と同一部分は同
一番号で示す。また第3図において5はメモリ、6はレ
ジスタである。また7はアドレス発生手段であり、DD
A3とメモリ5およびレジスタ6から構成される。
FIG. 3 is a block diagram for explaining one embodiment of the present invention, and FIG. 4 is a diagram for explaining the operating procedure of CPtJ at that time. In the drawings, parts that are the same as those in FIG. 1 are designated by the same numbers. Further, in FIG. 3, 5 is a memory and 6 is a register. 7 is an address generation means, DD
It consists of A3, memory 5, and register 6.

次に第3図のブロック図の構成及び動作について第4図
を参照して説明する。CPUIはメモリ2より読み出し
たデータによって第4図に示すA点、B点く始点)を計
算し、レジスタ6にセントしDDAを駆動する。DDA
によって始点列(A点からB点までの直線上の各ドツト
のアドレス)を計算しメモリ5へ出力し記憶する。同様
にCPU1は0点、D点を計算しレジスタ6にセントし
DDA3を駆動する。そしてDDA3によって終点列(
0点からD点までの直線上の各ドツトのアドレス)を計
算し、同しくメモリ5へ出力して。
Next, the configuration and operation of the block diagram in FIG. 3 will be explained with reference to FIG. 4. The CPU calculates the starting points (points A and B shown in FIG. 4) based on the data read from the memory 2, stores them in the register 6, and drives the DDA. D.D.A.
The starting point sequence (addresses of each dot on the straight line from point A to point B) is calculated and output to the memory 5 and stored. Similarly, the CPU 1 calculates the 0 point and the D point, stores them in the register 6, and drives the DDA 3. Then, using DDA3, the end point string (
The address of each dot on the straight line from point 0 to point D is calculated and outputted to the memory 5 as well.

記憶する。次にCPUIはメモリ5より1線の始点、終
点(第4図において破線で結んだ点)のアドレスを読み
出し、レジスタ6にセットし、  DDA3を駆動する
。DDA3は第4図に示す破線上の各ドツトのアドレス
を計算し2画像メモリ4へ書き込む。DDA3が画像メ
モリ4ヘデータを書き込んでいる間に、CPIJIは次
の1組の始点。
Remember. Next, the CPU reads out the addresses of the start and end points of one line (points connected by broken lines in FIG. 4) from the memory 5, sets them in the register 6, and drives the DDA3. The DDA 3 calculates the address of each dot on the broken line shown in FIG. 4 and writes it into the two-image memory 4. While the DDA 3 is writing data to the image memory 4, the CPIJI is the starting point of the next set.

終点をメモリ5より読み出し、レジスタ6ヘセントする
。以下、同様の動作を繰り返し、B点、D点を読み出し
たらCPUIは動作を終了する。
The end point is read from memory 5 and placed in register 6. Thereafter, the same operation is repeated, and when points B and D are read out, the CPUI ends the operation.

次に別の実施例について説明する。DDAの出力は画像
メモリ4のアドレスであり、メモリに数バイトのバイト
長が必要である。したがって、これを直接メモリ5に書
き込むとメモリ5の容量が太き(なってしまう。しかし
、DDAの出力するアドレスは直線を表示するため、隣
り合ったビットのアドレスを順次出力するので、アドレ
スの変化分はX方向、Y方向とも高々±1ずつしか変化
しない。そこでメモリ5に格納するアドレスの変わりに
アドレスの変化分のみを格納すればメモリ容量を大幅に
減少することができる。
Next, another embodiment will be described. The output of the DDA is the address of the image memory 4, which requires several bytes of memory. Therefore, if this is written directly to the memory 5, the capacity of the memory 5 will become large. However, since the address output by the DDA displays a straight line, the addresses of adjacent bits are output sequentially, so the address The amount of change changes by at most ±1 in both the X and Y directions.Therefore, if only the amount of change in the address is stored in the memory 5 instead of the address, the memory capacity can be significantly reduced.

また別の実施例として、第3図に示したメモリ5とレジ
スタ6の代わりにDDA3と同じDDAを2個追加して
も本発明の目的は達成できる。すなわちアドレス発生手
段7は3個のDDAで構成される。、そして第4図にお
いてA、Bのアドレスを与えて始点列を計算する第1の
DDAと、C7Dのアドレスを与えて終点列を計算する
第2のDDAを設ける。そして第3のDDAに第1のD
DAと第2のDDAより2点のアドレス(第4図に示す
破線の始点と終点)を与えて5 この2点間の直線のア
ドレスを発生させる。
As another embodiment, the object of the present invention can be achieved by adding two DDAs similar to DDA 3 in place of the memory 5 and register 6 shown in FIG. That is, the address generating means 7 is composed of three DDAs. , and in FIG. 4, there are provided a first DDA that calculates a starting point sequence by giving addresses A and B, and a second DDA that calculates an ending point sequence by giving an address C7D. and the first D to the third DDA
Two points of address (starting point and ending point of the broken line shown in FIG. 4) are given from DA and second DDA, and an address of a straight line between these two points is generated.

(F)発明の効果 以上、詳細に説明したように2本発明によればCPUに
よっていちいち直線の始点と終点とを計算せず、DDA
によって始点列と終点列のアドレスを求め、これをメモ
リに格納するようにしたため、高速に画像メモリを塗り
潰すことができる。
(F) Effects of the Invention As explained in detail above, according to the present invention, the CPU does not calculate the starting point and ending point of a straight line one by one, and the DDA
Since the addresses of the start point string and end point string are determined by and stored in the memory, the image memory can be filled in quickly.

また、アドレスの変化分のみをメモリに格納するように
すればメモリ容量を大幅に減少して、低コスト化を実現
できる。
Furthermore, by storing only the changes in the address in the memory, the memory capacity can be significantly reduced and costs can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の画像メモリの書き込み方式を説明するだ
めのブロック図、第2図は画像メモリ内の塗り潰し領域
を説明するための図、第3図は本発明による画像メモリ
の書き込み方式を説明するための図、第4図は本発明の
画像メモリ内の塗り潰し領域を説明するための図である
。 図面において、1ばCPU、2.5はメモリ。 3は直線描画回路(DDA)、4は画像メモリ。 6はレジスタ、7はアドレス発生手段である。
Figure 1 is a block diagram for explaining the conventional image memory writing method, Figure 2 is a diagram for explaining a filled area in the image memory, and Figure 3 is for explaining the image memory writing method according to the present invention. FIG. 4 is a diagram for explaining the filled area in the image memory of the present invention. In the drawing, 1 is a CPU, and 2.5 is a memory. 3 is a straight line drawing circuit (DDA), and 4 is an image memory. 6 is a register, and 7 is an address generating means.

Claims (1)

【特許請求の範囲】 1)ヒントマツプ状に画像データを格納する画像メモリ
と、2点のアドレスを与えることによって該2点間の直
線を表わすド・ノドのアドレスを発生する直線描画回路
とを備え、該画像メモリ内に塗り潰された図形を表わす
データを書き込む画像メモリの書き込み方式であって、
予め前記塗り潰された図形を構成する始点群と終点群の
アドレスを求めるアドレス発生手段を備え、該アドレス
発生手段により求められた該始点群と該終点群のアドレ
スのうち対応する始点と終点のアドレスを組として順次
前記直線描画回路にセントして5前記画像メモリ内に該
塗り潰された図形を表わすデータを書き込むことを特徴
とする画像メモリの書き込み方式。 2)前記アドレス発生手段は、前記始点群および前記終
点群のアドレスを求める前記直線描画回路と、該直線描
画回路が求めた該アドレスを格納するメモリとで構成さ
れることを特徴とする特許請求の範囲第1項記載の画像
メモリの書き込み方式。 3)前記アドレス発生手段は、前記始点群および前記終
点群のアドレスを求める前記直線描画回路と、該直線描
画回路が求めた該アドレスの変位量を格納するメモリと
で構成されることを特徴とする特許請求の範囲第1項目
記載の画像メモリの書き込み方式。 4)前記アドレス発生手段は第1の直線描画回路と第2
の直線描画回路により構成され、前記始点群のアドレス
は該第1の直線描画回路によって求め、前記終点群のア
ドレスは該第2の直線描画回路によって求めることを特
徴とする特許請求の範囲第1項記載の画像メモリの書き
込み方式。
[Claims] 1) An image memory that stores image data in the form of a hint map, and a straight line drawing circuit that generates a do-no-do address that represents a straight line between the two points by giving addresses of two points. , an image memory writing method for writing data representing a filled-in figure into the image memory,
an address generating means for obtaining addresses of a starting point group and an ending point group constituting the filled-in figure in advance, and addresses of corresponding starting points and ending points among the addresses of the starting point group and the ending point group obtained by the address generating means; 5. A writing method for an image memory, characterized in that data representing the filled figure is written into the image memory by sequentially writing data representing the filled figure into the image memory. 2) A patent claim characterized in that the address generating means is constituted by the straight line drawing circuit that obtains the addresses of the starting point group and the ending point group, and a memory that stores the addresses obtained by the straight line drawing circuit. The writing method of the image memory according to item 1. 3) The address generation means is characterized by comprising the linear drawing circuit that obtains the addresses of the starting point group and the ending point group, and a memory that stores the displacement amount of the address obtained by the linear drawing circuit. An image memory writing method according to claim 1. 4) The address generating means includes a first linear drawing circuit and a second linear drawing circuit.
Claim 1: The linear drawing circuit comprises a straight line drawing circuit, wherein the address of the starting point group is obtained by the first straight line drawing circuit, and the address of the ending point group is obtained by the second straight line drawing circuit. Image memory writing method described in section.
JP58061769A 1983-04-08 1983-04-08 Write system of picture memory Pending JPS59188761A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58061769A JPS59188761A (en) 1983-04-08 1983-04-08 Write system of picture memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58061769A JPS59188761A (en) 1983-04-08 1983-04-08 Write system of picture memory

Publications (1)

Publication Number Publication Date
JPS59188761A true JPS59188761A (en) 1984-10-26

Family

ID=13180643

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58061769A Pending JPS59188761A (en) 1983-04-08 1983-04-08 Write system of picture memory

Country Status (1)

Country Link
JP (1) JPS59188761A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6288069A (en) * 1985-10-09 1987-04-22 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Graphic processor
JPH03174676A (en) * 1989-09-08 1991-07-29 Matsushita Electric Ind Co Ltd Clipping processor
WO1991013427A1 (en) * 1990-02-27 1991-09-05 Seiko Epson Corporation Method of generating dot signal corresponding to character pattern and device therefor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6288069A (en) * 1985-10-09 1987-04-22 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Graphic processor
JPH03174676A (en) * 1989-09-08 1991-07-29 Matsushita Electric Ind Co Ltd Clipping processor
WO1991013427A1 (en) * 1990-02-27 1991-09-05 Seiko Epson Corporation Method of generating dot signal corresponding to character pattern and device therefor
US5355448A (en) * 1990-02-27 1994-10-11 Seiko Epson Corporation Method of generating dot signals corresponding to character pattern and the system therefor

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