JP2001093800A - Electron beam lithography equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate setting of initial values required for each cumulative operation in a pipeline method operation unit wherein all the data is divided into a plurality of areas and the data in each area is processed by a cumulative operator which stores an operation path and a result of each data in a rapid primary memory and then these results are transferred from the primary memory to be stored in a ralatively slow secondary memory in a specified fundamental cycle. SOLUTION: When cumulative results are transferred to a secondary memory, the data is read from a primary memory in a first half of a fundamental cycle and initial values are stored in the primary memory in the latter half of the cycle. Due to this mechanism, the setting of initial values required each time acumulative operation is started up can be eliminated, shortening the operation time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit having means for holding a result of a cumulative operation, and more particularly, to an electron beam lithography system having an arithmetic unit capable of performing an operation on a semiconductor wiring pattern and storing the result in a memory. Related to the device.

[0002]

2. Description of the Related Art A conventional arithmetic circuit will be described below with reference to the drawings. In FIG. 2, reference numeral 11 denotes an n-bit data supplied from the data input means 14 having data representing data corresponding to a position and data representing the weight of the position. The address is used to control the activation of the pipelined data operation means 12 for generating storage data from the latter data, and to store the operation progress and the result output by the operation means 12.
The control means 11 operates asynchronously with the clock of the basic cycle, which is constituted by a CPU or the like having a data width of m bits so that the user can access the contents of the next memory 13 such as clearing. When the calculation of a certain range by 12 is completed, a process of transferring the result to the secondary memory 15 in the basic cycle is performed.

Before performing the accumulation operation, the control means 11 first sets an initial value in the primary memory 13. When the accumulative operation is started by the control means 11, the data operation means 12 generates a corresponding address of the primary memory 13 from the data representing the position of the data inputted from the data input means 14 in the first half of the basic period. An initial value is read out, and data to be stored at the address is generated from data representing the weight of the position. Next, in the latter half of the basic cycle, the data is stored at the address of the primary memory 13. When the accumulation operation in the primary memory 13 is executed for a certain operation unit, the result is transferred to the corresponding secondary memory 15.

In this process, access to the primary memory 13 requires continuous access to the same address, so high-speed performance is required. However, if a necessary portion is constituted by a memory having such a specification, the system becomes expensive. Therefore, it is necessary to repeat the process of configuring the minimum necessary area with the memory of the specification, dividing the entire operation area by the area, performing the cumulative operation, and transferring the result to the large-capacity secondary memory configured with the inexpensive memory. To calculate the desired area.

[0005] Because of the configuration described above, it is necessary to set an initial value before performing the cumulative operation for each divided area, and this is executed by the control means 11 writing the initial value to the primary memory 13. .

[0006]

As described in the preceding paragraph, in the conventional method, it is necessary to store an initial value in the primary memory every time the operation is started, and this requires control means to increase the overhead. However, this is a factor that lowers the throughput in proportion to the number of divisions of the calculation range.

Further, since the data width n bits for performing the normal operation is k times the bit width m accessible by the control means 11, it takes k times to access one address.
The throughput was to be further reduced.

[0008]

In order to solve the above-mentioned problem, at the time of transfer from the primary memory 13 to the secondary memory 15, data is read from the primary memory 13 in the first half of the basic cycle and in the latter half. Writing to the secondary memory 15 and the primary memory 13
A mechanism for writing an initial value to the read address is provided so that the initial value setting operation by the control means 11 before the accumulation operation is deleted, so that the operation throughput is not lowered irrespective of the number of activations of the accumulation operation. .

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS. In FIG. 1, reference numeral 11 denotes an n-bit data supplied from a data input means 14 having data representing data corresponding to a position and data representing the weight of the position, by using a clock having a certain basic period, from the former data to a memory element. The address is used to control the start of the pipelined data operation means 12 for generating stored data from the latter data, and the contents of the primary memory 13 for holding the operation progress and the result output by the operation means 12 are stored in the user memory. Has a data width of m bits that allows access such as clearing.
A control means 11 constituted by a PU or the like, which operates asynchronously with the clock of the basic cycle, and transfers a result to the secondary memory 15 in the basic cycle when the operation of a certain range by the data arithmetic means 12 is completed. Perform processing. In FIG.
16 transfers the operation result from the primary memory 13 to the secondary memory 15 in the first half of the basic cycle when transferring the operation result from the primary memory 13 to the secondary memory 15.
This is a data setting means for performing control such that the initial value set in the initial value register 21 is written into the primary memory 13 in the latter half of the process. In FIG. 1 and FIG. 3, a buffer connecting each means and a memory is an input enable signal.
(Indicated by OExx) to enable data transfer in the indicated direction.

The generation of data in the secondary memory 15 (hereinafter, referred to as map creation) is large, and is composed of an accumulation operation for each divided area in the primary memory 13 and transfer of the result to the secondary memory 15. All of these processes are performed in a pipeline manner in synchronization with a clock having a certain basic period.

First, the initial value for the cumulative operation is established in the primary memory 13 and the initial value register 20 by the control means 11.
Next, when OE4 and OE5 are deasserted and the accumulation operation is started by the control means 11, the data operation means 12 in the first half of the basic cycle causes the data supplied from the data input means 14 by the assertion of OE1. An address of the primary memory 13 is generated from the position information, and weight data corresponding to the address is generated. At the same time, the data read signals RD1 and OE2 of the primary memory 13 are asserted, so that the initial value read from the primary memory 13 is input to the data calculation means 12 and accumulated with the weight data. Further, in the latter half of the basic cycle, OE1 and OE2 are deasserted and OE
3. When the data write signal WR1 of the primary memory 13 is asserted, the data is replaced with the previous initial value and stored at the address.

By repeating the above operation within the basic period, the data of the divided area set in the data input means becomes 1
It is accumulated in the next memory 13.

When the accumulation in the primary memory 13 is completed, the transfer of the operation result to the secondary memory 15 is started. In the first half of the basic cycle, RD1 is first asserted to read the operation result, OE4, the data write signal WR2 of the secondary memory 15 is asserted, and the data is stored in the secondary memory 15. Next, in the latter half of the basic cycle, OE4 and RD1 are deasserted, OE5 and WR1 are asserted, and the initial value preset in the initial value register 21 is written into the primary memory 13 for initialization. As a result, the area of the primary memory 13 used for the accumulation operation is initialized at the same time when data is transferred to the secondary memory 15.

The subsequent divided areas are processed in the same manner.
In the conventional method, the initialization by the control means 11 of the primary memory 13 is required before the next accumulation operation. However, in the present invention, since the initialization is performed simultaneously with the data transfer to the secondary memory 15, No processing is required, and this leads to a significant improvement in throughput, especially for data with a large number of divisions.

An example of an electron beam drawing apparatus according to an embodiment of the present invention will be described below. In this system, in order to prevent the proximity effect, a map representing the degree of density is generated from the wiring pattern data so that the irradiation amount of the electron beam is optimally corrected in consideration of the degree of density of the surrounding pattern. That is, the address is obtained from the coordinate data of the shot data constituting the pattern data, the area is obtained from the data representing the size, and the two-dimensional array is provided on the map. This map requires a capacity of several G (giga) bytes especially for generating a mask used for a stepper.

Therefore, the primary memory is constituted by a high-speed memory of about several M (mega) bytes, and the secondary memory serving as a map is constituted by a relatively low-speed DRAM. According to the present invention, the initial value setting time conventionally required for 999 regions is not required, and it takes about several seconds for this processing. Assuming that the processing speed of the pipeline arithmetic unit is several hundred nanoseconds / data, Time equivalent to 2/3 can be reduced.

[0017]

According to the present invention, since the calculation can be performed without setting the initial value required for the cumulative calculation, the processing time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of a conventional system.

FIG. 3 is a block diagram of one embodiment of the present invention.

[Explanation of symbols]

11 control means, 12 data operation device, 13 primary memory,
14 ... data input means, 15 ... secondary memory, 16 ... initial data setting means, 21 ... initial value register.

Claims (1)

[Claims] 1. A data input means for supplying position data composed of position information and a weight of the position at a predetermined basic cycle, and a primary memory for storing operation data representing the operation progress and the operation result. A pipeline operation for generating a corresponding address from the position data in the basic cycle, reading a set value from the corresponding address in the primary memory, and simultaneously accumulating the operation result of the position data from the data input means. An electron beam lithography system having an arithmetic unit having a unit and a secondary memory for sending a result stored in the primary memory for each processing unit and combining a plurality of the results to form entire data; At the time of data transfer from the memory to the secondary memory, after reading the operation data from the primary memory within the basic cycle, Means for writing the set initial value.