JP4617210B2 - Drawing apparatus and exposure apparatus equipped with the same - Google Patents

Description

  The present invention relates to a novel drawing apparatus used in an exposure apparatus for exposing wiring pattern data designed by CAD (Computer Aided Design) or the like in a printed circuit board manufacturing process to a printed circuit board, and an exposure apparatus equipped with the same. .

  A direct exposure apparatus, which is one of exposure apparatuses, is an apparatus that exposes a wiring pattern on a printed circuit board without using a mask film, and a drawing apparatus is used as means for converting a wiring pattern designed by CAD or the like into an exposure pattern. .

  Here, the rendering apparatus performs raster conversion processing for converting a wiring pattern that is a vector image into an exposure pattern that is a bitmap image. In this drawing apparatus, the bitmap image is written into the bitmap memory at the time of conversion, and the bitmap image is read from the bitmap memory at the time of exposure and sent to the exposure unit.

  The performance of the rendering device is influenced by the access performance to the bitmap memory as well as the performance of the raster conversion processing. If the access performance to the bitmap memory is low, the performance of the rendering device deteriorates even if the raster conversion processing is fast. Leads to. In addition, the bit map memory requires a capacity of several GB as the raster conversion processing speed increases and the wiring pattern resolution increases.

  It is effective to use a high-speed SRAM (Static Random Access Memory; a memory that can be stored while the power is applied) to achieve high-speed access to the bitmap memory, but it is expensive and has a large mounting area. There is a drawback that the price of the equipment rises and the equipment is enlarged.

  When using DRAM (Dynamic Random Access Memory), which is inexpensive and has a small mounting area, it is possible to reduce the cost of the device and make it compact, but it draws a wiring pattern that frequently causes random access to the bitmap memory. In such a case, the DRAM assuming burst access has a drawback that the access performance to the bitmap memory is lowered, and as a result, the performance of the drawing apparatus is lowered.

  Even when an inexpensive DRAM with a small mounting area is used as a bitmap memory, conventionally, means for converting random access to burst access using a frame cache has been used as means for maintaining drawing performance. This is a small-capacity SRAM that can be randomly accessed at high speed. This is used as a frame cache, and the bitmap memory is divided into multiple cache areas of the same size as the frame cache. When writing a raster-converted bitmap image, the corresponding cache area is read from the bitmap memory to the frame cache, the bitmap image is written to the frame cache, and then the contents of the frame cache are written back to the bitmap memory. It is a method.

  In order to reduce the latency until bitmap images are written to the frame cache, the cache area to be written is communicated to the frame cache before raster conversion, and the reading from the bitmap memory to the frame cache is completed in advance. There is also a method that uses a means to keep it together. Patent Document 1 is known as an example of this.

JP-A-9-212661

  Compared with image data that is output and displayed on a display device or the like described in Patent Document 1, the image data handled by a drawing device used in an exposure device or the like has an aspect ratio size of several hundred K bits × several hundred K bits. Therefore, the size of the bitmap memory also increases. Therefore, the number of cache areas also increases, and the probability that a process of successively writing to different cache areas will increase. Such a method using the frame cache is efficient when writing to an area once read into the frame cache occurs continuously, but when writing to different cache areas occurs continuously. Many frame cache reads and write backs occur, resulting in a decrease in access efficiency. The present invention has been made in view of such circumstances.

  An object of the present invention is to provide a drawing apparatus capable of maintaining drawing performance even when a DRAM having a small mounting area is used as a bit map memory and further improving access efficiency to a frame cache and bit map memory, and the same. An exposure apparatus is provided.

  The present invention relates to a raster conversion processing means for converting a vector image into a bitmap image, a bitmap memory composed of DRAM for storing the transformed bitmap image, and access to the bitmap memory composed of DRAM. In a drawing apparatus including a frame cache for improving efficiency between the raster conversion processing unit and the bitmap memory, a write address of the bitmap image output from the raster conversion unit to the bitmap memory is set. When the area (cache area) to be included is read from the bitmap memory to the frame cache, the shape of the cache area is controlled based on the shape information of the bitmap image generated by the raster conversion processing means. For bitmap images to be written Cache area Te is optimized, it is possible to enhance the utilization efficiency of the frame cache.

  Further, a FIFO (First-In-First-Out) memory is provided between the raster conversion processing means and the frame cache, and a plurality of combinations of the FIFO memory and the frame cache are provided, and the bitmap image is provided. Is stored in the temporary FIFO memory, during which the cache area is read from the frame cache, and the bitmap image in the FIFO memory is written to the frame cache after the reading is completed.

  Further, during execution of the above processing, the next bitmap image is simultaneously processed, and if the cache area has already been read out to any of the frame caches, it is temporarily stored in the FIFO memory connected to the frame cache. When the cache area is stored and not read into any of the frame caches, temporarily stored in the FIFO memory connected to the unused frame cache, and there is no unused frame cache Preferably, the frame cache is used after the frame cache having the lowest access frequency is written back to the bitmap memory to be emptied.

  As described above, the present invention has found that the access efficiency can be improved by using means for optimizing the read area to the frame cache in order to reduce the number of times the frame cache should be read and written to solve the above-mentioned problems. It was made.

  According to the present invention, even when a DRAM with a small mounting area is used as a bitmap memory, the rendering performance can be maintained, and the rendering efficiency and the access efficiency to the frame cache and the bitmap memory can be improved, and the same is mounted. An exposure apparatus can be provided.

  Hereinafter, the best mode for carrying out the present invention will be described with reference to specific examples.

  FIG. 1 is a block diagram showing a configuration of a drawing apparatus according to the present invention. The drawing apparatus 2 of the present invention includes a raster conversion processing unit 3, a cache controller 4, a frame cache 5, and a bitmap memory 6.

  The drawing apparatus according to this embodiment includes a raster conversion processing unit 3 that converts a plurality of vector images into a plurality of bitmap images, a bitmap memory 6 that includes a DRAM that stores the converted bitmap images, and a DRAM. A frame cache 5 for improving the access efficiency to the configured bitmap memory 6 is provided between the raster conversion processing means 3 and the bitmap memory 6 and is output from the raster conversion processing means 3. When the area (cache area) including the write address of the bitmap image to the bitmap memory 6 is read from the bitmap memory 6 to the frame cache 5, the bit generated by the raster conversion processing means 3 is used. The shape of the cache area is controlled based on the shape information of the map image. Than is.

  The raster conversion processing means 3 receives a wiring pattern composed of a plurality of vector images generated by a CAD system operated on the CAD mounting apparatus 1 and converts it into a plurality of bitmap images. The converted bitmap image is finally written at a predetermined address on the bitmap memory. The raster conversion processing means 3 outputs a write address to the bitmap memory 6, image shape information, and bitmap image data for each bitmap image.

  The cache controller 4 receives the bitmap image write address and image shape information from the raster conversion processing means 3 and generates a cache area address and cache area shape information. The cache area address is the start address of the cache area including the write address. In addition, the cache area has several shape patterns (a shape with an aspect ratio of 1: 1, a shape with an aspect ratio of 1: 2, etc.), and an optimum shape pattern is selected based on image shape information, and this is selected as the cache area shape. Information. For example, if the bitmap image has a shape with an aspect ratio of 1: 1, a cache area shape pattern with an aspect ratio of 1: 1 is selected. If the bitmap image has a shape with an aspect ratio of 1: 2, the aspect ratio of 1: The shape pattern of the second cache area is selected.

  Further, the cache controller 4 performs control to read the cache area from the bitmap memory 6 to the frame cache 5 based on the cache area address and the cache area shape information.

  After reading the cache area into the frame cache 5, the raster conversion processing means 3 writes bitmap image data into the frame cache 5. When there is no bitmap image data to be written in the read cache area, the cache controller 4 performs processing for writing back the contents of the frame cache 5 to the bitmap memory 6.

  When the write back process to the bitmap memory 6 is completed, the next bitmap image output from the raster conversion processing means 3 is processed in the same manner.

  FIG. 2 is a diagram for explaining a processing example of a bitmap image. FIG. 2A shows an example in which a bitmap image 7 a and a bitmap image 7 b are written in the bitmap memory 6. FIG. 2B shows an example in which the shape of the cache area is uniform, and FIG. 2C shows an example in which the shape of the cache area is selected as an optimum shape pattern in accordance with the image shape information. In the example of FIG. 2B, when writing two bitmap images, it is necessary to read three cache areas. However, in the case of optimization based on image shape information as shown in FIG. It is only necessary to read the cache area, and therefore the number of times the cache area is read and written back can be reduced.

  According to this embodiment, even when a DRAM having a small mounting area is used as a bitmap memory, the drawing performance can be maintained, and the access efficiency to the frame cache and the bitmap memory can be improved.

  Also, by controlling the shape of the cache area when reading the cache area into the frame cache based on the shape of the bitmap image to be written, the cache area is optimized for the bitmap image to be written, and the efficiency of using the frame cache The bit map memory can be accessed more efficiently.

  FIG. 3 is a block diagram showing the configuration of the drawing apparatus according to the present invention. The drawing apparatus 2 includes a raster conversion processing unit 3, a cache controller 4, a cache selection unit 8, a plurality of FIFO memories 11-0 to 11-n, a plurality of frame caches 5-0 to 5-n, a memory interface 16, and a bitmap memory. 6 is provided.

  The cache selection unit 8 includes one input port 9 and a plurality of output ports 10-0 to 10-n.

  The FIFO memories 11-0 to 11-n include input ports 12-0 to 12-n and output ports 13-0 to 13-n, respectively.

  The frame caches 5-0 to 5-n include first access ports 14-0 to 14-n and second access ports 15-0 to 15-n, respectively.

  The raster conversion processing means 3 is connected to the CAD mounting apparatus 1 and to the input port 9 of the cache selection means 8.

  The output ports 10-0 to 10-n of the cache selection means 8 are connected to the input ports 12-0 to 12-n of the FIFO memories 11-0 to 11-n, respectively.

  The output ports 13-0 to 13-n of the FIFO memories 11-0 to 11-n are connected to the first access ports 14-0 to 14-n of the frame caches 5-0 to 5-n.

  The second access ports 15-0 to 15-n of the frame caches 5-0 to 5-n are connected to the memory interface 16. The memory interface 16 is connected to the bitmap memory 6.

  Next, a processing procedure in the above drawing apparatus will be described. The raster conversion processing means 3 sequentially receives a plurality of vector image data from the CAD-equipped device 1 and converts the received vector image data into a bitmap image in order. At this time, the bitmap image has a write address, image shape information, and bitmap image data.

  The cache selection unit 8 receives the bitmap image data and the write address sent from the raster conversion processing unit 3 from the input port 9, selects one of the output ports 10-0 to 10-n based on the cache selection signal, and performs a FIFO. Processing to send to any one of the memories 11-0 to 11-n is performed.

  The FIFO memory 11-0 temporarily stores bitmap data and a write address, and when the connected frame cache 5-0 is in a writable state, the output port 13-0 via the first access port 14-0. To write bitmap image data based on the write address. The FIFOs 11-1 to 11-n are also written in the frame caches 5-1 to 5-n, respectively, by the same operation as described above.

The cache controller 4 selects the frame caches 5-0 to 5-n to which the bitmap image is to be written, the control for reading the cache area from the bitmap memory 6 to the frame caches 5-0 to 5-n, and the bitmap image After the data is written in the frame caches 5-0 to 5-n, the data in the frame caches 5-0 to 5-n is controlled to be written back to the bitmap memory 6. The cache controller 4 selects a frame cache for writing a bitmap image based on the write address. The frame cache is selected based on the following three selection criteria.
(1) If the cache area has already been read into any of the frame caches 5-0 to 5-n, that frame cache is selected.
(2) When the cache area has not been read into any of the frame caches 5-0 to 5-n, a free frame cache is selected from the frame caches 5-0 to 5-n.
(3) If the cache area is not read and there is no free frame cache in any of the frame caches 5-0 to 5-n, the least frequently used frame cache is selected.

  In the case of the selection criterion (1), the cache controller 4 generates a cache selection signal for selecting the output port of the cache selection means 8 connected to the selected frame cache. For example, when the frame cache 5-0 is selected, a cache selection signal for selecting the output port 10-0 is generated. The bitmap image data and the write address received from the input port 9 of the cache selection unit 8 are output from the output port 10-0 and temporarily stored in the FIFO memory 11-0 via the input port 12-0. If other data is not stored in the FIFO memory 11-0, the bitmap image data and the write address are output as they are from the output port 13-0, and other data is stored in the FIFO memory 11-0. For example, after waiting for the output of the data, the data is output from the output port 13-0, and the bitmap image data is written to the frame cache 5-0 based on the write address via the first access port 14-0. It is. Similar processing is performed when the frame caches 5-1 to 5-n are selected.

  In the case of the selection criterion (2), as with the selection criterion 1, while the bitmap image data and the write address are stored in the FIFO memory 11-0, the cache controller 4 determines the cache area address based on the write address and the image shape information. The cache area shape information is generated, and control is performed to read the cache area from the bitmap memory 6 to the frame cache 5-0 via the second access port. When the reading of the cache area is completed, the frame cache 5-0 becomes writable, and the data temporarily stored in the FIFO memory 11-0 is written into the frame cache 5-0.

  In the case of the selection criterion (3), the cache controller 4 stores the data in the frame cache 5-0 while the bitmap image data and the write address are stored in the FIFO memory 11-0 as in the selection criterion (1). After writing back to the bitmap memory 6, a cache area address and cache area shape information are generated based on the write address and image shape information, and control is performed to read the cache area from the bitmap memory 6 to the frame cache 5-0. When the reading of the cache area is completed, the frame cache 5-0 becomes writable, and the data temporarily stored in the FIFO memory 11-0 is written into the frame cache 5-0.

  The memory interface 16 performs access arbitration of read requests and write requests from the frame caches 5-0 to 5-n. When all the bitmap images are processed, all the data in the frame caches 5-0 to 5-n are written back to the bitmap memory 6.

  As described above, a plurality of frame caches are provided as in the present embodiment, and a FIFO memory is provided in the preceding stage of the frame cache, so that the writing process of bitmap image data to the frame cache and the reading and writing back process of the frame cache are performed in parallel. It can be executed, and improvement in memory access efficiency can be expected.

  In this embodiment, the drawing apparatus shown in Embodiment 1 or 2 is used as an exposure apparatus. The exposure apparatus exposes wiring pattern data designed by CAD (Computer Aided Design) or the like on the printed circuit board without using a mask film in the manufacturing process of the printed circuit board. The wiring pattern designed by CAD or the like. A drawing device is used as means for converting the light into an exposure pattern.

  In the drawing apparatus, raster conversion processing for converting a wiring pattern as a vector image into an exposure pattern as a bitmap image is performed. In this drawing apparatus, the bitmap image is written into the bitmap memory at the time of conversion, and the bitmap image is read from the bitmap memory at the time of exposure and sent to the exposure apparatus.

  According to this embodiment, even when a DRAM with a small mounting area is used as a bitmap memory, the drawing performance can be maintained, the access efficiency to the frame cache and the bitmap memory can be improved, and the exposure time can be shortened. can do.

It is a block diagram of the drawing apparatus which concerns on this invention. It is a figure explaining the example of the cache area | region of the bitmap image which concerns on this invention. It is a block diagram of the drawing apparatus which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... CAD mounting apparatus, 2 ... Drawing apparatus, 3 ... Raster conversion process means, 4 ... Cache controller, 5-5-0-5-n ... Frame cache, 6 ... Bitmap memory, 7a, 7b ... Bitmap image, 8 ... Cache selection means, 9 ... Cache selection means input port, 10-0 to 10-n ... Cache selection means output port, 11-0 to 11-n ... FIFO memory, 12-0 to 12-n ... FIFO memory input Port, 13-0 to 13-n, FIFO memory output port, 14-0 to 14-n, first access port, 15-0 to 15-n, second access port, 16 ... memory interface.

Claims (4)

  Raster conversion processing means for converting a plurality of vector images into a plurality of bitmap images, a bitmap memory comprising a DRAM for storing the converted bitmap images, the raster conversion processing means and the bitmap memory In a drawing apparatus comprising a frame cache composed of SRAM between them, a cache area including a write address to the bitmap memory of the bitmap image output from the raster conversion processing means is transferred from the bitmap memory to the bitmap memory. A drawing apparatus comprising: a cache controller that controls the shape of the cache area based on shape information of the bitmap image generated by the raster conversion processing means when reading to a frame cache. 2. The method according to claim 1, wherein a cache selection unit, a plurality of FIFO memories connected to the cache selection unit, and a plurality of the plurality of FIFO memories connected to each of the FIFO memories are provided between the raster conversion processing unit and the frame cache. Frame cache,
A process of temporarily storing the bitmap image in the FIFO memory, a process of reading the cache area to the frame cache while being stored in the FIFO memory, and the bitmap in the FIFO memory after the completion of the reading A drawing apparatus, wherein a process of writing an image to the frame cache is executed simultaneously on a plurality of bitmap images.   3. The processing according to claim 2, wherein during the processing of the plurality of bitmap images, the next bitmap image is processed at the same time, and if the cache area has already been read out to any of the frame caches, the frame Temporarily store in the FIFO memory connected to the cache, and temporarily store in the FIFO memory connected to the unused frame cache when the cache area is not read to any of the frame caches, When there is no unused frame cache, the frame cache is used after the frame cache having the lowest access frequency is written back into a bitmap memory to be emptied. An exposure apparatus comprising the drawing apparatus according to claim 1.

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