JPH076008A - High-speed printer controller - Google Patents

Abstract

PURPOSE:To speed up printer control by performing parallel processing without increasing external bus lines in case of a conflict of start requests to a bit map memory conflict with each other. CONSTITUTION:The printer controller having one or >=2 printer control parts 201-20m which perform various control over a printer device and one or >=2 drawing process parts 301-30k which perform various drawing processes is equipped with plural bit map memories 101-10n which have specific address ranges assigned and can be actuated independently by the printer control parts 201-20m and drawing process parts 301-30k. Then a parallel processing part 40 sends actuation requests to the corresponding bit map memories 101-10n in parallel according to the specified address ranges when the printer control parts 201-20m or drawing process parts 301-30m send the actuation requests to the bit map memories 101-10n. The bit map memories 101-10n are memories where data can be written and read out in pixel units.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed printer control device, and more particularly to 1 or 2 for performing various controls of the printer device.
The present invention relates to a high-speed printer control device having the printer control unit described above and one or more drawing processing units that perform various drawing processes according to instructions.

[0002]

2. Description of the Related Art Conventionally, there has been a printer control device as shown in FIG. As shown in the figure, the printer control device includes a control processor (CTP) 8 that controls execution of various processors included in the printer control device and controls the work flow of the printer control device system (supervisor). , An input processing unit (front-end processor; FEP) 7 that is connected to a host computer and replaces data with analysis intermediate data, a drawing processing instruction unit 6 that gives an instruction for drawing processing, and an instruction of the drawing processing instruction unit 6 , RIO (Raster Image Op) that actually performs drawing processing on the bitmap memory 9 such as character expansion that replaces character codes with intermediate data, or compression or expansion.
It has an erator or Graphic Controler (drawing processing unit) 3 and a printer output unit (POC) 59.

Further, the drawing processing instruction unit 6 is provided with the FE.
The expansion processing unit 6 ₁ (RIP1) that expands the character based on the intermediate data of P7, and the drawing processing instruction to the RIO 3
Drawing instruction unit (RIP2) 6 ₂ for the
The printer output unit (POC) 59 has a DP (Dual Port RAM) 61 shared by IP and a main memory device (MS) 51 and a RIM (Raster Image Memory) 52.
A bitmap memory 90, and a printer control unit (PRC) 2 for reading image data to be output from the bitmap memory 90 and performing output processing as a video signal for each page. .

Each of these functional devices is connected to a control system C bus, a shared bus M bus, or an H bus. Further, FIG. 12 shows the bitmap memory 90 according to the conventional example. As shown in the figure, the bitmap memory 90 has a memory unit 94 for storing data, the printer control unit 2 (PRC), and the drawing processing unit 3 (RI).
When the activation request from O) competes in the bitmap memory 90, the rendering processing unit 3 (RI) which is the lower device is in accordance with the priority set in advance to the activation requesting device.
An arbitration circuit 92 for instructing the switching of the data line and the address line so as to interrupt the processing by the activation request from O) and prioritize the activation request from the printer control device 2 (PRC) which is a higher-level device. A memory control unit 93 that controls the memory unit 94 according to the address and the activation request,
An address line switching unit 91 that switches an address line based on an instruction from the arbitration circuit 92, and a switching unit 95a that switches a data line based on an instruction from the arbitration circuit 92.
b. In addition, the memory unit 94 has a first
Area 94 ₁ and second area 94 ₂ .

Next, the operation of the conventional printer control device will be described. The DMA controller, which controls the transfer of the printer controller 2 to the bitmap memory 90, outputs a first area 94 ₁ to the bitmap memory 90.
The data stored in 1 is activated for reading every three cycles of the basic clock (200 ns in this case). or,
The drawing processing unit 3 also activates the second area 94 ₂ of the bitmap memory 90 for the drawing processing of characters for each cycle of the basic clock.

The arbitration circuit 92 of the bit map memory 90 instructs the address line switching unit 91 to connect to the address line from the device which is the source of the activation request and activates the activation request unless the activations conflict. The switching unit 95 is instructed to switch the connection of the image data line with the original device. When the reception is completed, an affirmative response signal is sent to the device of the sender requesting activation.

If the printer controller 2 and the drawing processor 3
When there is a conflict between the start-ups from the printers, even if the process is started by the lower-order drawing processing unit 3, if there is a start-up request from the higher-order printer control unit 2, the arbitration circuit 92 The activation processing of the drawing processing unit 3 is interrupted, the activation request of the printer control device 2 is prioritized, and the image data for one page stored in the second area 94 ₂ is output as a video signal. Therefore, as shown in FIG. 11A, the drawing processing unit 3 develops characters in the memory unit 94 for two of the three cycles of the basic clock, and one of the three cycles is Printer control device 2
The output processing of the video signal is performed.

[0008]

As described above,
In the printer control device according to the conventional example, the priority order of the printer control section 2 is set higher than the priority order of the drawing processing section 3 in relation to the external interface. for that reason,
Even if the process according to the activation request from the drawing processing unit 3 has already been started, when the activation request is issued from the printer control unit 2, the drawing process is forcibly interrupted and the bitmap memory 90 is used. Since the read processing is performed, the character development processing capability of the drawing processing unit 3 is reduced, and there is a problem in that print control cannot be performed at high speed.

On the other hand, in order to speed up print control,
This can also be done by shortening the interval of the basic clock. But the base clock interval (200ns)
The shortening of has already reached its limit. In addition, it is not appropriate to increase the speed by using a cache memory because it causes an increase in cost. Further, by increasing the number of external bus lines, the first area and the second area of the bitmap memory can be made independent and realized by separate bitmap memories.

However, in this case, there is a problem in that the number of bus lines between the functional units (printed boards) and the corresponding terminals increase, resulting in a high cost and a complicated apparatus. Therefore, the present invention has been made for the purpose of speeding up printer control by enabling parallel processing when the activation requests for the bitmap memory compete without increasing the number of external bus lines. is there.

[0011]

In order to solve the above technical problems, the present invention, as shown in FIG. 1, includes one or more printer control units 20 ₁ to 20 ₁ to perform various controls of a printer device.
In a printer control device having 20 _m and one or more drawing processing units 30 ₁ to 30 _k for performing various drawing processes, a predetermined address range is assigned, and the printer control units 20 _{1 to} 20 _m and drawing A plurality of bitmap memories 1 that can be independently activated by the processing units 30 ₁ to 30 _k
0 ₁ to 10 _n and the start request by the printer control unit 20 _{1 to} 20 _m or the drawing processing unit 30 ₁ to 30 _{k in the} bitmap memory 10 ₁ to 10 _n , the specified address Applicable bitmap according to range
It has a parallel processing unit 40 for making a parallel activation request to the memories 10 ₁ to 10 _n .

Here, "bitmap memory" means
It refers to a memory that has a structure that enables writing and reading in units of one pixel. "Independently startable bitmap
The "memory" is formed by forming a so-called "bank" structure for a plurality of bitmap memories, and increasing the number of internal buses without newly providing an external bus line. ), Which enables control of the bitmap memory. “Predetermined address range” means each bitmap memory 10 ₁ to 10 _n ,
An address range set according to each memory capacity without overlapping the address range. What is "drawing processing"?
For example, RIO function (vector function; VG (vctorgen)
erater), rectangle conversion function (mover)), outline function (character expansion processing, character reduction / enlargement), scaling function (image image enlargement / reduction), and compression / decompression function. The number n of the bitmap memories, the number m of the printer control devices, and the number k of the drawing processing units can be arbitrarily determined.

According to the embodiment shown in FIG. 2, the address line selector 101 is provided in each of the bitmap memories.
_i , a memory control unit 106 _i , a memory unit 104 _i in which data is actually stored, and a data line selection unit 105 _i . Further, the memory controller 106 _i receives the activation request from the parallel processor 40 as a bitmap memory 10 _i.
If there is a conflict with the above, the data line and address line are selected so that the activation from the lower-level device is interrupted and the activation request from the higher-level device is prioritized according to the priority order set in advance for the activation request source device. The arbitration circuit 102 _{i for} instructing, and the memory unit 10 according to the designated address and the requested content.
And a control unit 103 _i that controls the 4 _i.

Further, according to the embodiment shown in FIG. 3, each of the printer control devices 20 ₁ to 20 2 is included in the parallel processing section 40.
0 _m and the activation request from each of the drawing processing devices 30 ₁ to 30 _k, the activation request distribution unit 41 that distributes the activation request to the corresponding bitmap memory based on the specified address. is there. As another embodiment, a plurality of insertable / removable memories 19 _{1 to} 19 _n capable of inserting / removing each of the bitmap memories are provided, and an insert / extract management unit for managing the insertion / removal state of the insertable / removable memories 19 _{1 to} 19 _n. 18 is provided to instruct the printer control devices 20 _{1 to} 20 _m and the drawing processing units 30 ₁ to 30 _k to change the configuration according to the device configuration according to the insertion / removal state.

[0015]

From the printer controller 2 or the drawing processor 3
Bitmap memory 10₁-10_nRequest to start
However, when the address is specified, the parallel processing unit
40 is a bit corresponding to the specified address range.
Tomap memory 10₁-10_nRequest to start
Bitmap memory 10 of the specified startup destination ₁~
10_nThen, the processing for each start is performed in parallel.
become. On the other hand, the same bitmap memory 10₁~ 1
0_nStartup requests from different devices conflict with each other
Then, for example, each bit described in the embodiment of FIG.
Arrangement circuit 102 of map memory_iRequest to start
Higher activation requests according to the priority set on the original device
Prioritize the activation request of the original device.

Since the output processing of the video signal is usually prioritized, the priority of the printer controller 2 is set higher than the priority of the drawing processor 2. Further, according to the embodiment shown in FIG. 4 described above, the bitmap memory is provided so that it can be inserted and removed. For example, in the case of a low speed machine, only one removable memory is required, and in the case of a medium speed machine, Only two are required, and in the case of a high-speed machine, three are provided. As a result, the processing can be performed with the optimum device configuration scale, and thus the efficient processing can be performed.

[0017]

EXAMPLES Next, examples of the present invention will be described.
5 to 7 show a first embodiment. FIG. 5 shows a printer control apparatus according to this embodiment. As shown in the figure, in the printer control apparatus according to this example, a control processor (CTP) 8, a communication control processor (front end processor; FEP) 7, and a drawing processing instruction unit 6
Drawing unit (RIP; Raster Image Processor or Graphic Controler) 3 and printer output unit (POC)
5 and. In the figure, the same reference numerals as those already used in FIG. 11 denote the same devices.

The printer output section (POC) 5
Is a main memory device (MS) 51 and RIM (Raster Image
Memory) 52 and a predetermined address range is allocated,
A printer controller 2 and the drawing processing unit 3 each independently plurality of bootable bitmap memory 1 ₁ by, 1 _2, with respect to said bit map memory 1 _1, 1 ₂ by the printer controller 2 or the drawing processing unit 3 activated when the request was includes a parallel processing unit 4 for performing an activation request in parallel to the bit map memory 1 _1, 1 ₂ which corresponds in accordance with the specified address range, the bit map memory 1 _1, 1 _The printer control unit (PRC) 2 reads image data to be output from ₂ and performs output processing as a video signal for each page.

Due to the existence of the parallel processing unit 4, the bitmap memories 1 ₁ and 1 ₂ can be independently activated from the printer control unit 2 and the drawing processing unit 3, respectively, whereby an external bus line is newly provided. There is no need to increase the number of internal bus lines. This corresponds to the introduction of a so-called bank structure into the bitmap memory.

FIG. 6 shows the bit map according to the first embodiment.
Memory 1₁, 1₂And the parallel processing unit 4. In the figure
As shown, each bitmap memory 1₁, 1₂To each
DRAM (dynamic RAM) that stores various data
Memory unit 14 consisting of₁, 14₂And the parallel processing unit 4
Activation request from PRCREQ or RIOREQ signal is a bitmap
Memory 1 ₁, 1₂If there is a conflict with the
The device from the lower device according to the priority set in advance.
Stop the operation and prioritize the activation request from the higher-level device.
As instructed to switch the data line and address line.
Bitmap memory 1₁And bitmap memory 1₂When
Arbitration circuit 12 that performs arbitration between₁, 12₂And specified
Memory unit 14 according to the address and the requested content₁, 14
₂Memory control unit (DRAMC) 13 for controlling₁, 1
Three₂And the arbitration circuit 12₁, 12₂Based on the SL signal from
Then, connect the Image Address bus line and the PRC Address bus line.
Address line to select address by switching
Multiplexer 11 that is a selection unit₁, 11₂And the tone
Stop circuit 12₁, 12₂Instructions, rioenb signal or prce
It is a switching unit that switches the data line based on the nb signal.
Driver and receiver 15a₁, 15b₁, 15a₂，
15b₂Have and.

[0021] In the figure, "DV / RV1" will be enabled in the bit map memory 1 ₁ during the access from the RIO, "DV / RV
"2" is enabled when accessing the bitmap memory 1 ₁ from PRC, "DV / RV3" is enabled when accessing the bitmap memory 1 ₂ from RIO, and "DV / RV"
4 "is enabled when the bitmap memory 1 ₂ is accessed from the PRC. In this embodiment, two internal buses are provided and connected to the bitmap memories 1 ₁ and 1 _2. ing.

Further, as shown in FIG. 6, the parallel processing section 4 has a PRC-REQ or RIO-REQ which is a start request signal from the printer control section 2 and the drawing processing section 3 and a PRC Address which is an address signal. RIO Address (Image Addres
s) Two activation request distribution units 4 ₁ , 4 which generate activation request signals to the bit map memories 1 ₁ , 1 ₂ based on the signals
Having ₂ . The number of the activation request distribution units of the parallel processing unit 4 corresponding to the number of both the printer control unit and the drawing processing unit, in this case, two are provided. Each activation request distribution unit 4 _1, 4 _2, a decoder 4a _1, 4a ₂ to decrypt the Image buses and PRC bus address signal is an address that is specified during the activation request, the decoder 4a _1, 4
Selection circuit 4 which sends a start request signal to the corresponding bitmap memory based on the decoded signal from a _2.
b ₁ and 4b ₂ .

In FIG. 6, "Image Address" is Image.
This is the address bus signal for the bus interface, and "Im
age Data ”is the data bus of the Image bus interface
This is a signal, and "PRC Address" is the PRC bus interface.
Address bus signal, and "PRC Data" is the PRC buffer
Interface data bus signal, and “SL” is a bus signal.
The map / memory access right is RIO or PRC
Indicates that there is either. “RIO-REQ” is Im
A bitmap from the RIO that is the bus master of the age bus.
Memory access request signal, "RIO-REQ1 / 2" is Im
A bitmap from the RIO that is the bus master of the age bus.
Memory 1₁Or bitmap memory 1 ₂Access to
This is a request signal, and “RIO-ACK 1/2” is the bit of RIO-REQ1 / 2.
It is a response signal to the map memory access request.
“PRC-REQ” is the PRC that is the bus master of the Image bus.
Request signal to the bitmap memory from the
And "PRC-REQ1 / 2" is the bus master of the Image bus.
Bitmap memory 1 from a PRC₁And Bitma
Up memory 1₂Access request signal of "PRC-AC
"K1 / 2" requires PRC-REQ1 / 2 bitmap memory access
It is a response signal to the request signal, "rio-enb1 / 2" is DV / R
V1 and DV / RV3 enable signals (RIO bitmap memory
(During re-access), "prc-enb1 / 2" is DV / RV2, DV / RV4
Navel signal (during PRC bitmap memory access)
 , "Cnt" is bitmap memory 1₁And bit map
Memory 1₂Control signal for (RAS / CAS / W
E) and "adr" is the bitmap memory 1₁as well as
Bitmap memory 1₂With the address bus signal to
is there.

Next, the operation of the printer control apparatus according to this embodiment will be described. Printer control unit (PRC) 2
Or the bitmap memory (B from the drawing processing unit (RIO) 3
MM) 1 ₁ , 1 ₂ activation request RIO-REQ or PRC-REQ
When the signal is designated together with the designation of the address Image Address or PRC Address, the activation request distributors 4 ₁ and 4 ₂ of the parallel processing unit 4 correspond to the corresponding bit map memory 1 ₁ according to the designated address range. , 1 and ₂ , the activation request RIO-REQ1 / 2 or PRCX-REQ1 / 2 is sent.

As long as the activation requests for the designated activation destination bitmap memories 1 ₁ and 1 ₂ do not conflict with each other, the processes for activation of the bitmap memories 1 ₁ and 1 ₂ are performed in parallel. . On the other hand, when the plurality of activation requests from different devices for the same bit map memory 1 _1, 1 ₂ conflict, the arbitration circuit 12 _1, 12 ₂ of each bit map memory 1 _1, 1 _2, the activation request source The activation request from the higher-level device is prioritized according to the priority set in the device.

In this embodiment, since the printer control unit 2 is set to a higher priority than the drawing processing unit 3, in the case of conflict, the activation request from the printer control unit 2 is preferentially adopted, An activation request is made to the bitmap memory, and the corresponding processing is performed. Therefore,
Since the activation request from the printer controller 2 is once every three cycles, the bitmap memory 1 by the printer controller 2 is once every three cycles as shown in FIG.
Reading processing from ₁ and 1 ₂ is performed. At this time, unlike the prior art, in the present embodiment, the processing by the drawing processing unit 3 is performed in parallel even while the activation processing from the printer control unit 2 is being performed. 200ns without being affected by the printer controller
Since the drawing process is continuously performed in a cycle, the performance is improved.

Next, the second embodiment will be described.
In this example, as shown in FIG. 8, unlike the first example,
Bit map memory 1 ₁ and 1 ₂ (however, memory unit 1
4 ₁ and 14 ₂ are excluded) LSI 100 ₁ and 1
00 ₂ provided further, the LSI 100 _1, 10
0 ₂ is provided so that it can be inserted and removed.

Further, the control processor 8 recognizes the insertion / removal of the LSIs 100 ₁ and 100 ₂ and outputs L
An insertion / removal management unit 18 for instructing the printer control device 2 and the drawing processing unit 3 to change the device configuration according to the device configuration corresponding to the insertion / removal of SIs 100 ₁ and 100 ₂ is provided. In this example, low-speed machines to high-speed machines can be supported by cascade connection of bitmap memories. That is, in the case of low-speed aircraft, LS
One I is sufficient, and in the case of a medium-speed machine, two are provided, and in the case of a high-speed machine, three LSIs are provided.
As a result, the processing can be performed with the optimum device configuration scale, and thus the efficient processing can be performed. That is, when performing low-speed processing that is sufficient even if the capacity is low,
Since the bitmap memory having a large capacity hinders the efficiency improvement, it is possible to improve the processing efficiency by deleting the unnecessary memory area.

FIG. 9 shows the bit map memories 1 ₁ and 1 ₂ and the parallel processing section 4. As shown in the figure, each of the bitmap memories 1 ₁ and 1 ₂ is an LSI.
It is provided in. When the number of bitmap memories is increased, the number of activation request distribution units does not increase, but the bitmap memory to be distributed by each activation request distribution unit of the parallel processing unit 4 is Increase,
Therefore, the number of signal lines provided in each activation request distribution unit increases.

When the number of printer control units or drawing processing units is increased, the number of activation request distribution units is increased by the number of printer control units and drawing processing units. However, the number of signal lines provided in each activation request distribution unit does not increase. Therefore, when the number of bitmap memories and the number of printer control units or drawing processing units increase, both the number of activation request distribution units and the number of signal lines of each activation request distribution unit increase. It will be.

Further, another embodiment is shown in FIG. this
In the embodiment, unlike the second embodiment, the printer output unit 5
Bitmap memory 1 of 5₁And bitmap memo
Ri 1 ₂, 1 sheet for parallel processing unit 4 and printer control unit 2
The printed board 110 of FIG. As a result,
-Like image bus interface as it is, drawing processing
Improves character expansion processing by the part (for example, RIO)
You can Thus, in this example,
Since it does not affect the image bus interface,
You can make the most of your assets without changing them
Wear. Also, there is no effect on the back panel.

[0032]

As described above, according to the present invention, the character to the bitmap memory by the drawing processing unit,
By providing the parallel processing unit for the expansion processing of figures and the like and the reading processing of the bitmap memory by the printer control section, it becomes possible to perform the processing in parallel, and by performing the parallel processing, the expansion performance of characters, figures, etc. can be improved. Is improving. Further, according to the present invention, the drawing processing unit (image bus master) can access the bitmap memory without being affected by the reading of the bitmap memory of the printer control unit, so that the performance of the image bus master can be fully exhibited. it can. Further, since the existing technology can be used, it can be realized at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 is a block diagram showing a bitmap memory according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a parallel processing unit according to an embodiment of the present invention.

FIG. 4 is a block diagram showing an embodiment of the present invention.

FIG. 5 is a block diagram showing a printer control device according to the first embodiment.

FIG. 6 is a block diagram showing a bitmap memory according to the first embodiment.

FIG. 7 is a diagram showing an operation according to the first embodiment.

FIG. 8 is a block diagram showing a printer control device according to a second embodiment.

FIG. 9 is a block diagram showing a bitmap memory according to a second embodiment.

FIG. 10 is an overall block diagram according to another embodiment.

FIG. 11 is a block diagram showing an operation and a printer control device according to a conventional example.

FIG. 12 is a block diagram showing a bitmap memory according to a conventional example.

[Explanation of symbols]

_{10 1 ~10 n, 1 1,} 1 2 -bit map memory 20 ₁ ~20 _m, 2 printer controller 30 ₁ ~30 _k, 3 rendering unit 40,4 parallel processing unit _{101 i (11 1, 11 2} ) Address line selection unit (multiplexer) 102 _i , 12 ₁ , 12 ₂ arbitration circuit 103 _i , 13 ₁ , 13 ₂ control unit 104 _i , 14 ₁ , 14 ₂ memory unit 105 _i (15 ₁ , 15 ₂ ) data line selection unit (Driver, receiver)

Claims (4)

[Claims] 1. 1 or 2 for performing various controls of a printer device
More printer control unit and the (20 ₁ ~20 _{m), 1} or 2 or more drawing processing unit performs various drawing processing (30 ₁ - 30
In the printer controller having a _k) and a predetermined address range is allocated, the printer control unit (20 ₁ to 20 _m) and the drawing processor (30 _1-3
0k ) multiple bitmaps that can be activated independently
A memory (10 ₁ ~10 _n), the activation request by the printer control unit (20 ₁ ~20 _m) or the drawing processing unit (30 ₁ ~30 _k) is a to said bit map memory (10 ₁ ~10 _n) And a parallel processing unit (40) for making a parallel activation request to the corresponding bit map memory (10 ₁ to 10 _n ) according to a designated address range. Control device. 2. The bitmap memories (10 _i ;
i = 1 ... n) is activated when the memory unit (104 _i ) for storing data and the activation request from the parallel processing unit (40 _i ) compete in the bitmap memory (10). An arbitration circuit for instructing the selection of the data line and the address line so that the processing by the activation request from the lower level device is interrupted and the activation request from the higher level device is prioritized according to the priority order preset in the request source device ( 102 _i ), and a control unit (103 _i ) for controlling the memory unit (104 _i ) according to a specified address and request content.
Performed when, on the basis of the instruction by the arbitration circuit (102 _i), the address line selector for selecting the address lines and (101 _i), on the basis of the instruction by the arbitration circuit (102 _i), the selection of the data line The high-speed printer controller according to claim 1, further comprising a data line selection unit (105 _i ). 3. The parallel processing section (40)_i) Is the above
Input control unit (20₁~ 20_m) Or a drawing processing unit (30₁
~ 30_k), The startup request is required.
Based on the requested address and the specified address.
Up memory (10₁-10_n) Start request to
Start request distribution unit (41)₁~ 41 _{m + K})
It is provided corresponding to the input controller and the drawing processor.
The high-speed printer controller according to claim 1. 4. 1 or 2 for performing various controls of a printer device
More printer control unit and the (20 ₁ ~20 _{m), 1} or 2 or more drawing processing unit performs various drawing processing (30 ₁ - 30
In the printer controller having a _k) and a predetermined address range is allocated, the printer control unit (20 ₁ to 20 _m) and the drawing processor (30 _1-3
0k ) multiple bitmaps that can be activated independently
A plurality of removable memory (1
9 _{1 to} 19 _n ) and the printer control unit (20 _{1 to} 20 _m ) or the drawing processing unit (30 ₁ to 30 _k ) to the removable memory (19 ₁
〜 19 _n ) when there is a request for activation, the corresponding removable memory (1
The parallel processing unit (40) for making a start request in parallel to 9 _{1 to} 19 _n ) and the insertion / removal of the removable memory (191 _{1 to} 19 _n ) are recognized, and the removable memory (191 _{1 to} 19 _n ) accordance apparatus configuration corresponding to insertion, the printer control unit (20 ₁ -
20 _m), claim 1, claim 2 or claim, characterized by comprising insertion manager for drawing processing unit to (30 ₁ to 30 _k) an instruction corresponding to the device configuration and (18) Three
The described high speed printer controller.