JP4116997B2 - Image processing device - Google Patents

Description

  The present invention converts a plurality of band areas obtained by band-dividing print data for one page into intermediate language data, and sequentially generates output image data corresponding to the intermediate language data for each converted band area. In particular, the image processing apparatus for output is comprehensively simplified by simplifying arithmetic processing (ie, drawing processing) when storing output image data generated from intermediate language data in a drawing area such as a main memory. The present invention relates to an image processing apparatus capable of improving the speed of the image.

2. Description of the Related Art Conventionally, an image processing apparatus such as a printer receives one page of PDL data (PDL: Page Description Language) transferred from a host computer (hereinafter referred to as “host PC”), and this PDL data Is converted into an intermediate language, and output image data such as bitmap data is generated while interpreting the converted intermediate language, and output to the image formation control unit (engine control unit), thereby enabling image formation (printing). Done. Such a data processing method is employed in electrophotographic printers (laser printers, LED printers, etc.). Such printers are collectively referred to as page printers.
In such a page printer, it is necessary to provide a main memory having a capacity enough to store bitmap data for one page generated from PDL data as a minimum condition. Accordingly, the main memory is required to have a large capacity.

On the other hand, there is a band division method as one of the methods for reducing the capacity of the main memory (see the prior art column in Patent Document 1). Here, referring to FIGS. 6 and 7, assuming that the image data 40 for one page shown in FIG. 6 created by the host PC is printed out to the printer, the above band division method is adopted. The image processing will be briefly described. Here, the image data 40 shown in FIG. 6 is an example of image data to be printed out, and is an image in which characters “AB” and “CD” are arranged in the vertical direction (sub-scanning direction) at the upper left corner. It is data. FIG. 7 is an image diagram for explaining a state where the PDL data is divided into bands. The image data 40 shown in FIG. 6 is A4 vertical size image data, but the lower part thereof is omitted.
When the image data 40 is converted into PDL data on the host PC side and transferred to the printer, the transferred PDL data is converted into an intermediate language on the printer side. Further, the converted intermediate language data is divided into a plurality of band regions (band-like regions) B1, B2,... As shown in FIG. Then, bitmap data is sequentially generated for each band area, and is sequentially drawn (stored) in the drawing area of the main memory, and the bitmap data in band units stored in this drawing area is sequentially read, Printed out.
Thus, when the band division method is used, the capacity of the main memory can be reduced to at least the capacity corresponding to the band region.
Further, Patent Document 1 discloses a method of improving the above-described band division method, further subdividing a band region obtained by band division into subband regions, and sequentially performing processing for each subband region. ing.
JP 2001-249774 A

By the way, when reading / writing data from / to the main memory, in order to realize high-speed data processing, generally known cache processing is performed using a cache memory that can be accessed at a higher speed than the main memory.
However, when the above band division method is adopted, as described later, since the number of times of cache processing when rendering (storing) bitmap data in the main memory increases, it is difficult to increase the rendering processing speed. There was a problem.

For example, a case is assumed where bitmap data generated based on the intermediate language data 101 of the band area B1 (see FIG. 7) is drawn in the drawing area 70 (storage area of addresses A0 to A31) of the main memory shown in FIG. . Here, the storage area of one address (memory address) in the drawing area 70 has a capacity of one word. That is, the drawing area 70 is assumed to be a 32-word storage area. Further, it is assumed that the cache memory has a capacity of 8 words. 8A is an image diagram of an image corresponding to the band area B1 drawn in the drawing area 70 when the drawing area 70 in the main memory is assumed to be a drawing canvas, and FIG. 8B is a drawing area in the main memory. It is a figure which shows the address arrangement | sequence of 70. FIG.
Normally, the cache process uses the property that there is a high possibility that an address near the address that has been accessed once will be accessed again when data is read or written. For example, when the address A0 is accessed in order to write data to the address A0, the storage areas A0 to A7 for 8 words (the capacity of the cache memory) after the address A0 are replaced with the cache memory as a unit, and thereafter , Data is written to and from the cache memory. Of course, reading is performed in the same manner.
In this case, in the example shown in FIG. 8, since there is data to be drawn at addresses A0 to A2, the corresponding data is written into the cache memory. At this time, there is no data to be written at addresses A3 to A7. Therefore, three words (A0 to A2) in which data is written in the cache memory and five words (A3 to A7) in which no data is written in the same state are returned to the drawing area of the main memory. As a result, new bitmap data is drawn only at addresses A3 to A7.
Subsequently, the addresses A8 to A15 for the next eight words are replaced with the cache memory, and the bitmap data is drawn at the addresses A8 to A10 in the same manner. Such processing is similarly performed for the addresses A16 to A23 and A24 to A31, so that bitmap data corresponding to the band area B1 is drawn. In this way, when bitmap data is drawn in the drawing area 70 based on the intermediate language data 101 of the band area B1 (see FIG. 7), a total of four cache processes are performed. Further, when the image data 40 shown in FIG. 6 is divided into, for example, N band areas, 4 × N cache processes are performed. This is because the addresses of the image areas of the main memory are sequentially arranged in the main scanning direction (horizontal direction in FIG. 8A).
However, when bitmap data is originally drawn in the drawing area 70, a background color (for example, a white background color) is previously stored in the address areas (A3 to A7, A11 to A15, A19 to A23, and A27 to A31) where no data exists. Since these data (white data) are stored, it is not necessary to access these address areas, and areas where data to be drawn exist (A0 to A2, A8 to A10, A16 to A18, A24 to A26). However, as described above, since data for one column (8 words) in the main scanning direction is cached as a unit as described above, the CPU does not need to access the data. There was no choice but to access the address, and a lot of useless cache processing and memory access processing were performed.
For example, in an image with horizontal writing, the text is created from the left corner to the right. Therefore, when the left and right edge portions of the image are compared, characters are gathered at the left edge portion rather than the right edge portion. It is clear that is high. Therefore, when data such as images of horizontal text that are to be drawn is aggregated in the vertical direction, if the processing is performed in order from the left end to the main scanning direction, the cache processing can be performed. It is obvious that there are many accesses to areas that do not need to be accessed.

  Accordingly, the present invention has been made in view of the above circumstances, and the object of the present invention is to change output image data generated from intermediate language data by changing the address array of a drawing area such as a main memory. An object of the present invention is to provide an image processing apparatus capable of comprehensively improving the speed of image processing by simplifying arithmetic processing (that is, drawing processing) when storing in a drawing area.

To achieve the above object, the present invention converts print data (PDL data) for one page described in a predetermined language into band intermediate language data for each of a plurality of band areas, and the converted band intermediate language data Applied to an image processing apparatus that outputs output image data such as bitmap data generated based on the above, and provided with data storage means having a drawing area in which output image data corresponding to at least one band area is stored, transfer based address of the drawing area to a predetermined rule, and, 1 to the drawing area address output image data the generated was replaced swing as to generate the output image data based on the band intermediate language data It is configured to store sequentially in units of words.
In general, high-speed data processing such as cache processing is performed during image processing. Therefore, the drawing process when the output image data is stored (drawn) in the drawing area is simplified by changing the address as described above. Specifically, the number of high-speed data processes performed during the drawing process is reduced. As a result, the drawing process can be speeded up, and the image processing speed can be increased overall.
In this case, it is preferable that the address array in the main scanning direction of the drawing area is changed in the sub-scanning direction so that the output image data can be sequentially arranged and stored in the sub-scanning direction of the drawing area in units of one word. Specifically, when the drawing area is assumed to be a drawing canvas, the array of addresses in the main scanning direction of the drawn image is changed to the array in the sub-scanning direction. By changing the address of the drawing area as described above, the number of high-speed data processes is reduced to the minimum, and the drawing process in the drawing area is further accelerated.
Here, in the case of further comprising a data high-speed storage means such as a cache memory having a storage capacity smaller than that of the data storage means and capable of high-speed access, the generated output image data is stored for the storage capacity of the data high-speed storage means. It is conceivable that the image data is stored temporarily in the high-speed data storage unit, and the output image data stored in the high-speed data storage unit is stored in the drawing area. With such a configuration, high-speed data processing such as cache processing is realized. As a result, speeding up of the drawing process and speeding up of image processing are specifically realized.

  According to the present invention, since the address of the drawing area is transferred, the drawing process is simplified by reducing the number of high-speed data processing such as cache processing performed during the drawing process. As a result, the drawing process can be speeded up, and the image processing speed can be increased overall.

Hereinafter, embodiments and examples of the present invention will be described with reference to the accompanying drawings so that the present invention can be understood. It should be noted that the following embodiments and examples are examples embodying the present invention, and do not limit the technical scope of the present invention.
FIG. 1 is a block diagram showing an embodiment of an image processing apparatus of the present invention, FIG. 2 is an address array diagram showing a conventional address array and an address array of the present invention, and FIG. 3 is a drawing area in a main memory. FIG. 4 is an image diagram showing an address arrangement when an image corresponding to the band region B1 is drawn, FIG. 4 is a flowchart for explaining an example of a drawing process executed by the memory control unit of the image processing apparatus of the present invention, and FIG. Is a block diagram showing an embodiment of an image processing apparatus of the present invention,
FIG. 6 is a diagram showing an example of image data to be printed, FIG. 7 is an image diagram for explaining a state where PDL data is divided into bands, and FIG. 8 is a band area B1 in the drawing area of the main memory by the conventional method. It is an image figure which shows the address arrangement | sequence when the image corresponding to is drawn.

First, the schematic configuration of the image processing apparatus according to the present embodiment will be described with reference to the block diagram of FIG. FIG. 1 is a block diagram of the processing control system of the image processing apparatus. The image processing apparatus according to the present invention corresponds to a printer or a multifunction peripheral (MFP) having a printer function.
The image processing apparatus of the present invention converts one page of PDL data (corresponding to print data) expressed in PDL (page description language), which is an example of a predetermined language, into band intermediate language data for each of a plurality of band areas. Then, processing for outputting bitmap data (output image data) generated based on the converted band intermediate language data is performed.
As shown in FIG. 1, the image processing apparatus includes an intermediate language conversion unit 1, a memory control unit 2, a main memory 3 (an example of data storage means), an output buffer 5, and an engine control unit 6. It is roughly composed. In the present embodiment, the intermediate language conversion unit 1 is described as hardware such as an ASIC configured by hardware logic or the like. For example, an arithmetic operation based on a predetermined program is performed by an image processing control unit (CPU) (not shown). The processing in the intermediate language conversion unit 1 may be realized by the processing.

The intermediate language conversion unit 1 receives one page of PDL data transferred from a host computer or the like connected to a network such as a LAN, and divides it into a plurality of band areas, A process of sequentially converting the band area into intermediate language data from the top of the PDL data is performed. Specifically, all of the transferred one page of PDL data is temporarily converted into intermediate language data and stored in an internal memory (not shown) of the intermediate language conversion unit 1, and then the converted intermediate language data is stored. A band division process is performed in order from the top of the image.
Here, FIG. 6 shows image data 40 in which only the characters “AB” and “CD” are arranged in the vertical direction (sub-scanning direction) at the upper left corner and drawn in the A4 vertical size. 7 shows a plurality of band regions B1, B2,... Obtained by dividing the PDL data of the image data 40 of FIG. 6 in the vertical direction (sub-scanning direction) of A4 vertical size. In the following description of the embodiment, an example will be taken in which the PDL data of the image data 40 shown in FIG. 6 is transferred, and the PDL data is subjected to drawing processing on a plurality of band regions divided as shown in FIG. I will explain. Of course, the present invention is not limited to such processing examples.

The main memory 3 is a storage device such as a readable / writable DRAM (Dynamic RAM) or SDRAM (Synchronous DRAM). The main memory 3 stores bitmap data generated based on the intermediate language data converted by the intermediate language conversion unit 1. Accordingly, the main memory 3 has a drawing area 30 (see FIGS. 2 and 3) in which the generated bitmap data is stored (drawn). Here, the main memory 3 is illustrated as an example of the data storage means, but a large-capacity storage medium such as an HDD may be used instead of the main memory 3.
In this embodiment, bitmap data is generated for each of a plurality of band areas divided by the intermediate language conversion unit 1 and stored in the drawing area 30. Therefore, it is sufficient that the drawing area 30 has a capacity capable of storing bitmap data corresponding to at least one band area. In the present embodiment, as shown in the image diagrams of FIGS. 2 and 3A, the drawing area 30 has a capacity of a total of 32 words in which 8 words are arranged in the main scanning direction and 4 words are arranged in the sub-scanning direction. A cache 20a described later has a capacity of 8 words.
3A is an image diagram of an image corresponding to one band area B1 drawn in the drawing area 30 when the drawing area 30 in the main memory 3 is assumed to be a drawing canvas. FIG. FIG. 4 is a diagram showing an address array of a drawing area 30 in the main memory 3.

The memory control unit 2 controls the intermediate language interpretation unit 21, the address transfer unit 23 (an example of an address transfer unit), controls these units, and writes (draws and stores) bitmap data to the main memory 3. And a CPU 20 that executes reading. The intermediate language interpretation unit 21 and the CPU 20 are examples of output image data generation and storage means.
In this embodiment, the intermediate language interpretation unit 21 and the address transfer unit 22 are both described as circuit boards and ICs configured by hard logic or the like. However, the processing in each unit is a processing example in which the CPU 20 performs program processing. May be.

  The CPU 20 executes a cache process so as to speed up the process when reading / writing data from / to the main memory 3. Therefore, the CPU 20 can be accessed at a higher speed than the main memory 3 and is abbreviated as a cache memory (hereinafter referred to as “cache”) such as a small capacity (capacity of 8 words) SRAM (Static RAM). An example) 20a is provided. The cache 20a only needs to be accessible at a higher speed than the main memory 3. Therefore, when an HDD having an access speed slower than the memory is used instead of the main memory 3, not only the SRAM having a higher speed than the HDD but also the SRAM DRAM, SDRAM, etc. can be used as the cache memory.

  The intermediate language interpretation unit 21 generates bitmap data based on the intermediate language data for each band area converted by the intermediate language conversion unit 1. When the intermediate language data is data in the band area B1 (see FIG. 7), the intermediate language data includes image information “AB”, position information of the image information “AB” in the band area B1, In this case, the intermediate language interpretation unit 21 interprets (decodes) each of these pieces of information because at least the information on the white background portion other than the image “AB” is included. To generate bitmap data.

The address transfer unit 22 performs an address transfer process of transferring the address of the drawing area 30 of the main memory 3 based on a predetermined rule. This address transfer process is executed before the bitmap data is drawn (stored) in the drawing area 30 by the CPU 20.
Normally, the address array of the drawing area 30 in the main memory 3 is sequentially arranged in the main scanning direction (horizontal direction) as shown in FIG. 2A. The address array in the main scanning direction of the drawing area 30 is arranged in the sub-scanning direction so that the bitmap data generated by the drawing processing unit 22 can be sequentially stored in the sub-scanning direction of the drawing area in units of one word. Transferred. In other words, a process of changing the address array shown in FIG. 2A to the address array shown in FIG. 2B is performed. Here, FIG. 2A shows a drawing area 30 of a conventional address array, and FIG. 2B shows a drawing area 30 whose address is transferred by the address transfer unit 23.

The address transfer by the address transfer unit 22 is performed by, for example, a known chain pointer method using a chain and a pointer as shown in FIG. In this chain pointer method, a descriptor area storing information such as an address to be accessed next and a start address is prepared in advance in a storage area such as the main memory 3, and a pointer linked to the descriptor area is set in the drawing area 30. It is attached to each address. In this way, when an address is accessed, the address to be accessed next can be determined by referring to the information in the descriptor area linked to the pointer attached to the access. Linking addresses in this way is called “stretching a chain”.
By using this method, for example, if a ruled chain is set between the pointers attached to each address in the drawing area 30 so as to follow addresses A0 → A4 → A8. The access order when accessing data in the area 30 is the order determined by the pointer and the chain. By changing the access order to the drawing area 30 in this way, the address of the drawing area 30 is apparently transferred from FIG. 2A to FIG. 2B and FIG. 3A. Will be.

なお，アドレスの振り替えは前記チェーンポインタ方式や上記関数Ｆ（ｘ）に限らず，他の種々の方式を採用することも可能である。 Further, instead of the chain pointer method, a function of the following expression (1) for converting an address to be accessed may be used.
F (x) = G _a (x) × b + H _a (x) (1)
Here, in the above equation (1), “F (x)” is an address after address conversion, “x” is an address to be accessed when the CPU 20 stores data in the drawing area 30, and “a” is one. The number of arrangements of unit data in the main scanning direction of the image data drawn in the band area of “1”, “b” is the number of arrangements of unit data in the same sub-scanning direction, and “G _a (x)” is when x is divided by a “H _b (x)” represents the quotient when x is divided by a. In the present embodiment, the unit data refers to data having a capacity for one word.
By using the function F (x) in the address transfer unit 22, the address to be accessed when the CPU 20 tries to access when storing data in the drawing area 30 is converted by the function F (x). In this way, address transfer is realized.
For example, the function F (x) for accessing the drawing area 30 of 4 × 8 words shown in FIG. 2 is expressed as the following expression (2) by substituting a = 8 and b = 4.
F (x) = G ₈ (x) × 4 + H ₈ (x) (2)
According to the equation (2), for example, the address (A0 to A31) to be accessed to the drawing area 30 is converted as the following equation (3).

Note that the address transfer is not limited to the chain pointer method and the function F (x), and various other methods can be employed.

The output buffer 5 has a FIFO memory or the like, and outputs the bitmap data transferred from the drawing area 30 to the engine control unit 6 in that order.
The engine control unit 6 performs control for forming an image according to the bitmap data output from the output buffer 5.

Next, an example of a schematic procedure of the drawing process executed by the memory control unit 2 will be described using the flowchart of FIG. 4 with reference to FIGS. In the figure, S10, S20,... Indicate processing procedure numbers (step numbers). The process starts from S10.
As described above, when the PDL data of the image data 40 shown in FIG. 6 is transferred from a host PC or the like and divided into a plurality of band regions B1, B2,... By the intermediate language conversion unit 1 (see FIG. 1), The intermediate language conversion unit 1 sequentially outputs intermediate language data to the memory control unit 2 from the band region B1 at the head of the image.
When the intermediate language data is output in this way, in the memory control unit 2, the CPU 20 determines whether or not the intermediate language data 101 (see FIG. 7) of the band area B1 is input from the intermediate language conversion unit 1. (Step S20).
When the input of the intermediate language data 101 is confirmed, the CPU 2 instructs the address transfer unit 23 to change the address array of the drawing area 30 of the main memory 3 as shown in FIG. (Step S20).
Thereafter, the input intermediate language data 101 is transferred by the CPU 20 to the intermediate language interpretation unit 21, and the intermediate language interpretation unit 21 creates bitmap data based on the intermediate language data 101 (step S30). ). For example, in the case of the band region B1, the bitmap data created here is the background color (white) image data and the image data “AB”.

The bitmap data created by the intermediate language interpreter 21 is sequentially drawn (stored) by the CPU 20 from the storage area at the address A0 in the drawing area 30.
This drawing process is performed according to the following procedure. First, background color (white) image data is stored at all addresses in the drawing area 30.
Thereafter, in order to store the image data “AB” in the drawing area 30, the first cache processing is performed. Specifically, addresses A0 to A7 corresponding to the capacity of the cache 20a from the address A0 (8 words in this embodiment) are temporarily read (stored) in the cache 20a, and image data is transferred to and from the cache 20a. Transfer of D1 (see FIG. 3A) is performed.
In the conventional method, the addresses of the drawing areas are arranged in the main scanning direction as shown in FIG. 2A, but in this embodiment, the addresses are arranged in the sub-scanning direction (vertical direction) as shown in FIG. Therefore, there is data to be written to all of the addresses A0 to A7 read into the cache 20a. Therefore, at this time, data is transferred to all of the addresses A0 to A7 read into the cache 20a. The cache hit rate at this time is 100%.
When the transfer of the image data D1 is completed, the data in the cache 20a is returned to the drawing area addresses A0 to A7. Thus, first, the image data D1 is drawn at addresses A0 to A7 of the drawing area 30.
Subsequently, a second cache process is performed. That is, eight words of addresses A8 to A15 are read into the cache 20a from the next address A8, and the image data D2 (see FIG. 3A) is transferred to the cache 20a in the same manner as described above. Done. In this case, data is transferred to addresses A8 to A11. The cache hit rate at this time is 50%. When this data transfer is completed, the data in the cache 20a is returned to the addresses A8 to A15 in the drawing area 30. As a result, the image data D2 is drawn at addresses A8 to A11 of the drawing area 30. Since the data is returned to the addresses A12 to A15 without being transferred, the white color image data drawn in advance is still stored in the address.
Thus, since the image “AB” to be drawn is drawn by two cache processes, the CPU 20 does not need to access the drawing area 30 any more. That is, since there is no image to be drawn at the addresses A16 to A31, these addresses are not accessed. Therefore, the third and subsequent cache processing is not performed.
By performing such a drawing process, bitmap data corresponding to the band area B1 is drawn in the drawing area 30. As described above, in the present embodiment, since the drawing process accompanied by the cache process with a high hit rate is performed on the drawing area 30 to which the address has been transferred, the cache process with a low hit rate is performed many times (as described above). In this example, the bitmap data can be drawn (stored) in the drawing area 30 without performing it four times. Therefore, the drawing process is accelerated accordingly.

When the drawing processing of the bitmap data corresponding to the band area B1 is completed in step S40, it is subsequently determined whether the data in the drawing area 30 has been transferred to the output buffer 5 (S50). It is then determined whether intermediate language data for the next band area has been input (S60). If it is determined that the intermediate language data of the next band area B2 has been input, the process from step S20 is repeated, and the drawing process of the image “CD” to be drawn is executed.
In this way, when the drawing process is completed for the intermediate language data in all the band areas and no intermediate language data is input, a series of processes is thereafter terminated.
In the image data 40 of FIG. 6 used in the present embodiment, since there is no image to be drawn after the band region B3, the processes of steps S20 to S40 are omitted. That is, even if intermediate language data of the next band area is input, if it is determined that there is no data to be rendered, the processing from step S50 is performed without performing the processing of steps S20 to S40. Repeated. As a result, useless address transfer processing or the like when there is no data to be drawn is omitted, so that the drawing processing speed can be increased.

In the above-described embodiment, the bitmap data read processing (data output processing to the output buffer 5) drawn (stored) in the drawing region 30 is performed by accessing the drawing region 30 in the order according to the transferred address. Done. In other words, not only during the bitmap data rendering process but also during the bitmap data readout process, the readout process is performed in the order of the transferred addresses.
However, the process of accessing a distant address is more complicated than the process of accessing the next address or an adjacent address, and requires a lot of processing time.
In this case, as shown in FIG. 5, a mapping processing unit 4 for mapping the bitmap data transferred from the main memory 3 is provided, and the CPU 20 cancels the chain, the pointer, etc. stretched on the drawing area 30 or It is preferable that the bitmap data is read out in order from the address A0 of the main memory 3 and transferred to the mapping processor 4 after being invalidated.
When the address transfer unit 22 performs the address transfer process using the function F (x) of the equation (1), when reading data from the drawing area 30, the bits are sequentially written from the address A0. It is preferable that the map data is read out and transferred to the mapping processing unit 4.
With this configuration, the reading process from the drawing area 30 of the main memory 3 is not limited to a chain or the like, but is read in order (A1, A2,...) From the head address A0. Will not drop.
The mapping processing unit 4 is configured by hardware such as an ASIC including a mapping circuit and an internal memory, and the mapping processing unit 4 reads out one word in the order of A0, A1, A2,. If the image pieces of the unit are mapped, the CPU 20 simply transfers the bitmap data to the mapping processing unit 4 and the mapping is executed without the CPU 20 being involved. Therefore, the CPU 20 can perform other processes such as address transfer even during the mapping process. Therefore, there is no delay in the reading process of bitmap data, and the processing speed from the drawing process to the reading process can be increased.

In the embodiment described above, the image data 40 in which only the characters “AB” and “CD” are drawn in the vertical direction (sub-scanning direction) at the upper left corner, that is, the image to be drawn at the upper left corner is collected. Although the image data 40 has been described as an example, the image to be printed out is not always the image data 40 described above. For example, horizontally long image data such as ruled lines extending in the main scanning direction may be printed out. Even for such image data, if the above-described processing is performed by changing the address, the cache hit rate decreases.
Therefore, in this embodiment, based on various information included in the intermediate language data input in the intermediate language interpretation unit 21, it is determined what kind of image data the band area to be rendered is. As a result of the determination, if it is determined that the image data in the band area is a horizontally long image such as a ruled line that is long in the main scanning direction, that is, the address transfer process of the present invention (see step S40 in FIG. 4). If it is determined that the image data is such that the number of cache processing times during rendering processing is increased, the rendering processing is performed by the conventional method without performing the address transfer processing. If it is determined that the image data has been aggregated to some extent and the conventional method increases the number of cache processes, the address transfer process described in the above embodiment is performed. Perform a drawing process after Tsu.
Thereby, it is possible to increase the drawing processing speed regardless of what kind of image data is drawn.

1 is a block diagram showing an embodiment of an image processing apparatus of the present invention. The address arrangement | sequence figure which shows the conventional address arrangement | sequence and the address arrangement | sequence of this invention. FIG. 3 is an image diagram when an image corresponding to one band area B1 is drawn in the drawing area 30 of the main memory 3, and a diagram showing an address arrangement of the drawing area 30 in the main memory 3. 6 is a flowchart for explaining an example of a drawing processing procedure executed by a memory control unit of the image processing apparatus according to the invention. 1 is a block diagram showing an embodiment of an image processing apparatus of the present invention. The figure which shows an example of the image data printed out. The image figure for demonstrating the state by which PDL data was divided into bands. The image figure when the image corresponding to one band area | region B1 is drawn on the drawing area 70 of the main memory by the conventional method, and the figure which shows the address arrangement | sequence of the drawing area 70 in the main memory.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Intermediate language conversion part 2 ... Memory control part 3 ... Main memory (an example of a data storage means)
4 ... Mapping processing unit 5 ... Output buffer 6 ... Engine control unit 20 ... CPU
20a ... Cache memory (an example of data high-speed storage means)
21 ... Intermediate language interpretation unit 22 ... Drawing processing unit 23 ... Address conversion unit 30 ... Drawing area

Claims (3)

An image processing apparatus that converts print data for one page described in a predetermined language into band intermediate language data for each of a plurality of band areas, and outputs output image data generated based on the converted band intermediate language data Because
Data storage means having a drawing area for storing output image data corresponding to at least one band area;
Address transfer means for transferring the address of the drawing area based on a predetermined rule;
Output image data generated for sequentially storing the output image data said generated in units of one word in the drawing area address has been changed swing by the address transfer means and generates the output image data based on the band intermediate language data Storage means;
An image processing apparatus comprising: The address transfer means is
The address array in the main scanning direction of the drawing area is rearranged in the sub-scanning direction so that the output image data generating and storing means can sequentially store the output image data in the sub-scanning direction of the drawing area in units of one word. The image processing apparatus according to claim 1. A data high-speed storage means having a smaller storage capacity than the data storage means and capable of high-speed access;
The output image data generation / storage means temporarily stores the generated output image data in the data high speed storage means by the storage capacity of the data high speed storage means, and further stores the output image data stored in the data high speed storage means. The image processing apparatus according to claim 1, wherein data is stored in the drawing area.

Images