JP5966805B2 - Control device for printing - Google Patents

Description

  The technology disclosed in this specification relates to a control device for printing. In particular, the present invention relates to a control device including a plurality of processors.

  Patent Document 1 discloses a printing apparatus. The printing apparatus includes a first CPU and a second CPU. Each of the first CPU and the second CPU can execute both a process for converting print data into intermediate-stage data and a process for converting intermediate-stage data into bitmap data.

JP 2003-251867 A

  The present specification provides a technique for reducing the capacity of a memory used when bitmap data is generated by a plurality of processors.

  The technology disclosed by this specification is a control device for printing. The control device includes a first processor and a second processor. Each of the first processor and the second processor uses one page of PDL data among a plurality of pages of PDL data to generate intermediate code data for one page; A bitmap generation process for generating bitmap data using the generated intermediate code data is executed using a plurality of pages of PDL data until bitmap data for a plurality of pages is generated. Each of the first processor and the second processor performs intermediate code generation processing among PDL data for a plurality of pages in the first case where another processor different from the processor executes the bitmap generation processing. Thus, intermediate code generation processing is executed using PDL data for one page for which generation of intermediate code data has not yet been completed. Each of the first processor and the second processor, in the second case where the other processor is not executing the bitmap generation processing, among the generated intermediate code data, bitmap data by the bitmap generation processing Bitmap generation processing is executed using intermediate code data that has not yet been generated.

  There is a high possibility that the amount of memory used while the processor executes the bitmap generation processing is larger than the amount of memory used while the processor executes the intermediate code generation processing. In the above control device, when one processor is executing the bitmap processing, the other processor executes the intermediate code generation processing. For this reason, it is possible to avoid a situation in which the first processor and the second processor execute bitmap processing at the same time. According to this configuration, the memory capacity used when the first processor and the second processor generate bitmap data from PDL data can be reduced.

  Note that a control method, a computer program, and a computer-readable recording medium storing the computer program for the control device are also novel and useful.

An example of a structure of a communication system is shown. An example of PDL data for a plurality of pages is shown. The flowchart of a PDL process is shown. The flowchart of a setting command process is shown. The flowchart of both command processing is shown. The flowchart of a BMP process is shown. An example of the time transition for demonstrating a mode that CPU performs a process in parallel is shown.

(First embodiment)
(System configuration)
As shown in FIG. 1, the communication system 2 includes a PC (peripheral device of the printer 10) 6 and a printer 10. The PC 6 and the printer 10 can communicate with each other via the LAN 4.

(Configuration of Printer 10)
The printer 10 includes an operation unit 12, a display unit 14, a print execution unit 16, a network interface 18, and a control unit 20. Each of the above-described units 12 to 20 is connected to a bus line (reference numeral omitted). The operation unit 12 includes a plurality of keys. The user can give various instructions to the printer 10 by operating the operation unit 12. The display unit 14 is a display for displaying various information. The print execution unit 16 includes a printing mechanism such as an inkjet method or a laser method, and executes printing in accordance with an instruction from the control device 20. The network interface 18 is connected to the LAN 4.

  The control unit 20 includes an IC (abbreviation of integrated circuit) 22 and a memory 30. The IC 22 includes two CPUs 24 and 26 and a cache memory 28. Each CPU 24, 26 executes various processes according to a program 48 stored in the memory 30. The CPUs 24 and 26 can execute processing in parallel (simultaneously).

  The cache memory 28 is a memory for temporarily storing data used when the CPUs 24 and 26 execute processing. The memory capacity (for example, 32 kBytes) of the cache memory 28 is very small compared to the memory capacity of the memory 30 (for example, 20 MByte). On the other hand, the data size that each CPU 24, 26 can write in the cache memory 28 per unit time is extremely large compared to the data size that each CPU 24, 26 can write in the memory 30 per unit time. The same applies to the data size that each CPU 24 and 26 can read out per unit time. That is, when the CPUs 24 and 26 execute processing using only the cache memory 28, the processing speed of the CPUs 24 and 26 is higher than when processing is executed using the cache memory 28 and the memory 30. high. When the two CPUs 24 and 26 execute processing in parallel, the two CPUs 24 and 26 use one cache memory 28 jointly.

  The memory 30 includes a ROM, a RAM, a hard disk, and the like. The memory 30 includes a program storage area 46, a shared memory area 50, and various data storage areas 70 to 74. The program storage area 46 stores a program 48 executed by the CPUs 24 and 26.

  The shared memory area 50 is a memory area shared by the CPUs 24 and 26. The shared memory area 50 includes a common processing page counter 60 (hereinafter referred to as “CPC (Common Process page Counter) 60”) and a common setting data counter 62 (hereinafter referred to as “CSC (Common Setting data Counter) 62”. ), A setting command processing flag 64 (hereinafter referred to as “SPF (abbreviation of Setting command Process Flag) 64”), and a bitmap generation processing flag 66 (hereinafter referred to as “BPF (abbreviation of Bitmap generating Process Flag)”). 66 ”), setting data 52, and intermediate code data table 54 are stored.

  The CPC 60 is a counter indicating a page to be processed in the PDL (abbreviation of page description language) process of FIG. The CSC 62 is a counter indicating up to which page setting data (details will be described later) has been generated. The SPF 64 is a flag indicating whether any CPU 24 or the like is executing the setting command process of FIG. The BPF 66 is a flag indicating whether any CPU 24 or the like is executing the BMP (abbreviation of Bit Map) process of FIG. The setting data 52 is data generated when the CPU 24 or the like executes a setting command described later. The intermediate code data table 54 is a table for registering a data name for identifying intermediate code data.

  The PDL data storage area 70 is a storage area for storing PDL data received from the PC 6 or the like. The intermediate code data storage area 72 is a storage area for storing intermediate code data. The intermediate code data is data generated by the CPU 24 and the like executing both command processes in FIG. The BMP data storage area 74 is a storage area for storing bitmap data. The bitmap data is data generated when the CPU 24 or the like executes the BMP process of FIG.

(PDL data structure)
PDL is a concept that includes all languages for describing data using the concept of pages. Examples of PDL include PDF (Portable Document Format) and PS (Post Script). Of the languages used in word processing software, spreadsheet software, drawing software, etc., a language for describing data using the concept of pages is also an example of PDL.

  The user can generate PDL data by using an application stored in the PC 6. When the user desires to print an image represented by the PDL data, the user can add an operation for transmitting the PDL data to the printer 10 to the operation unit of the PC 6. In this case, the PC 6 transmits the PDL data to the printer 10.

  FIG. 2 shows an example of PDL data for a plurality of pages. The PDL data for the first page includes five lines of text data indicating alphabets “A” to “E”. The text data of the first line included in the PDL data of the first page includes a drawing command indicating the text “A” and a setting command indicating the character size “10 pt”. Accordingly, the printer 10 can know that the text “A” should be described with the character size “10 pt” by reading the text data of the first line.

  The text data of the second line included in the PDL data of the first page includes a drawing command indicating the text “B”. However, the text data on the second line does not include a setting command indicating the character size. In this case, the printer 10 can know that the text “B” should be described with the same character size “10 pt” as the previous line (the first line in this example). Similarly, the text data of the third line included in the PDL data of the first page includes a drawing command indicating the text “C” but does not include a setting command indicating the character size. In this case, the printer 10 can know that the text “C” should be described with the character size “10 pt”. As described above, when the same character size is continuously used over two or more lines, a setting command indicating the character size may not be described in the subsequent lines.

  Similarly, the printer 10 should describe the texts “D” and “E” with the character size “20 pt” by reading the text data of the fourth and fifth lines included in the PDL data of the first page. Can know.

  The PDL data on the second page includes three lines of text data indicating alphabets “F” to “G”. The text data of the first line included in the PDL data of the second page includes a drawing command indicating the text “F”, but does not include a setting command indicating the character size. In this case, the printer 10 knows that the text “F” should be described with the same character size “20 Pt” as the last line (ie, “E”) of the PDL data of the previous page (ie, the first page). it can. As described above, when the same character size is continuously used for two or more pages, the setting command indicating the character size may not be described in the subsequent pages.

  Similarly, the printer 10 should describe the text “G” with the character size “20 pt” by reading the text data of the second and third lines included in the PDL data of the second page, and the character It is possible to know that the text “H” should be described with the size “30 pt”.

  The drawing command is not limited to text format data, and may be vector format data or image format data (that is, bitmap data such as JPEG). The setting command is not limited to the character size, and may be a character font (ie, Times New Roman, etc.), a character decoration (ie, bold, shaded, etc.) Or the size of a page (that is, the size of a print medium such as A4 or B4).

  As will be described in detail later, for example, the CPU 24 generates the intermediate code data of the first page using the PDL data of the first page, and then uses the intermediate code data of the first page, Bitmap data for the first page is generated. Then, the CPU 24 supplies the bitmap data of the first page to the print execution unit 16. As a result, the print execution unit 16 executes printing based on the bitmap data of the first page. Similarly, for example, the CPU 26 generates the intermediate code data of the fourth page using the PDL data of the fourth page, and then uses the intermediate code data of the fourth page to map the bitmap of the fourth page. Generate data. Then, the CPU 26 supplies the bitmap data of the fourth page to the print execution unit 16.

  As described above, in this embodiment, the printer 10 generates bitmap data from the PDL data through the intermediate code data. The intermediate code data is data described in an intermediate language determined in advance by the vendor of the printer 10. For example, the intermediate language may be a language uniquely developed by the vendor of the printer 10 or may be a known language.

  A method of generating bitmap data directly from PDL data without using intermediate code data (hereinafter referred to as “direct method”) is conceivable. In the direct method, in order to realize printing according to a plurality of types of PDL data (for example, PS (Post Script), PDF (Portable Document Format, etc.)), for each of a plurality of types of PDL data, A program for directly generating bitmap data from PDL data is required, and in this case, a large-capacity memory capable of storing many programs must be installed in the printer.

  On the other hand, in the configuration of the present embodiment using intermediate code data, for each of a plurality of types of PDL data, there is a program for generating intermediate code data described in a common intermediate language from the types of PDL data. is necessary. A program for generating bitmap data from the intermediate code data is required. According to this configuration, it is possible to share a program for generating bitmap data from intermediate code data for a plurality of types of PDL data. Therefore, the total program amount for generating bitmap data from a plurality of types of PDL data can be smaller than that of a direct method.

(PDL processing; Fig. 3)
Next, the PDL process executed by each of the CPUs 24 and 26 will be described with reference to FIG. When receiving the PDL data (see FIG. 2) from the PC 6, the CPUs 24 and 26 execute the PDL processing in parallel. That is, while the CPU 24 is executing the PDL process, the CPU 26 can also execute the PDL process. In the following, the contents of each process will be described with the CPU 24 as the main body, but the CPU 26 executes the same process.

  In S10, the CPU 24 reads the value of the CPC 60 (common processing page counter (see FIG. 1)) from the shared memory area 50, and determines the value of the CPC 60 as the processing page number. The initial value of CPC 60 is “1”. For example, the CPU 24 determining “M” as the processing page number means that the CPU 24 determines the PDL data of the Mth page as the processing target of S14 to S26.

  Next, in S12, the CPU 24 adds “1” to the value of the CPC 60 read in S10 to calculate a new value of the CPC 60 (for example, “2”). Then, the CPU 24 writes the new CPC 60 value in the shared memory area 50. As a result, for example, when the other CPU 26 executes the process of S10, the value of the new CPC 60 (for example, “2”) is determined as the process page number. In this example, the CPU 26 determines the PDL data of the second page as a processing target in S14 to S26. As is apparent from this description, each of the CPUs 24 and 26 uses each different page of PDL data in ascending order from the PDL data of the first page among the PDL data of a plurality of pages. Execute the process.

  Next, in S14, the CPU 24 reads the value of the CSC 62 (common setting data counter (see FIG. 1)) from the shared memory area 50, and determines whether or not the processing page number “M” determined in S10 is larger than the value of the CSC 62. Judging. The initial value of the CSC 62 is “1”. If the processing page number “M” is larger than the value of CSC62 (YES in S14), the process proceeds to S16. If the processing page number “M” is equal to the value of CSC62 (NO in S14), Proceed to S20. If the processing page number “M” is larger than the value of the CSC 62 (YES in S14), setting data up to one page before the page indicated by the processing page number “M” (that is, up to the M−1th page). Setting data) has not been generated, and if the processing page number “M” is equal to the value of the CSC 62 (NO in S14), the setting up to one page before the page indicated by the processing page number “M” This means that data (that is, setting data up to the (M-1) th page) has been generated.

  In S16, the CPU 24 reads the value of the SPF 64 (setting command processing flag (see FIG. 1)) from the shared memory area 50 and determines whether or not the value of the SPF 64 is “1”. If the value of SPF64 is “1” (YES in S16), the process proceeds to S14, and if the value of SPF64 is “0” (NO in S16), the process proceeds to S18.

  When the value of the SPF 64 is “1” (YES in S16), the other CPU 26 executes the setting command process in S18. In such a situation, the CPU 24 returns to S14 without executing the setting command processing of S18, and as a result, waits until the setting command processing of the other CPUs 26 is completed.

  On the other hand, when the value of the SPF 64 is “0” (NO in S16), the other CPU 26 has not executed the setting command processing in S18. In such a situation, the CPU 24 executes the setting command process of S18.

(Setting command processing; FIG. 4)
In the setting command process, in S40, the CPU 24 changes the value of the SPF 64 in the shared memory area 50 from “0” to “1”. Next, in S42, the CPU 24 reads the value of the CSC 62 from the shared memory area 50, and sets the value of the CSC 62 (for example, “1”) as the value of a self-setting data counter (hereinafter referred to as “OSC (Own Setting data Counter)”). Determine as. Further, the CPU 24 writes the OSC value (for example, “1”) in the cache memory 28. The OSC is a counter indicating the page number (for example, “1”) that is the processing target of the current setting command processing.

  Next, in S <b> 44, the CPU 24 acquires the setting data 52 by reading the setting data 52 from the shared memory area 50. As will be described later, the setting data 52 is written in the shared memory area 50 in S60 of FIG. 4 or S98 of FIG. For example, when the OSC value determined in S42 is “N”, the setting data 52 up to the (N−1) th page is normally written in the shared memory area 50. Therefore, in S44, the CPU 24 obtains the setting data 52 (for example, the character size “20pt”, the character decoration “bold”, and the character color “black”) from the shared memory area 50 to the (N−1) th page. Then, the setting data 52 is written into the cache memory 28. When the value of OSC (that is, “N”) is “1”, the setting data has not been written in the shared memory area 50 yet. In this case, the CPU 24 skips S44.

  Next, in S <b> 46, the CPU 24 reads from the PDL data storage area 70 one page of PDL data indicated by the OSC value determined in S <b> 42. In the process of reading one page of PDL data, the CPU 24 executes the processing after S48 every time one command is read. In the following, one command to be processed in the processes after S48 is referred to as a “specific command”. For example, when the PDL data read in S46 is the PDL data of the first page in FIG. 2, the CPU 24 first specifies the text “A” that is a drawing command included in the text data of the first line. As a command, the processing after S48 is executed. Thereafter, the CPU 24 executes the processing from S48 onward with the character size “10pt”, which is a setting command included in the text data on the first line, as a specific command.

  In S48, the CPU 24 determines whether or not the specific command is a command indicating the end of the page. If the specific command is a command indicating the end of the page (YES in S48), the process proceeds to S58. If the specific command is not a command indicating the end of the page (NO in S48), S50 is executed. Proceed to

  In S50, the CPU 24 determines whether or not the specific command is a setting command. If the specific command is a setting command (YES in S50), the process proceeds to S52. If the specific command is not a setting command (NO in S50), the process proceeds to S54.

  In S52, the CPU 24 executes a setting command (that is, a specific command) to generate setting data. For example, when the PDL data received from the PC 6 is PDL data described in a specific type (for example, PS) of PDL, the CPU 24 first generates intermediate code data from the specific type of PDL data. The program code describing the setting command is analyzed by using the program to do this, and the content of the setting command (for example, the character size “30 pt”) is interpreted. Next, the CPU 24 generates setting data corresponding to the interpreted contents in the cache memory 28.

  For example, when the PDL data of the first page in FIG. 2 is the processing target of the setting command process, the CPU 24 reads the setting command (character size “10 pt”) included in the text data of the first line in S46. In S52, setting data corresponding to the character size “10pt” is generated in the cache memory 28. Thereafter, when the CPU 24 reads a setting command (character size “20 pt”) included in the text data on the fourth line in S46, the character size “10” is substituted for the setting data corresponding to the character size “10 pt” in S52. Setting data corresponding to “20 pt” is generated in the cache memory 28. That is, when the CPU 24 generates new setting data corresponding to the specific setting type (“character size” in the above example) in S52, the old setting data corresponding to the specific setting type is stored. If it is already stored in the cache memory 28, the old setting data is erased and new setting data is stored in the cache memory 28. However, in this case, the CPU 24 does not change setting data (for example, character decoration “bold”, character color “black”) corresponding to other setting types in the cache memory 28.

  Further, for example, when the PDL data on the second page in FIG. 2 is the processing target of the setting command process, the CPU 24 sets the setting command (character size “30 pt”) included in the text data on the third line in S46. In S52, setting data corresponding to the character size “30pt” is generated in the cache memory 28 instead of setting data corresponding to the character size “20pt”.

  When the setting data is generated from the setting command, the CPUs 24 and 26 need not read the setting command again and need to read the setting data when the contents of the setting command are to be used in later processing. As described above, in order to interpret the contents of the setting command, the CPUs 24 and 26 use a program for generating intermediate code data from a specific type of PDL data and describe the setting command. The code needs to be analyzed and takes a relatively long time. On the other hand, if the setting data is generated as in this embodiment, the CPU does not need to analyze the program code, and can read the setting data by reading the setting data. That is, the CPU can acquire the contents of the setting command in a relatively short time in the subsequent processing.

  On the other hand, in S54, the CPU 24 determines whether or not the specific command is a drawing command. If the specific command is a drawing command (YES in S54), the process returns to S46. That is, the CPU 24 does not execute the drawing command. On the other hand, if the specific command is not a drawing command (NO in S54), the process proceeds to S56, and the CPU 24 executes a process according to the command. When S56 ends, the process returns to S46.

  In S <b> 58, the CPU 24 reads the value of the CSC 62 from the shared memory area 50. Then, the CPU 24 determines whether or not the value of OSC determined in S42 is equal to or greater than the value of CSC62. As described above, in S42, it is determined that the value of OSC = the value of CSC62. Therefore, in S58, since the value of OSC and the value of CSC62 are usually the same, it is determined that the value of OSC is equal to or greater than the value of CSC62 (YES in S58), and the process proceeds to S60. However, while the CPU 24 is executing the processes of S46 to S56, another CPU 26 may execute the process of S100 of FIG. 5 described later, and the value of the CSC 62 may be incremented. In this case, it is determined that the value of OSC is smaller than the value of CSC 62 (NO in S58), and S60 and S62 are skipped and the process proceeds to S64.

  In S <b> 60, the CPU 24 writes the setting data in the cache memory 28 to the shared memory area 50. For example, when the setting data corresponding to the character size “20Pt” is stored in the shared memory area 50 and the setting data corresponding to the character size “30Pt” is stored in the cache memory 28, in S60 The CPU 24 stores the setting data corresponding to the character size “30 Pt” in the shared memory area 50 instead of the setting data corresponding to the character size “20 Pt”. As a result, in the shared memory area 50, setting data up to the processing target page of the setting command processing of FIG. 4 (that is, the page indicated by the value of the CSC 62) is stored.

  Next, in S62, the CPU 24 adds “1” to the OSC value to calculate a new value of the CSC 62 (eg, “2”). Then, the CPU 24 writes the new CSC 62 value in the shared memory area 50. When S62 ends, in S64, the CPU 24 changes the value of the SPF 64 in the shared memory area 50 from “1” to “0”. As a result, the setting command processing ends, and the process returns to S14 of FIG.

  In S14 of FIG. 3, the processing page number “M” is equal to the value of the CSC 62 (NO in S14), that is, setting data up to one page before the page indicated by the processing page number “M” (that is, the M−1th page). When it is determined that the setting data up to (the setting data) has been generated (NO in S14), in S20, the CPU 24 executes both command processes.

(Both command processing; Fig. 5)
In both command processing, the CPU 24 acquires the setting data by reading the setting data from the shared memory area 50 in S80. Thereby, the CPU 24 can acquire setting data up to one page before the page indicated by the processing page number “M” (that is, setting data up to the (M−1) -th page). For example, when the processing page number is “2”, the CPU 24 can acquire the setting data (that is, the character size “20 Pt”) up to the PDL data of the first page in FIG. The CPU 24 acquires setting data from the shared memory area 50 to the (M−1) th page and writes the setting data to the cache memory 28. As a result, the CPU 24 can execute both command processes (particularly, processes in S84 to S94) using the setting data up to the (M-1) th page in the cache memory 28. When the processing page number is “1”, the setting data has not been written in the shared memory area 50 yet. In this case, the CPU 24 skips S80.

  Next, in S <b> 82, the CPU 24 reads from the PDL data storage area 70 one page of PDL data indicated by the process page number “M” determined in S <b> 10 of FIG. 3. In the process of reading one page of PDL data, the CPU 24 executes the processes after S84 every time one command is read. The processing of S84 to S94 is substantially the same as the processing of S48 to S56 in FIG. However, as described above, in the setting command processing of FIG. 4, when the specific command is a drawing command (YES in S54 of FIG. 4), the CPU 24 does not execute the drawing command. On the other hand, in the both command processing, when the specific command is a drawing command (YES in S90 of FIG. 5), in S92, the CPU 24 executes the drawing command and generates intermediate code data. In this embodiment, the intermediate code data is vector format data.

  In S92, for example, when the PDL data received from the PC 6 is PDL data described in a specific type (for example, PS) language, the CPU 24 first determines the intermediate code from the specific type of PDL data. Using a program for generating data, the program code describing the drawing command is analyzed to interpret the contents of the drawing command (for example, the text “A”). Next, the CPU 24 generates intermediate code data corresponding to the interpreted contents in the cache memory 28 according to the setting data up to the (M−1) th page in the cache memory 28.

  For example, if the PDL data on the second page in FIG. 2 is both subject to command processing, the CPU 24 reads a drawing command (text “F”) included in the text data on the first line in S82. In S92, intermediate code data indicating the text “A” of the character size “20pt” is generated according to the setting data (character size “20pt”) up to the (M−1) th page in the cache memory 28. When S92 ends, the process returns to S82.

  If the specific command is a command indicating the end of the page in S84 (YES in S84), the CPU 24 reads the value of the CSC 62 from the shared memory area 50 in S96. Then, the CPU 24 determines whether or not the processing page number “M” determined in S10 of FIG. 3 is equal to or greater than the value of the CSC 62. As described above, in S14 of FIG. 3, it is determined that the processing page number “M” = the value of CSC 62 (NO in S14). Therefore, in S96 of FIG. 5, since the processing page number “M” and the value of the CSC 62 are usually the same, it is determined that the processing page number “M” is equal to or greater than the value of the CSC 62 (YES in S96), and S98. Proceed to The process of S98 is the same as the process of S60 of FIG. Next, in S100, the CPU 24 adds “1” to the processing page number “M” to calculate a new value of CSC 62 (eg, “3”), and proceeds to S102.

  However, while the CPU 24 is executing the processes of S82 to S94, another CPU 26 may execute the process of S62 of FIG. 4 and the value of the CSC 62 may be incremented. In this case, it is determined that the processing page number is smaller than the value of CSC 62 (NO in S96), S98 to S100 are skipped, and the process proceeds to S102. In S <b> 102, the CPU 24 determines the data name (for example, “P2”) of the intermediate code data for one page generated in the cache memory 28, and registers the determined data name in the intermediate code data table 54. The CPU 24 registers the determined data name one below the data name already registered in the intermediate code data table 54. If the data name is not registered in the intermediate code data table 54, the CPU 24 registers the determined data name at the uppermost position of the intermediate code data table 54. Next, in S104, the CPU 24 stores the generated intermediate code data for one page in the intermediate code data storage area 72, and ends both command processing. In this case, the process proceeds to S22 of FIG.

  In S22 of FIG. 3, the CPU 24 reads the value of the BPF 66 (bitmap generation processing flag (see FIG. 1)) from the shared memory area 50, and determines whether or not the value of the BPF 66 is “1”. If the value of BPF 66 is “1” (YES in S22), the process proceeds to S27. If the value of BPF 66 is “0” (NO in S22), the process proceeds to S23. In S23, the CPU 24 changes the value of the BPF 66 in the shared memory area 50 from “0” to “1”. Next, the process proceeds to S24 bitmap generation processing (hereinafter referred to as “BMP processing”).

(BMP processing; FIG. 6)
In the BMP process, the CPU 24 uses a program for generating bitmap data from the intermediate code data, and uses multiple gradations (one gradation page) from the intermediate code data for one page in the vector format generated by the command process in S20. For example, bitmap data for one page (256 gradations) is generated.

  First, in S112, the CPU 24 reads intermediate code data specified by the data name registered at the uppermost position of the intermediate code data table 54 from the intermediate code data storage area 72 into the cache memory 28, thereby Get code data. Next, in S <b> 114, the CPU 24 stores the band end count value WE in the cache memory 28. The band end count value WE may be specified when intermediate code data is generated in both command processes. Next, in S 116, the CPU 24 sets the value “0” of the band count value W in the cache memory 28.

  Next, in S118, the CPU 24 selects, from the intermediate code data corresponding to the band count value W, data representing the image represented by the intermediate code data corresponding to the band count value W in the bitmap format (hereinafter referred to as “partial bitmap data”). "). The partial bitmap data is stored in the cache memory 28. Next, in S120, the CPU 24 determines whether or not intermediate code data that is not used in the processing of S118 remains in the intermediate code data acquired in S112. Specifically, the CPU 24 determines whether or not the band count value W is less than the band end count value WE. If the band count value W is less than the band end count value WE, the CPU 24 determines that intermediate code data that is not used for the processing of S118 remains (YES in S120), and proceeds to S122. In S122, the CPU 24 adds “1” to the band count value W, calculates a new band count value W, and returns to S118.

  On the other hand, if the band count value W is equal to the band end count value WE, the CPU 24 determines that there is no intermediate code data that is not used for the processing of S118 (NO in S120), and proceeds to S124. In S124, the CPU 24 executes printing of bitmap data for one page (one sheet of printing paper (one)) formed by a plurality of partial bitmap data generated by repeating the processing of S118 to S122. To the unit 16. Specifically, the CPU 24 reads bitmap data from the cache memory 28 and writes it in the BMP data storage area 74. The print execution unit 16 uses the bitmap data stored in the BMP data storage area 74 to print the image represented by the bitmap data on a printing paper. The CPU 24 deletes the data name of the intermediate code data acquired in S112 from the intermediate code data table 54. As a result, the BMP process ends, and the process returns to S25 of FIG.

  In S <b> 25, the CPU 24 determines whether or not intermediate code data to be used for BMP processing is stored in the intermediate code data storage area 72. When the data name is registered in the intermediate code data table 54, the CPU 24 determines that the intermediate code data to be used for the BMP process is stored in the intermediate code data storage area 72 (YES in S25). , Return to S112. On the other hand, if the data name is not registered in the intermediate code data table 54, the CPU 24 determines that the intermediate code data to be used for the BMP processing is not stored in the intermediate code data storage area 72 (in S25). NO), the process proceeds to S26. In S26, the CPU 24 changes the value of the BPF 66 in the shared memory area 50 from “1” to “0”.

  Next, in S <b> 27, the CPU 24 determines whether there is data that has not been subjected to the process of S <b> 20 among the data included in the PDL data received from the PC 6. If YES here, the process returns to S10, and if NO, the process proceeds to S28.

  In S <b> 28, the CPU 24 determines whether or not the value of the BPF 66 in the shared memory area 50 is “1”. If the value of BPF 66 is “0” (NO in S28), the PDL process is terminated. In S28, when the value of the BPF 66 is “0”, the intermediate code data that the CPU 24 should use in the BMP processing is not stored in the intermediate code data storage area 72, and the CPU 24 uses both in the command processing. This is a case where the PDL data to be stored is not stored in the PDL data storage area 70 and the other CPU 26 is not executing the BMP process. In this case, the CPU 24 ends the PDL process.

  On the other hand, when the value of BPF 66 is “1”, the process proceeds to S30. In S30, the CPU 24 executes BMP auxiliary processing. Specifically, in S30, the CPU 24 changes the assistable flag (not shown) in the cache memory 28 from “0” to “1”. When the assistable flag is changed from “0” to “1”, the other CPU 26 that is executing the BMP process has completed the process of S118 in the intermediate code data acquired in S112 of FIG. The intermediate code data that does not exist is divided into two.

  Specifically, first, the CPU 26 subtracts the current band count value W (for example, 200) from the band end count value WE (for example, 2000) (for example, WE−W = 1800). Next, the CPU 26 divides the value of (WE−W) by 2, and calculates the number of processing bands (for example, (WE−W) ÷ 2 = 900) to be processed by the CPUs 24 and 26. Then, the CPU 26 adds a processing band number (for example, 900) to the current band count value W (for example, 200) to calculate a new band end count value WE ′ (1100). Next, the CPU 26 adds “1” to the new band end count value WE ′ to calculate a band count value W ′ (for example, 1101) that the CPU 24 should use in the BMP auxiliary processing. Further, the CPU 26 determines the original band end count value WE (for example, 2000) as the band end count value that the CPU 24 should use in the BMP auxiliary processing.

  When the band count value W ′ (for example, 1101) and the band end count value WE (for example, 2000) that the CPU 24 should use in the BMP auxiliary process are determined, the CPU 24 uses the cache memory 28 to assist the BMP. Execute the process. In the BMP auxiliary process, the CPU 24 first sets “0” as an auxiliary process end flag (not shown) in the cache memory 28, and executes the processes of S118 to S122 of FIG. If NO in S120, that is, if the band count value W ′ and the band end count value WE are equal, the auxiliary process end flag in the cache memory 28 is changed from “0” to “1”.

  The CPU 26 executes the BMP process in parallel with the BMP auxiliary process of the CPU 24. At this time, if NO in S120, if the auxiliary process end flag is set in the cache memory 28, the CPU 26 waits until the auxiliary process end flag is changed to “1”. When the auxiliary processing end flag in the cache memory 28 is changed to “1”, the CPU 26 proceeds to S124. If the auxiliary process end flag is not set in the cache memory 28, the CPU 26 does not wait and proceeds to S124.

  As described above, in the present embodiment, the CPUs 24 and 26 execute the PDL process of FIG. As described above, when the CPUs 24 and 26 execute processing using only the cache memory 28, the processing speeds of the CPUs 24 and 26 are higher than when processing is executed using the memory 30. As a result, the CPUs 24 and 26 can finish the PDL process relatively quickly.

(Processes executed by CPU in parallel)
With reference to FIG. 7, a description will be given of how the CPUs 24 and 26 execute PDL processing in parallel using PDL data for seven pages. In FIG. 7, the time has passed as it progressed downward. (P1), (P2), etc. mean page numbers. For example, “(P1) setting command processing” means executing setting command processing (S18 in FIG. 3) using the PDL data of the first page, and “(P1) both command processing” This means that both command processes (S20 in FIG. 3) are executed using the PDL data of the first page. Further, for example, “(P1) BMP processing” means that the BMP processing (S24 in FIG. 3) is executed using the intermediate code data of the first page.

  In FIG. 7, which process uses data generated by which process is indicated by a dashed arrow. For example, the CPU 24 executes (P1) both command processing, and then executes (P1) BMP processing using the intermediate code data generated by (P1) both command processing. Further, the CPU 24 executes (P2) BMP processing by using the intermediate code data generated by the (P2) both command processing of the CPU 26.

  First, the CPU 24 determines “1” as the processing page number “M1” of the CPU 24 in S10 of FIG. In this case, since M1 = 1 and the value of the CSC 62 = 1 (initial value), the CPU 24 determines NO in S14 of FIG. Therefore, the CPU 24 uses the cache memory 28 to execute (P1) both command processing.

  While the CPU 24 is executing (P1) both command processing, the CPU 26 determines “2” as the processing page number “M2” of the CPU 26 in S10 of FIG. In this configuration, the CPU 26 executes both command processing by using the PDL data having the smallest number of pages among the PDL data for one page that has not yet been used to generate the intermediate code data by both command processing. In this case, since M2 = 2 and the value of the CSC 62 = 1, the CPU 26 determines YES in S14 of FIG. Then, the CPU 26 executes (P1) setting command processing using the cache memory 28 using the PDL data of the first page which is the minimum page for which the setting command has not yet been executed. The (P1) setting command processing of the CPU 26 is completed in a shorter time than the (P1) both command processing of the CPU 24 because the drawing command is not executed. Therefore, the CPU 26 stores the setting data up to the PDL data of the first page from the cache memory 28 to the shared memory area 50 in S60 of FIG. 4 of (P1) setting command processing.

  Further, the CPU 26 increments the value of the CSC 62 from “1” to “2” in S62 of FIG. 4 of (P1) setting command processing. Therefore, when (P1) the setting command processing is completed, since M2 = 2 and the value of the CSC 62 = 2, the CPU 26 determines NO in S14 of FIG. 3, and uses the cache memory 28 to (P2) Both command processing is executed. According to this configuration, the CPU 26 can use the setting data up to the first page generated by the CPU 26 itself when executing both command processing using the PDL data of the second page (S80 in FIG. 5). ). Further, according to this configuration, when the CPU 24 has not generated the setting data for the first page, the CPU 26 (P2) performs both command processing until the setting data for the first page is generated by the CPU 24. There is no need to wait for execution.

  In this case, the CPU 26 stores the setting data up to the PDL data of the second page in the shared memory area 50 in (P2) both command processing (S98 in FIG. 5). Then, the CPU 26 increments the value of the CSC 62 from “2” to “3” in S100 of FIG. 5 (P2) both command processing.

  When the CPU 24 finishes the (P1) both command processing, the CPU 26 is executing the (P2) both command processing, and the BPF is “0” (NO in S22 of FIG. 3). In this case, the CPU 24 executes (P1) BMP processing using the cache memory 28 following (P1) both command processing.

  At the stage when the CPU 26 has finished the (P2) both command processing, the CPU 24 is executing (P1) BMP processing (YES in S22 of FIG. 3). For this reason, the CPU 26 does not execute (P2) BMP processing. The CPU 26 determines “3” as the processing page number “M2” of the CPU 26 in S10 of FIG. At this stage, setting data up to (P2) is stored in the shared memory area 50, and the value of the CSC 62 is “3”. Accordingly, the CPU 26 determines NO in S14 of FIG. 3, and executes the (P3) both command processing following the (P2) both command processing without executing the BMP processing. According to this configuration, the CPU 26 can avoid a situation in which the BMP process is executed simultaneously with the CPU 24 while the CPU 24 is executing the BMP process. Further, while the CPU 24 executes the BMP process, the CPU 26 executes both the command processes, so that the intermediate code data can be efficiently generated from the PDL data. As a result, the bitmap data can be efficiently generated from the PDL data through the intermediate code data. The CPU 26 stores the setting data of the PDL data for the third page generated in the (P3) both command processing in the shared memory area 50 (S98 in FIG. 5).

  At the stage when the CPU 24 finishes (P1) BMP processing, the CPU 26 executes (P3) both command processing. In the intermediate code data table 54, “P2” is registered by the (P2) both command processing of the CPU 26 (YES in S102 of FIG. 5 and S25 of FIG. 3). Therefore, the CPU 24 executes (P2) BMP processing without executing both command processing following (P1) BMP processing. According to this configuration, the CPU 24 can generate bitmap data relatively early using the generated intermediate code data. As a result, the CPU 24 can supply the bitmap data to the print execution unit 16 at an early stage. For this reason, the user can acquire a printing result at an early stage.

  Similarly, following (P2) BMP processing, the CPU 24 executes (P3) BMP processing without executing both command processing. The CPU 26 executes (P4) both command processing following (P3) both command processing.

  At the stage when the CPU 24 finishes the (P3) BMP process, the CPU 26 executes both (P4) command processes. At this stage, intermediate code data to be used in the BMP process is not stored in the intermediate code data storage area 72. Therefore, the CPU 24 determines NO in S25 of FIG. In S26 of FIG. 3, the CPU 24 changes the BPF from “1” to “0”, ends the BMP process, and returns to S10 of FIG. Since the value of the CSC 62 = “4” and the processing page number “M1” = “5” of the CPU 24, the CPU 24 determines YES in S14 of FIG. 3, and executes (P4) setting command processing. .

  In (P4) both command processing, the CPU 26 determines that the processing page number “M2” of the CPU 26 is “4” and the value of the CSC 62 is “4”, so that YES is determined in S96 of FIG. Therefore, the CPU 26 stores the setting data up to the PDL data of the fourth page from the cache memory 28 to the shared memory area 50 (S98 in FIG. 5). Further, the CPU 26 increments the value of the CSC 62 and starts (P4) BMP processing.

  The CPU 26 increments the value of the CSC 62 while the CPU 24 executes (P4) setting command processing. Therefore, the CPU 24 ends the setting command processing (P4) without storing the setting data up to the PDL data of the fourth page from the cache memory 28 to the shared memory area 50. Next, the CPU 24 executes (P5) both command processing. At this time, the CPU 24 reads the setting data up to the fourth page of PDL data generated by the CPU 26 from the shared memory area 50 and writes it into the cache memory 28. The CPU 24 executes both command processing (P5) using the setting data in the cache memory 28. In the modification, the CPU 24 may execute (P5) both command processing by using the setting data generated in the cache memory 28 by (P4) setting command processing.

  In this configuration, the CPU 24 should start both command processing using the fifth page of PDL data, and the CPU 26 completes both command processing using the first to fourth page PDL data. In this case, the CPU 24 uses the setting data for the first to fourth pages generated by the CPU 26 to execute both-command processing for the fifth page. According to this configuration, when the CPU 24 executes both command generation processing using the PDL data of the fifth page, the setting command processing using each of the PDL data from the first page to the fourth page is performed. You don't have to do it. However, depending on the processing timing of the CPUs 24 and 26, the CPU 24 may generate setting data for the fourth page.

  Thereafter, similarly to the above, the CPU 24 executes (P5) BMP processing, (P6) setting command processing, and (P7) both command processing. On the other hand, after the end of (P4) BMP processing, the CPU 26 executes (P5) setting command processing, (P6) both command processing, and (P6) BMP processing.

  At the timing when the CPU 24 ends the (P7) both command processing, the CPU 26 executes (P6) BMP processing. At this stage, both command processes have been completed for all the 7 pages of PDL data (NO in S27 of FIG. 3). The BPF is “1” (YES in S28 of FIG. 3). As a result, the CPU 24 executes (P6) BMP auxiliary processing (S30 in FIG. 3, S118 to S122 in FIG. 6).

  When the CPU 26 finishes the (P6) BMP process, the intermediate code data generated by the (P7) both command process by the CPU 24 is stored in the intermediate code data storage area 72. For this reason, the CPU 26 determines YES in S25 of FIG. 3, and executes (P7) BMP processing following (P6) BMP processing. On the other hand, when (P6) BMP auxiliary processing is completed, the CPU 24 determines YES in S28 of FIG. 3 in order for the CPU 26 to execute (P7) BMP processing (that is, BPF = 1), and (P7) BMP auxiliary processing. Execute. In this configuration, the CPU 24 executes a process for generating bitmap data together with the CPU 26 using the intermediate code data used in the BMP process executed by the CPU 26. According to this configuration, the CPU 26 completes the (P6) BMP process and the (P7) BMP process earlier than the case where the CPU 26 executes the (P6) BMP process and the (P7) BMP process alone. be able to.

(Effect of this embodiment)
The memory capacity used while each CPU 24, 26 is executing the BMP process is larger than the memory capacity used while each CPU 24, 26 is executing the setting command process. More likely than the amount of memory used during execution. As described above, the capacity of the cache memory 28 is relatively small. If the CPUs 24 and 26 use different intermediate code data at the same time and execute the BMP process individually, the capacity of the memory used while the BMP process is executed is determined as the cache capacity. The memory capacity of the memory 28 may be exceeded. In this situation, the BMP process is executed using the memory area of the memory 30. As described above, when the CPUs 24 and 26 execute processing using only the cache memory 28, the processing of the CPUs 24 and 26 is performed as compared with the case where processing is executed using the cache memory 28 and the memory 30. The speed is high. For this reason, in the above-mentioned specific situation, there is a high possibility that the BMP process will be delayed.

  In this embodiment, when one CPU (for example, CPU 24) is executing the BMP process, the other CPU (for example, CPU 26) executes either the setting command process or the both command process. For this reason, when one of the CPUs 24 and 26 executes the BMP process using the intermediate code data of the Mth page, the other of the CPUs 24 and 26 has the M page. BMP processing is not executed using intermediate code data other than the intermediate code data of the eye. According to this configuration, it is possible to reduce the memory capacity used when the bitmap data is generated from the PDL data by the CPUs 24 and 26. Therefore, in a configuration in which both the CPU 24 and the CPU 26 execute processing using the cache memory 28, the memory 30 is used exceeding the capacity of the cache memory 28 during the processing of the CPU 24 and CPU 26. Can be avoided.

(Correspondence)
The printer 10 of this embodiment is an example of a “control device”, and the CPU 24 and the CPU 26 are examples of a “first processor” and a “second processor”, respectively. Both command processing is an example of “intermediate code generation processing”, and BMP processing is an example of “bitmap generation processing”. The case of YES in S22 of FIG. 3 is an example of “first case”, and the case of NO is an example of “second case”.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The modifications of the above embodiment are listed below.

(Modification 1) In the above embodiment, there are two CPUs, but the number of CPUs is not limited. That is, the printer 10 may include three or more (that is, a plurality) CPUs.

(Modification 2) In each of the above embodiments, the “control device” is the printer 10, but may be a FAX device that executes printing of FAX data, or a multi-function device having a printing function. Also good.

(Modification 3) In each of the above embodiments, the printer 10 includes a plurality of CPUs 24 and 26, and each of the CPUs 24 and 26 executes the PDL processing of FIG. 3 in parallel. Instead of this, the PC 6 may include a plurality of processors, and each processor may execute the PDL processing of FIG. 3 in parallel. In this case, each processor may supply bitmap data to the printer 10 when executing the process of S24 of FIG. In this modification, each PC 6 is an example of a “control device”. In other words, the “control device” may not include the print execution unit 16. Generally speaking, the “control device” may be a control device for printing. Any device that generates bitmap data using PDL data may be used.

(Modification 4) In the above embodiment, one page of intermediate code data is generated from one page of PDL data, and one bit map data (that is, printing paper 1) is generated from one page of intermediate code data. Single-sided bitmap data) is generated. However, one piece of bitmap data may be generated from intermediate code data for a plurality of pages. For example, when the user selects a print setting so that an image represented by PDL data for a plurality of pages is printed on a single sheet of printing paper, the CPUs 24 and 26 determine from the intermediate code data for a plurality of pages, One piece of bitmap data may be generated. In the present modification, before starting the BMP process of S24 in FIG. 3, the CPUs 24 and 26 store intermediate code data for a plurality of pages for which generation of bitmap data by the BMP generation process has not yet been completed. It may be determined whether it is stored in the storage area 72. When the intermediate code data for a plurality of pages or more is stored in the intermediate code data storage area 72, the CPUs 24 and 26 proceed to S24, and only the intermediate code data for less than a plurality of pages is stored in the intermediate code data storage area 72. If not, the process may proceed to S27.

(Modification 5) In the above embodiment, the CPUs 24 and 26 execute a setting command process. However, the CPUs 24 and 26 do not have to execute the setting command process. For example, in FIG. 7, the CPU 26 may be on standby while the CPU 24 executes (P1) both command processing. When the CPU 24 stores the setting data for the first page in the common memory area, the CPU 26 may start both command processing (P2).

(Modification 6) In the above embodiment, the CPUs 24 and 26 execute BMP auxiliary processing. However, the CPUs 24 and 26 do not have to execute the BMP auxiliary process. For example, in FIG. 7, the CPU 24 may end the PDL process when both command processes are ended (P7).

  The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

2: communication system, 10: printer, 16: print execution unit, 20: control unit, 24, 26: CPU, 28: cache memory, 50: shared memory region, 70: PDL data storage region, 72: intermediate code data storage Area, 74: BMP data storage area

Claims (9)

A control device for printing,
A first processor and a second processor;
Each of the first processor and the second processor is:
Intermediate code generation processing for generating intermediate code data for one page using the PDL data for one page of the PDL data for the plurality of pages;
A bitmap generation process for generating bitmap data using the generated intermediate code data;
And using the PDL data for the plurality of pages until the bitmap data for the plurality of pages is generated,
Each of the first processor and the second processor is:
In the first case where another processor different from the processor is executing the bitmap generation process, generation of the intermediate code data is still completed by the intermediate code generation process among the PDL data for the plurality of pages. The intermediate code generation process is executed using the PDL data for one page that has not been executed,
In the second case where the other processor is not executing the bitmap generation process, the generation of the bitmap data by the bitmap generation process among the generated intermediate code data is not yet completed. A control device that executes the bitmap generation process using the intermediate code data. A memory for storing the intermediate code data generated by the intermediate code generation processing of each of the first processor and the second processor;
Each of the first processor and the second processor is:
When the processor finishes the bitmap generation process, the intermediate code data in the second case and the generation of the bitmap data by the bitmap generation process is not yet completed. The control device according to claim 1, wherein the bitmap generation process is executed using the intermediate code data stored in the memory when stored in the memory. Each of the first processor and the second processor is:
When the processor finishes the intermediate code generation process, in the first case, generation of the intermediate code data among the PDL data for the plurality of pages is still completed by the intermediate code generation process. The control device according to claim 1, wherein the intermediate code generation process is executed using the PDL data for one page that is not present. Each of the first processor and the second processor in the intermediate code generation process,
Executing a setting command included in the PDL data of the target page to be processed among the PDL data of the plurality of pages to generate setting data of the target page;
Using the setting data up to the target page generated as a result of executing the setting command included in the PDL data up to the target page and the PDL data of the target page, the intermediate data Generate code data,
Each of the first processor and the second processor is:
The other processor starts the intermediate code generation process using the PDL data of N (N is an integer of 1 or more) of the PDL data of the plurality of pages, and When the intermediate code data to be used in the bitmap generation process is not generated,
Executing the setting command included in the PDL data of the N page to execute setting data generation processing for generating the setting data of the N page;
The intermediate code generation process is executed using the setting data up to the Nth page that has already been generated and the PDL data on the (N + 1) th page among the PDL data of the plurality of pages. 4. The control device according to any one of items 1 to 3. Each of the first processor and the second processor in the intermediate code generation process,
Executing a setting command included in the PDL data of the target page to be processed among the PDL data of the plurality of pages to generate setting data of the target page;
Using the setting data up to the target page generated as a result of executing the setting command included in the PDL data up to the target page and the PDL data of the target page, the intermediate data Generate code data,
Each of the first processor and the second processor is:
The intermediate code generation process should be started using the PDL data of the M (M is an integer of 2 or more) page, and the other processor is L (L is 1 or more and less than M) Integer) when the intermediate code generation process using the PDL data of the page has been completed,
5. The control apparatus according to claim 1, wherein the intermediate code generation process of the M page is executed using the setting data of the L page generated by the other processor. 6. . In the first case, and when the intermediate code generation processing has been completed for all of the PDL data for the plurality of pages,
Each of the first processor and the second processor is:
6. The bitmap processing is executed together with the other processor using the intermediate code data used in the bitmap generation processing executed by the other processor. The control device according to one item. Each of the first processor and the second processor is:
Executing the intermediate code generation process using the PDL data having the smallest number of pages among the PDL data for one page not yet used for generating the intermediate code data by the intermediate code generation process; The control device according to any one of claims 1 to 6.   The control device according to any one of claims 1 to 7, further comprising a print execution unit that prints an image represented by the generated bitmap data on a print medium. A computer program for a control device for printing,
The control device includes a first processor and a second processor,
The computer program is stored in each of the first processor and the second processor.
Intermediate code generation processing for generating intermediate code data for one page using the PDL data for one page of the PDL data for the plurality of pages;
A bitmap generation process for generating bitmap data using the generated intermediate code data;
Using the PDL data for the plurality of pages until the bitmap data for the plurality of pages is generated,
The computer program is stored in each of the first processor and the second processor.
In the first case where another processor different from the processor is executing the bitmap generation process, generation of the intermediate code data is still completed by the intermediate code generation process among the PDL data for the plurality of pages. The intermediate code generation process is executed using the PDL data for one page that has not been performed,
In the second case where the other processor is not executing the bitmap generation process, the generation of the bitmap data by the bitmap generation process among the generated intermediate code data is not yet completed. A computer program for executing the bitmap generation processing using the intermediate code data.

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