JPS59172078A - List vector control system - Google Patents

Abstract

PURPOSE:To realize high-speed list vector access by using data, which is read out from the optional one of plural vector register, as the address data of another vector register. CONSTITUTION:The data in the vector registers 7 and 8 are read out successively in accordance with the addresses indicated by address registers 16 and 17 and are led to read data registers 10 and 11 and are led to a main storage device or a vector operating circuit through an OR circuit. The data read out from the vector register 7 is set to the address register 17 for the vector register 8 to access the vector register 8. Consequently, data is read out from the vector register 8 in accordance with the list data stored in the vector register 7.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Object of the Invention The present invention relates to a control method for vector data, and in particular to a control method for vector data having a list structure. The increment method performs high-speed reading and writing, but in normal vector operations, the data cannot be arranged in an orderly manner, so even if the interleap method is used, the reading/writing
There were no factors that limited the throughput in write operations.

However, when reading/writing vector data with a list structure using the same system configuration, depending on the list structure,
Since the order of reading/writing vector data is random, there is a problem in that the effect of the interleaving method cannot be fully utilized due to bank collision.

(e) Purpose of the Invention An object of the present invention is to read vector data from a main memory at high speed in an interleaved manner and store the vector data stored in a plurality of vector registers in an arbitrary vector register for use as list vector data. It is an object of the present invention to provide a method for avoiding throughput limitations due to bank collisions in a main memory device, as in the prior art, by using list data currently stored as address data for other vector registers.

(d) Main points of the present invention The present invention realizes high-speed list vector access by using data read from any vector register among a plurality of vector registers as address data of other vector registers. This is what I did.

(e) Embodiments of the Invention FIG. 1 conceptually shows the parts related to the present invention of a vector processor system that performs vector operations, in which 1 is a main memory composed of a plurality of banks. ,2
It is assumed that the data read out from the main memory device 1 in an interleaving manner is stored, organized, and sent to a desired vector register. 4 to 6 are write data registers to the respective vector registers, 7 to 9 are vector registers, 10 to 12 are read data registers from the vector registers, and 13 to 15 are OR circuits, which can be devised as necessary. It is assumed that an input gate (not shown) is opened. Address registers 16 to 18 are incremented by 1 at a predetermined timing in order to access the respective vector registers and update the addresses.

First, vector data is read out from the main memory 1 in an interleaved manner by a load instruction, stored and sorted by an aligner 2, and then sent to each vector register 7-9 via an OR circuit 3 and write data registers 4-6. The data is accumulated sequentially for each address indicated by registers 16-18.

When the accumulated vector data is processed by a vector operation instruction such as vector addition, the data in the vector register 8 and the data in the vector register 9 are sequentially read out according to the addresses indicated by the address registers 17 and 18, respectively. Datarenster 11.12
It is led to the vector'OXx circuit (not shown) through the OR circuit 14 and 15, where it is subjected to vector calculation, and the result is passed through the OR circuit 3, the write data register 4, and is sequentially stored in the vector register 7 according to the address indicated by the address data register 6. will be accumulated. Thereafter, the stored data is stored in the main memory device 1 via the read data register 10 and the OR circuit 13 according to a store instruction, and a series of vector calculation processing is completed. The above is an outline of the basic operation of the vector processor system.If the vector data mentioned above is list vector data, when vector data is read out from the main memory 1 in an interleaved manner by a load command, each bank of the main memory It is necessary to read out data according to an order of 11 lists that is different from the order of data stored in the memory, and depending on the order of the list, a problem arises in which the effect of the interleaving method cannot be fully utilized due to bank collisions.

The present invention is a system devised to solve this problem, and one embodiment thereof is shown in FIG.

Here, write data registers 4 and 5, vector registers 7.8, read data registers 10 and 11, and address registers 16 and 17 are the same as those in FIG. It is located in a place where it is configured to access vector register 8 by setting it in address register 17 of vector register (8 in this case).
Since data can be read from the vector register 8 in accordance with the list data stored in the vector register 7, list vector operations can be easily realized. Operation of load instruction (loading to vector register 8)
is exactly the same as before, so there is no problem due to bank collision. Further, the vector data processing after reading the list vector data is the same as the procedure explained in FIG. 1, and there is no problem.

In this embodiment, the output of the read data register 10 is input to the address register 17 of the vector register 8, but it goes without saying that the output of the vector register 7 itself may be directly input to the address register 17. .

FIG. 3 shows a specific example of the contents of vector registers 7 and 8 in FIG. 2. Vector register 7 contains the original vector data, and vector register 8 contains original vector data.

Now, read from vector register 7 and store data 5.
, 8, 4, 2, 4, 4.4... as the address data of other vector registers 8, the vector data becomes DH, Ds, D4, Dt + according to the contents.
are read in the order of D4, D4, D<...,
This means that list vector access has been achieved.

According to the present invention, in a vector processor system, list data is stored in any vector register among the plurality of vector registers that the system originally has, and the read data is used as address data for other vector registers. By configuring the system, operations on list-structured vector data can be easily and quickly processed.

An example of this system configuration is shown in FIG.

Here, 7 to 9, 10 to 12. 16 to 18 are the same as those in Figure 1, 20 to 22 are OR circuits, and 8 to 7.
．． 9-7 and the like are input gate circuits of the OR circuit, and 8-7, for example, indicates that the output of the vector register 8 is input to the address register of the vector register 7 at a predetermined timing.

Considering the case where the vector operation instruction of this system specifies vector register 9 as the vector register for list data and vector register 7 as the vector register for vector data, in implementing the present invention, first , the register 9 is read and the data must be input to the address register 16 of the vector register 7, so the input gate circuit 9- of the OR circuit 20 is
7 is opened, the operation described in FIG. 2 is performed and the list vector data is read. It is clear that the list vector calculation can be performed using the procedure explained in FIG. 1 below.

(f) As described in detail of the present invention, according to the present invention, list data is stored in any vector register among a plurality of vector registers, and the readout output is inputted to the address register of other vector registers. By constructing a system such that list vector data reading 7 can be performed using a similar procedure to reading original vector data, it is possible to construct a list vector processor system with a similar configuration to the conventional one. be.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the concept of a vector processor system, FIG. 2 is a diagram explaining an embodiment of the present invention, and FIG. 3 is a diagram specifically explaining the contents of a vector register related to the present invention. FIG. 4 is a diagram showing the main part of the system configuration in which the present invention is implemented. In the figure, 1 is the main memory, 7 to 9 are vector registers, and 16 to 18 are address registers.

Claims (1)

[Claims] In a vector gross sensor system having multiple vector registers, list data is stored in any vector register, and the read data is connected to the address register input of other vector registers to control the vector registers. List vector control method 1 is characterized by the following.