JPS6364474A - Picture memory controller - Google Patents

Abstract

PURPOSE:To attain the development of high speed dot data overlappingly even in a case of a system using a CPU having no margin in its address space by setting the assignment of a memory area to each bank of a picture memory split to the area at every bank overlappingly. CONSTITUTION:Banks whose areas are overlapped, that is, odd number banks 4b, 4d, 4f are provided in the picture memory 4 of the titled controller in addition of even number banks 4a, 4c, 4e, 4g only. Thus, when an address is developed after (C80000)H in each bank except a bank 64g in a picture data, the banks are switched when the development by one line is finished, the developing address is revised according to equation (A)H-(28000)H=(B)H, (in equation, A is a bank N and B is a bank (N+1)), even if a character or the like exists at the boundary between banks, the picture data is developed in the same bank without having consiousness to the boundary.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image output system such as an image display system or a laser printer, and particularly relates to an image output system such as an image display system or a laser printer, and particularly to an image display system in which image data to be displayed or recorded is recorded as binary data for each pixel. The present invention relates to an image memory control device equipped with a memory.

[Conventional technology]

Generally, the capacity of an image memory varies depending on the contents of the system, but it ranges from about 128 bytes for a CRT display to several megabytes for laser printer printing. However, the memory space of a commonly used 16-bit CPU is from 1 Mbyte to more than ten bytes, and the capacity of this image memory cannot be ignored in terms of the CPU's memory configuration. In particular, in a controller that has an image memory buffer for a laser printer using a CPU with an address space of 1 Mbyte, as shown in the CPU address map shown in Fig. 6, the controller has a program memory, text data memory, and character generator ( CG), etc., and the address space that can be secured for the image memory is limited.

A method generally called a bank switching method is available as a means for allowing a CPU to access a memory having a capacity that does not fit in the CPU's address space. This method divides the memory into a plurality of areas, selects one of the areas, and controls the memory so that it can be accessed by the CPU.

Related devices of this type include, for example, the Japanese Patent Laid-Open No. 5
There is a description in Publication No. 7-150070.

[Problem that the invention seeks to solve]

With the above conventional technology, a CPU with insufficient address space
Even in the case of devices using image memory, it has become possible to configure the image memory using bank switching methods, etc., but no consideration has been given to dot data development, which is unique to image memory, and the access area of the divided image memory (bank ), so if there are characters or figures on the boundary, it becomes necessary to select multiple areas and access memory when expanding dot data, which is a factor that inhibits high-speed dot expansion. It had become.

An object of the present invention is to provide an image memory control device that solves the conventional problems and can realize high-speed dot data expansion even in the case of a system using a CPU with limited address space.

[Means for solving problems]

The above object is achieved by overlapping allocation of memory areas for each bank of the image memory, which is divided into areas for each bank.

[Effect]

Each divided area overlaps with the other, so if there are characters or figures on the boundary between areas, you can expand the dot data by selecting and accessing another area that includes the boundary. Therefore, the expansion processing to the image memory becomes faster.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

2 and 3 are configuration diagrams of a controller for a laser printer (hereinafter referred to as LP) to which an embodiment of the present invention is applied.

The LP controller 21 is connected to a host device 22, and the host device 22 transfers programs and printing text data to the controller 21. The LP controller 21 is connected to the LP 23 and sends video data and control signals for printing to the LP 23.

The controller 21 includes a CPU for controlling, a program memory 2 for storing programs and data, a character generator (CG) 3 for storing character patterns for printing, an image memory 4 for printing, and a read-only image memory 4. Circuit unit 5, L P i / F unit 6 which serially converts the parallel data of the image memory 4 from the read-only circuit 5 and outputs it to the LP 23 as a video output. , CPU
a memory control circuit unit 7 for controlling one bank in the image memory 4 divided into banks;
Host 1-j/F8 that sends and receives data to and from the host device 22
It's decorated.

FIG. 4 is a block diagram of the memory control circuit section 7. As shown in FIG.

The memory control circuit 7 controls the CPU based on the information sent via the address bus 11 and the control bus 12.
The UI performs processing to write bank data to the bank data latch 13. One of the banks of the image memory 4 divided according to the bank data value is selected. Furthermore, since the addresses applied to the same storage element are different between even and odd banks, the bank even/odd determining section 14 makes a determination and the memory address generating section 15 outputs the address. 16 indicates a data bus.

FIG. 1 shows the CPUI address space of image memory 4 associated by memory bank control circuit 7. FIG. The image memory 4 is divided into banks 4a to 4g, but the banks overlap each other as shown in the figure. Therefore, when image data is expanded and stored, for example, if it is expanded to Atres (D 1000) + (in bank 0),
Expanding to address (A 9000) l (in bank 1 is the same expansion operation. Also, in the image data expansion program built in program memory 2, expansion is performed while keeping in mind the address and bank as the expansion position coordinates. As a result, coordinate management is interrupted during the deployment process.

In the image memory with the above configuration, conventionally, only the even-numbered banks shown in Figure 1 were configured, that is, each bank was independent, and because the areas did not overlap, groups of image data such as characters were placed on the boundaries between banks. If it exists, for example as shown in FIG. 5, it will be necessary to access two banks in order to develop one character's worth of data read from the CG 3 into the image memory 4, and the bank switching operation will be necessary. It takes. On the other hand, as shown in Figure 5, "Ai...
C only for the dot data that should be expanded to bank 1.
If the image is read from G3 and developed in the image memory 4, searching for the character start address in CGa becomes complicated.

According to one embodiment of the invention, a conventional independent bank configuration, ie even banks 4a, 4c, 4e.

In addition to the configuration with only 4g, there is also a bank configuration with overlapping areas, that is, odd-numbered banks 4b and 4d.

4f is a further provision. Therefore, during image data expansion, each bank except Panchromatic 4g has an address (C8000).
)H or later, when the expansion for one line is completed, change the bank and change the expansion address according to the following formula, and then convert the bank(A))l (28000)
)I = (B).

Here, A: Bank N, B: Bank (N+1) Even if there are characters, figures, etc. at the boundaries between the banks.

Image data can be developed within the same bank without being aware of boundaries, and development speed can be improved.

〔Effect of the invention〕

According to the present invention, it is possible to speed up the expansion of dot data into the image memory.

[Brief explanation of the drawing]

Figure 1 is a bank configuration diagram of an image memory according to an embodiment of the present invention, Figure 2 is a system configuration diagram, Figure 3 is a circuit block diagram, and Figure 5 shows the operation of an embodiment of the present invention. FIG. 6 shows a memory map of the dot data developed in the image memory to be explained. 4... Image memory, 4a, 4c, 4e, 4g... Even bank, 4b, 4. d, 4f...odd bank, 7.
...Control circuit section.

Claims (1)

[Claims] 1. An image memory that stores image data to be displayed or recorded as binary data for each pixel in correspondence with each pixel forming a display surface or recording surface, and control of the image memory. the image memory into a plurality of areas (A)
An image memory control device that divides and controls an image, characterized in that a plurality of regions (B) are provided spanning a plurality of regions (A) including the boundaries of the divided regions (A). Memory controller. 2. In claim 1, two areas (A)
An image memory control device characterized in that the same number of regions (B) as the number of boundaries are provided.