JPS63231548A - Writing system for data - Google Patents

Abstract

PURPOSE:To obtain a cheap and highly speedy writing circuit by providing one latch means of one word length to hold the previously written data and a shifter means to input the number of bits for two words and output the number of the bits for one word. CONSTITUTION:When the data of one word are written to an address (n), only the part written in (n) is written into a memory 6 and the part written in n+1 is simultaneously held to a latch means 3. Next, when the data of one word over addresses n+1 and n+2 are written into the address n+1, the part written in the n+1 of the data and the part (this just comes to be the data of one word length when both are joined.) written in the address n+1 of the data before one time held at a previous latch are written into the address n+1 of the memory 6 and the part written in the address n+2 is held at the latch means 3 in the same way as the previous one. By repeating the action, the data over an address boundary can be written to a continuous address without increasing the redundant memory writing cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access method suitable for rewriting contents spanning address boundaries of a mesori of a combinator.

[Conventional technology]

To read and write memory in a combinator (hereinafter referred to as CPU), generally, the address of the memory to be read is given to the memory via an address bus, and then the CPU sends the address via a data bus.
This method involves writing the contents of registers within the CPU to memory, and reading the contents of memory to registers within the CPU. The data bus has a width specific to the CPU, typically 8, 16, 52
It is made up of bits, etc. Data having the number of bits equal to this data bus width is called a word, and memory access is performed in units of words or bytes (8 bits). Memory is also addressed in words or bytes, and memory reading and writing have traditionally been performed in addressed words or bytes. Therefore, in order to read and fold words or bytes across the boundaries of adjacent addresses, read and write the contents for each adjacent address, and combine the contents of the two addresses into words or bytes by bit processing. Required soft processing.

In order to eliminate the need for this software processing,
A technique disclosed in Japanese Patent No. 644 has been proposed.

FIG. 2 shows the conventional system described in the above publication.

11 is a CPU address bus, 2 is a data bus, 35 is a shifter circuit, and 6 is a memory. Control information indicating the shift amount of the shifter 35 and which memory 6 to write data into using the write control line 4 and gate 63 is written into the register 50 by the CPU. The characteristics of this method are
The data spanning two addresses 1, for example, RU and RU+1, is shifted to an appropriate bit position by the shifter 55, and the data is transferred to the register 30.
0 control information and gate 33 to the outside address and outside +1 address.
This should be written in parts. This will be explained with reference to FIG. B and C are the contents of the memory 6 at the current addresses 1 and 1+1. Assume that the data of A is inserted into this at the position shown in the figure. Write control information 1D is written in advance in the register 60, and information for shifting one write data A to the shifter 35 as A' is also stored therein. When writing to this first address, 5 bits of the first address are rewritten as shown in B'. Next, the compliment control information 1D is automatically transferred to D by a method not shown.
Since the data changes as shown in D', when the data is written to address 1+1, 5 bits of data is changed as shown in D'. In this way, the method disclosed in the above-mentioned publication reads data that spans the address boundary by performing two memory write cycles. However, this method always requires two memory write cycles to load one word.

A method for realizing this with only one memory write cycle is described in Japanese Patent Application Laid-Open No. 111169/1983.

FIG. 4 shows a circuit according to the same publication. In the same figure, 14 is a constant memory that always outputs address information "@1".
13 is an adder.

1 is added to the address bus of the address bus 11 of the CPU (not shown), and 1llI&-address information +1 is output to the address bus 15. Reference numeral 17 denotes a latch that holds address selection control information, and input to the latch 17 is performed by control@19. The output of latch 17 is input to multiplexer 16 via address selection control edge 20. For example, if the data latched in the latch 17 is 1. If the lower 5 bits are 0, the multiplexer 16 transfers the address bus 1 to the memory chip corresponding to the lower 5 bits of the data in the memory 6.
The address information of the address bus 11 is applied via the address bus 2, and the address information 1+1 of the address bus 15 is applied to the memory chip corresponding to the upper three bits. Therefore C
When 1 byte of data in a register in the PU is stored outside the memory address, the lower 5 bits are actually stored in the lower 5 bits outside the memory address.
The upper 3 bits are stored in the upper 5 bits of +1 outside the memory address. At this time, the upper 5 bits outside the memory address and the lower 5 bits of the address +1 are not affected and retain the values before the above processing. In other words, a group of bits between data buses spanning boundaries between adjacent memory addresses can be written in one memory write cycle.

[Problem that the invention seeks to solve]

The above conventional technology has the following problems. First, JP-A-55
The method disclosed in Publication No. 112644g requires two memory write cycles for convolution of one word. Therefore, the problem is that it takes at least twice as much processing time as the method disclosed in JP-A-58-111169. On the other hand, the method disclosed in Japanese Patent Application Laid-Open No. 58-111169 has no difference in writing time for data that straddles the address boundary or data that falls within the boundary, but it is necessary to provide a separate multiplexer 16 for each chip of the memory 6. There is. Fourth
In the figure, the data bus 2 is 8 bits, but in applications that require the loading of data across such address boundaries, such as bitmap memory systems in display devices, the data bus 2 is 8 bits in order to perform high-speed drawing processing. Bus 2 is often set to 16 bits or more. If we use a 256-bit dynamic memory (such as Hitachi GX 50256P) for memory 6, there will be 9 addresses for each address @12 to memory 6, and even if data bus 2 is 8 bits, the address @12 will be The total number is 72, or 144 in the case of 16 bits. Therefore, even if an attempt is made to make the multiplexer 16, adder 13, etc. into components using an LSI technique such as a gate array, the number of terminals in the package is too large, making it difficult to put them into practical use.

Further, even if this LSI implementation is possible, since the number of address lines 12 is large, the mounting technology is difficult to assemble. In other words, the method disclosed in Japanese Patent Application Laid-Open No. 58-111169 is superior in terms of write processing speed, but consideration must have been given to implementation.

The purpose of the present invention is to eliminate both problems. In other words, the categorization processing time can be made the same as in Japanese Patent Application Laid-open No. vifA5B-111169, and in terms of implementation, the address bus 11 for supplying to the memory 6 can be shared as in Japanese Patent Application Laid-Open No. 55-112644. The purpose of this paper is to propose a method for writing data across address boundaries.

[Means for solving problems]

The conventional method attempts to complete the processing of data that spans address boundaries in units of one word. However, in applications where data is read across address boundaries, for example image data is read into an arbitrary position in the bitmap memory of a display device, data is generally read into a continuous address area. Multiple words are digitized consecutively.

Taking advantage of this property that 'C' storage is performed continuously in consecutive address areas, input one word-long latch means to hold the previously written data and the number of bits equivalent to two words. The above object can be achieved by providing a shifter means for outputting the number of bits for one word.

[Effect]

When an attempt is made to write data of one word length across an address boundary, the one word of data can be divided into two parts: a part to be written to the address boundary and a part to be written to the address boundary +1. Then, 1 for the address audience.
When the data of the word is written, only the 1% portion is written to the memory, and the stone portion corresponding to rk+1 is held in the latch means at the same time. Next, when writing one word of data spanning addresses +1 and +2 to address +1, the part written to 1+1 of the data and the previous data held in the latch last time are written to address +1. The part that is written (this is exactly one word long data when both are combined) is written to address +1 of the memory, and the part written to address +2 is held in the latch means as before. By repeating.

Data spanning address boundaries can be written to consecutive addresses without increasing redundant memory write cycles.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. .

FIG. 1 shows an embodiment of the present invention. 6 is a memory element, 1
1 is a CPU address bus (not shown), 2 is a data bus (the path width is 6 bits), and 3 is an α-bit length latch for holding write data.

55 is the output 8 (α bit) of the ratte 5 and the data bus 2 (
α bit) as input (input H2a bit) shifter (
Shifter 350 output 9 is the α bit).

30 is a register that holds the shift amount of the shifter 35 (above the dot edge) and a register (a part below the dot edge) that holds information for controlling convolution in 1-bit units;
is a gate, and 4 is a memory 60 write control signal.

5 and 6 are examples of the relationship between the input and output of the shifter 350. Here, the width of the bus 20 will be explained as 8 bits. The input to the shifter 35 is a total of 16 bits, consisting of the data/(S bit 2 (8 bits) and the output 8 (8 bits) of the latch 3, and is inputted in the arrangement shown in FIG. 5. Here, the LS bit (
The lower bit) is aO.

The MSbit (most significant bit) is set to b7. As shown in the figure, the output 9 of the shifter 65 is 8 bits from CO to 07, with the LS bit being cO and the Msbit being C7.

FIG. 6 is a diagram showing the relationship between the shift amount applied to the shifter 35 via the control edge 51 and the output (CO~ay). In the same figure, the area surrounded by a diagonal edge indicates the signal of the latch 5, that is, the signal that is given to the memory 6 as data on the first page.

Next, the operation will be explained using FIGS. 7(, 4) and (B).

Figure (B) is an example in which the memory 6 is used as a graphic display memory (bitmap memory) of a display device.
I am thinking of adding a graphic button "B16" to this. The vertical axis α indicates the word (in this example, 8 bits) boundary of memory 6, and the address is 1 horizontally from the left.
It increases one by one.

When it reaches the right end (not shown), it moves down one column, and the addresses increase again from the left end to the right. Same figure (
, 60 in parentheses is a pattern memory that stores a pattern to be written into the memory 6, and in this example, there are 4 words (4 bytes) of data in the horizontal direction and 11 columns in the vertical direction. Pattern memory 60 may be part of memory 6 or may be another memory located at a location not shown in FIG. In the button memory 60 shown in FIG. 6A, it is assumed here that the addresses increase by 1 from the top to the bottom.

Further, the value of (i, j) indicates the location to be written to the memory 6.

In this example, the data in the button memory 60 is shifted to the right on the memory 6 by 3 bits as shown in FIG. 6B.

This corresponds to the case where the shift amount in FIG. 6 is 6 (white arrow).

Figure 8 shows register 3 for realizing the sorting in Figure 7.
It is an explanatory diagram of setting of 0. Of the registers 50, the value "3' is set in the register 501 for setting the shift amount of the shifter 35, as described above.

The data in Figure 7 (, f) is shown in Figure 7 (B) from the top to 711.
Number = 1 = 1 to 4, then 1 = 2 = 1
Write them in order from 4 to 4. Honor can be divided into three virtues. The first area is ■. Here, the storage mask 60 of the register 30 in FIG.
After setting the value of ■ to 2, transfer the data. Then (i
The data of *j)=(',') is shifted as indicated by the white arrow in FIG. 6, and the five bits on the right are written by the gate 53 in FIG. Also, at the same time as it is written to memory 6, (1, 1) of Fig. 7 (, 4) is also written to Latte 3.
data is held (Fig. 1).

Next is the area (■) of the memory 6. Here, the convolution mask 302' of the register 6o in FIG. 8 is set as shown in (■). This is the same situation as when there is no convolution mask circuit. Now, if you transfer the data (1, 2) in Figure 7 (, (),
The remaining 3 bits from 1.1) and the 3 bits transferred this time (1.2)
) are injected into the memory 6. At the same time, the data (1, 2) is held in the latch 5. Hereinafter, writing to the area (■) is performed simply by transferring data. During this time, there is no need to perform any work such as setting h of registers.Data transfer is performed using the CPU's continuous transfer command or D
This can be done at high speed using MA transfer or the like. The last area is ■. Here, the write mask 502N in FIG. 8 is set as shown in (■). Then, only the part surrounded by g+Iwao in FIG. 6, that is, the data held in Latte 3 last time, is selected. Therefore, the remaining 5 bits are written into the memory 6 by simply performing dummy writing. Below i
The button can be transferred to the memory 6 using a method similar to =2, 5, . . . . In this way, according to the present invention, data writing that spans address boundaries can be achieved using the same processing procedure and same processing speed as normal data transfer that does not span address boundaries, except for the beginning and end, that is, the parts marked ■ and ■. It is. Here, in Figure 7, the area marked ■ is 5
Although it is explained as a word, in actual applications it is often 50 words or more. That is, since the areas ``■'' and ``■'' each have one word, most of the time required for writing data is occupied by the area ``■''. In this embodiment, a write mask circuit centered around the gate 33 is provided, but even if this mask circuit is omitted, the processing time will hardly change when data is written in a large area. On the other hand, when transferring a large number of small area data as shown in FIG. 7, this mask circuit reduces the processing time. This is an effect unique to this embodiment.

FIG. 9 shows a second embodiment of the invention. The difference from the first embodiment shown in FIG. 1 is that a second latch 57 which inputs the read data bus 36 from the memory 6 is provided instead of the data bus 2 of the CPU, and its output is sent to the latch 3 and shifter 35. This is the point where the input data bus 2' is set as the input data bus 2'. When an external control means (not shown) (herein collectively referred to as CPU) specifies an address on the address bus 11 and reads out the memory 6, the result is held in the second latch 37. Then c
When the PU specifies an address on the address bus 11 and writes into the memory 6, the data of the second latte 37 and the latte 3 are written to the memory 6 through the shifter 35. At the same time that data is written to the memory 6, the contents of the second latch 37 are held in the latch 3. This is the circuit operation of FIG. 9 shown in the second embodiment. FIG. 10 is an explanatory diagram showing an application of the second embodiment. Here, memory 6 is used as a bitmap memory, and the button data in area 61 is stored in area 65.
Consider transferring to a location across the word boundary α of the memory 6 such as .

Such applications are very common in multi-window processing for display devices.

Since the operation of the circuit is basically the same as that of the first embodiment, a data flow specific to the second embodiment will be shown. It is assumed that the first data in the area 61 has already been held in the latch 3 as indicated by a dotted line 62 in the previous process. When the CPU reads the next word in the area 61, the read data is held in the second ratte 57 as shown by a solid line 63. Next, C
When PU writes to area 650 next position, second latte 3
The data No. 7 flows as shown by a solid line 64, and is shifted to an appropriate position by the No. 7 lid 35 together with the data held in the latch 3 and written into the area 65. At the same time as this writing, the contents of the latch 3 are replaced with the contents of the second latch 57 in preparation for the next data transfer. Now the second latch 3
The operation is the same as that described in the first embodiment except that the data passes through 7.

Display devices often have a plurality of bitmap memories (memories 6 in this case) in order to perform multi-color display or multi-gradation display. For example, as shown in Figure 11, memory 6 is
When used in combination, it is possible to express two colors or gradations per pixel. The circuit 38 of the second embodiment is as shown in the same figure! If the memory sets and memories 6 are provided in correspondence with each other, the processing shown in FIG. 10 can be performed in the same processing time regardless of the number of memory sets (60). This is because if the second latch 37 were not provided, the CPU would have to transfer the area once for each set of memories 6, so the processing time could be kept constant regardless of the number of 60 sets of memories. This is an effect unique to this embodiment.

In the above explanation, one word has been assumed to be 8 bits, but how many bits (for example, 16 bits or 32 bits) is this?
I don't mind. Moreover, the operation of the shifter may be shifted in the opposite direction or in both directions. These do not change the essence of the present invention.

〔Effect of the invention〕

According to the present invention, the write processing time is
It is possible to achieve the same level as that of Publication No. 169 (if the number of data to be written is taken as a shoulder), the method of this publication is
The method of Publication No. 644 has 2 chickens, and the method of the present invention has 2 chickens.
One write cycle to memory 6 is required. In normal use, the address bus 11 to the memory 6 can be shared as in JP-A-55-1i2644, and the number of inputs to the shifter 35 can be doubled compared to the circuit in the same publication. This can be realized by increasing the number of data latches 5. Since the main part of the present invention has a configuration suitable for LSI implementation, it is economically possible to create a high-speed write circuit at low cost.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a first embodiment of the present invention, FIG. 2 and FIG.
The figure is a diagram for explaining the conventional example, Figure 3 is a diagram for explaining writing of data across address boundaries, and Figures 5, 6, 7, and 8 are diagrams for explaining the first embodiment. , FIG. 9 is a diagram showing a second embodiment of the present invention, and FIGS. 10 and 11 are explanatory diagrams of the second embodiment. 5...Latch 35...Shifter 6...Memory 11...Axis...Address bus 2...・・・－・・・・・・Data bus 4・・・・・・・・・・・・・・・Write control signal Agent Patent attorney Masaru Ogawa 2 Unillustrated 3 Verbal abuse 4 times Figure 5 Figure L

Claims (1)

[Claims] A memory system having a data input of 1, n (n is a natural number) bits, comprising at least n bits of latch means;
Shifter means having 2n bits as input and n bits as output is provided, the latch means is connected to an n-bit data bus that provides data to be written into the memory system, and the input of the shifter means is connected to the latch means. An output of the shifter means is connected to a data input of the memory system, and the latch means stores information on the data bus when writing to the memory system is performed one time. A data writing method characterized by data retention. 2. The memory system has a second latch means connected to its data output, and the output of the second latch means is the data input. Data writing method.