JPS62214475A - Control system for mask register - Google Patents

Abstract

PURPOSE:To use each bank efficiently by writing and reading mask data on and from addresses, which are obtained by shifting at every m-th stage, of N numbers of banks constituting a mask register in m-element units. CONSTITUTION:Mask data DA0-DA3 set to registers 440-443 element in each one element are set to write buffer registers 440'-443' in the next cycle and are set to bank write registers BI0-BI3 in every two cycle together with following elements set to register 440-443. These mask data are written on pertinent addresses of respective banks 4a-4d of the mask register by an output ADRB0 of an address register B1 constituting a shift register and its shift outputs ADRB1-ADRB3. This operation is repeated to write data without generating idle areas in banks. The read operation is executed in the same operation procedures.

Description

[Detailed Description of the Invention] (Table of Contents) Overview Industrial Application Fields Prior Art and Problems to be Solved by the Invention Means for Solving the Problems Actions Examples Effects of the Invention [Summary] For example, 8 banks Mask register (MR) consisting of
is accessed from a specific port of multiple ports by writing at a specific timing of a timing signal that divides one cycle into 8 cycles.

For example, by specifying the read timing and synchronizing the address given at that time with the above eight timing signals,
In the mask register (MR) access method, each element of the mask data input from the port is divided into two elements. By providing a means for writing and reading data every two cycles, the eight banks of mask registers (MR) are constructed into, for example, four banks.

[Industrial application field]

The present invention relates to a control method for reading and writing data to and from a mask register (MR) in a pipelined vector computer system.

Normally, in a pipelined vector computer system, one element data is associated with, for example, one bit of mask data, and operations on the element data are controlled by turning on or off the mask data. , a so-called mask operation is performed.

Therefore, the mask register (M
Since R) requires high speed, for example, an emitter-coupled logic circuit (hereinafter referred to as ECL) element is often used.

A memory chip using such an ECL element is configured to be a random access memory (RAM) for high-speed logical operations, so for example, 8 bits/16 bits x
In many cases, it has a structure of 256 words, and if it is used as a mask register (MR) which basically has a 1-bit structure, it is difficult to generate a vacant area due to the module structure.

On the other hand, recent computer systems are required to be more and more miniaturized with the progress of highly integrated technology, so a decline in implementation efficiency cannot be tolerated. There is a growing demand for a mask register (MR) control method that can efficiently use chips.

[Prior art and problems to be solved by the invention] FIG. 3 is a diagram schematically showing a general vector calculation method.

First, vector data is read from vector register (VR) 1 to calculation registers 2a and 2b for one element, and after being calculated in calculation pipeline (ALU) 3,
It is stored in vector register (VR) 1 again.

At this time, mask data is read out for 1 bit from the mask register (MR) 4 in synchronization with the read timing of the vector data from the vector register (VR) 1, and the mask data corresponds to 1'. For the element, the above vector fJ'JX is performed, and for the element whose mask data corresponds to °O゛,
The above-mentioned vector operation operates to be suppressed, and a so-called mask operation is executed.

FIG. 4 is a diagram showing an outline of the control method for the mask register (MR), and FIG. 5 is a diagram showing the outline of the control method for the mask register (MR).
MR) is a diagram showing an example of the configuration.

Usually, the mask register control section (MRC) 41 is provided with a main timing generator (MTG) 41a.
For example, in the case of 8 banks/8 time slot control method,
One period is, for example, K, F3. F2. El, L, F3. F2. Eight main timing signals, repeated in the order of Fl, are generated and used for timing control for the mask register (MR) 4. .

Input/output port (S) for mask register (MR) 4
AO~5A3) 45a~45d, (SBO-5B3
) There are a plurality of 46a to 46d (in this example, 4 as shown), and the mask register (MR) from each port
The write/read start timing for 4 (hereinafter referred to as -9 or R start timing) is defined.

For example, one start timing from the port (SAO) 45a is determined to be the E3 timing, and the W timing from the port (SAI) 43b is determined to be the E1 timing.

In synchronization with E3 timing, one of the main timings, the instruction unit (
II) When the address (ADH) for mask register (MR) 4 is sent from 5, the address register (BO to B7) consisting of 8 shift registers is sent.
42 register BO is set as ^DRBO,
Thereafter, the signals are sequentially shifted in synchronization with the main timing.

At this time, the main timing (K, E3.E2.El, L,
F3. 5ELA, which is one of the bank select control signals (SIELAO~3) generated in synchronization with F2°Fl)
O is energized and the port (SAO) 43a to bank 0
(BANKO) The write route for 4a is
When gated at 3 timings, mask data D^0(
For example, mask data from the main memory (MS) is
Register (DIO) 440 to the port) (SAO)
45a, and the corresponding address (8DRI) of the bank 0 (BANKO) 4a through the input register (BIO).
IO).

Each stage (BO-87) of the address register 42 functions as an address register for each bank ([1ANKO to 7). Therefore, as the address (ADRBO) is sequentially shifted to the shift register BO=OB1=6B2=O・・・・・−=OB7, the mask data from the port (SAO) 43a is transferred to the bank 1 ( BANKI) 4b
=O bank 2 (BANK2) 4c...---→Bank? (BANK7) The data is sequentially written to the same address of 4h via the respective input registers (BII to Ill7).

Thereafter, in the same way, the mask data (DAI) from the port (SAI) 43b is transmitted as described above, for example,
At the timing of El, the address register (BO~
B? ) It functions so that the data is sequentially written to the addresses set in 42.

Such control is herein referred to as the 8-slot control force type, as described above.

When the mask register (MR) 4 is composed of 8 banks as in this example, 8 banks/8 slots control is performed.

In the configuration example shown in FIG. 5, one element of mask data is 2 bits + 2 parities = 4 bits, but each bank of the mask register (MR) 4 is composed of, for example, a memory module (chip) of 8 bits x 256 words. ) is used.

Therefore, in the above write control, each bank (BA
NKO-BANK7) Only 4 bits of the 8-bit width from 4a to 4h are used.

Similar control is performed for read operations as well. That is, at a predetermined specific timing (for example, E2
timing) and address registers (BO to B7) 4
By setting the read address (ADH) for BO 2, the acid address is shifted sequentially from then on, and the addresses are sequentially shifted from bank 0 (BANKO) 4a to bank 1 (BANKI
) From 4b, -, the mask data of the corresponding address is sequentially read out to the bank read registers (800 to BO7).

At this time, the read port (SII
O~4) One of the 46a"d (SBO) 46a is selected, and the mask data is stored in the register (0~4) every cycle.
00), and the main memory (MS
) or sent to the arithmetic circuit as mask data DBO.

In this way, in the conventional method, for example, 2 bits +
Even in the case of simultaneous writing of 2 parity (1 element), since 8-bit wide random access memory (RAM) is used as mask register (MR) 4, each module of random access memory (RAM) There is a problem in that a vacant area is created in the chiffle, and as a result, the number of memory chips (LSI) mounted on one mask register (MR) printed board increases, resulting in uneconomical results.

In view of the above conventional drawbacks, the present invention aims to provide a method for effectively utilizing LSI chips used for mask registers (Ml?) that require high-speed access and reducing the number of modules (chips). That is.

[Means for solving problems]

FIG. 1 is a principle block diagram of the mask register control method of the present invention.

In the present invention, for example, in the control method for the mask register (MR) 4 in which the address register (80 to B?) 42 for controlling 8 slots constitutes a shift register, for example, one element is 4 bits. A 4-bit wide write buffer register (0
10'~) 440'~ and exit, l-to (SBO~)
46a, a read register (Doo”~
) 470'~ are provided, and the bank select control signals (SELAO~, 5BLBO~) during the above 8 slot control are provided.
Without changing the timing, for example, every two cycles when 8-bit width mask data consisting of two elements is prepared, the above-mentioned data is added to each bank (BANKO~) 4a~ that constitutes the mask register (MR) 4. It is configured to control writing and reading of 8 bits at the same time.

[Effect]

That is, according to the present invention, for example, when a mask register (MR) consisting of 8 banks is accessed from a specific port of a plurality of ports, the timing is determined by dividing one period into 8 cycles. Write and read timings are defined at specific timings of signals, and the addresses given at that time are synchronized with the eight timing signals mentioned above, and the eight addresses obtained by shifting, for example, eight steps, are used to write the eight banks. In the mask register (1'lR) access method in which the same address of each bank is sequentially accessed, each element of the mask data inputted from the above port is written and read every two cycles as a set of two elements. By providing the mask register (MR), the 8 banks of mask registers (MR) described above are configured, for example, in 4 banks.
This has the effect of reducing the number of LSI memory chips constituting the.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention, and the write buffer registers (010' to
DI3') 440' to 443', and read registers (000' to 003') 470' to 473',
and related mechanisms are the functional blocks necessary to implement the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

Even if the present invention is implemented, the mask register control unit (MRC)
Main timing at 41 (K, E3.E2.El,
L, F3°F2. PI), and bank select control signals (SELAO to 3.5ELBO) corresponding to each port.
~3) generation operation, and address register (BO~B7)
) The shift operation and the like at 42 will not be changed and will therefore be omitted, and the description will focus on the fortune-telling and readout operations for mask register (MR) 4 here.

In this embodiment, first, each port (SAO~3) 4
The mask data (DAO-3) for 5a-45d is:
In the same manner as before, registers (DIO to 3) 440 to 4 are provided for each element filling port.
43, and write bus registers (DIO' to DI3'') 440' to 443 in the next cycle.
At the same time, the mask data of the next element is sent to registers (D!0-3) 440-443.

In synchronization with this set timing, the address registers (BO to B7) 42 that constitute the shift register are also
A write address corresponding to each port is set.

And write register (DIO~3) 440~4
43 and write baffle registers (DIO' to DI
3') The contents of 440' to 443° are simultaneously activated by the bank select control signal (SHLAO to 3),
After being set in the bank access registers (810 to 3) every two cycles, the address register Bl 42 is
output (ADR[lO) and its shift output (ADRB
I~3), the data is written to the corresponding address of each bank (13ANKQ~3) 4a~4d of the mask register (MR) 4.

The above fortune-telling operation can be performed on a specific port, for example, port (
Focusing on SAO) 45a, the first element (4 bits) of the mask data input from DAO is set in the register (DIO) 440, and in the next cycle it is moved to the buffer register (010') 440° and stored in the buffer. When ringing, mask data (4 bits) for the next element is set in register (DIO) 440.

By activating the bank select control signal (SELAO) at this point (i.e., E3 timing),
The contents of the register (DIO) 440 and the buffer register (010') 440° are read out at the same time.
Bank 0 (BANKO) Input register for 4a (
The contents (8 bits) of the input register (BIO) are written into the area specified by the write address (ADRBO) set in the address register B142.

In the same way, the third. When the mask data of the fourth element is in the registers 440'' and 440,
When the bank select control signal (SELAO) is activated, the output of the port (SAO) 45a becomes bank 1 (B
ANKI) 4b and address register (B3
) is written to the same address as bank O ([1ANKO) 4a according to the instruction of address (ADHBI) which is the output of bank O ([1ANKO) 4a.

By repeating the above operation every two cycles, each bank of mask register (MR) 4 (BANK1 to BANK3)
Write operations are performed on the four banks at the same timing as in the past without creating free areas in 4a to 4d.

This kind of movement is each port) (SA1~3) 45b~
45d as well, the write start timings are determined respectively (for example, El, F3. Fl, respectively).
It will be held in

The read operation is also performed in exactly the same operating procedure. To summarize the read operation, each mask data read into the bank read registers (I100-3) is transferred to the registers (D00-3) by the bank select control signal (SULBO-3) generated in the same manner as before.
3) 470 to 473 and registers (000' to 3'
) 470' to 473° every two cycles, and the gate signal (GO, G1) causes the register (
D00-3) 470-473 and register (D00'
~3') The contents of 470 "~473" are output alternately every cycle.

In this way, writing and reading are performed using the same 8-slot control as in the prior art.

In this way, the present invention allows elements input from each port with a width of l bits to a mask register (hR) composed of N banks of K bits wide, for example.
m elements, i.e. It-m bits (however, f-m≦
An input buffering mechanism (4
40”~) and the exit cover sofa ring mechanism (470’~
), and the address is shifted by m-N stages, and N addresses for each m stage are extracted and applied to each bank of the mask register composed of the N banks, and the address is shifted in units of m elements. The mask register (MR) is characterized in that it appears to have an upper mN bank configuration by controlling writing and reading with the MR.

It goes without saying that the main timing mentioned above is not limited to eight time slots.

〔Effect of the invention〕

As described above in detail, the mask register control method of the present invention requires one period to access the mask register (CMR) consisting of 8 banks from a specific port of a plurality of ports, for example. The write and read timings are defined at specific timings of timing signals divided into eight cycles, and the address given at that time is synchronized with the eight timing signals and shifted by eight steps, for example. 8 addresses above
In the mask register (MR) access method, which sequentially accesses the same address in each bank, each element of the mask data input from the above port is written into and read out as a set of two elements every two cycles. By providing the means, the 8-bank mask register (MR) is configured into, for example, 4 banks, so that the L forming the mask register (MR)
This has the effect of reducing the number of SI memory knobs.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of the mask register control method of the present invention. FIG. 2 is a block diagram showing an embodiment of the present invention. FIG. 3 is a diagram schematically showing a general vector calculation method. FIG. 4 is a diagram schematically showing a control method for the mask register (MR). FIG. 5 is a diagram showing an example of the configuration of a conventional mask register (MR). It is. In the drawing, 1 is a vector register (VR). 2a and 2b are operation registers. 3 is the arithmetic vibe line (ALU). 4 is a mask register (MR). 4a to 4h are banks (BANKO~?). 41 is a mask register control unit (MRC). 41a is a main timing generator (MTG). 42 is an address register (BO to B7). 440-443 are registers (010-013). 440' to 443' are (write) buffer registers (DIo' to 013'). 45a to 45d are input ports (SAO to 3). 46a to 46d are output ports (SBO to 3). 470 to 473 are registers (DoO to 003). 470' ~ 473° Hareshista (000' ~ 003
'). DAO-DA3 is mask data. 5ELAO~3.5ELBO~3 are bank select control signals. 80RBO~7 is the address. are shown respectively. ＼−２、／′General 2 doctor
3 mouths of grass

Claims (1)

[Claims] In a vector calculator equipped with a mask operation function, the mask register (4) used for the mask operation is
Consisting of N banks (4a~) with K bit width and accessed from multiple ports (45a~45d), 1
The start point of writing or reading from a specific port (45a~) is defined at a specific timing of a timing signal whose period is divided into M cycles, and the access address given at that time is sequentially synchronized with the above timing signal. In the access control method for the mask register (4) in which the address (42) obtained by shifting is given as the address for the N banks (4a~) and each bank of the mask register (4) is accessed, The mask data elements input sequentially from ports (45a~) with l bit width are divided into m elements (however, m
is an integer of 2 or more, and an input buffering mechanism (440'~) and an output buffering mechanism (470'~) are provided to store l・m≦K as one set, and the above address is stored in m・N stages. Shifting, extracting N addresses for each m stage and applying them to each bank of the mask register (4) composed of the N banks, and controlling writing and reading in units of the m elements. A control method for a mask register, characterized in that the mask register (4) has an apparently m/N bank configuration.