JPH02162438A - Memory circuit - Google Patents

Abstract

PURPOSE:To increase the data processing speed by carrying out simultaneously the different operations to the same addresses of plural memory planes. CONSTITUTION:A memory circuit contains three memory planes MP1-MP3, a latch circuit 11, three selector circuits 13a-13c, and a control circuit 15. The circuits 13a-13c are set opposite to the planes MP1-MP3 respectively and receive the write data from a data bus 7 and the circuit 11 to select one of these two types of data. When the write data is selected, the planes MP2 and MP3 perform the reading and writing operations respectively. At the same time, the plane MP1 perform a writing action in response to the reading operation of the MP2. The commands of these operations are given to the circuit 15 from a CPU, etc. Thus it is possible to give accesses simultaneously to plural different memory planes and to increase the data processing speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a memory circuit including a plurality of memory planes that are accessed independently.

(Prior Art) Some memory circuits have a storage area divided into a plurality of blocks (hereinafter referred to as "memory planes"), and a series of information is stored in each memory plane.

An example of such a memory circuit is one constructed as shown in FIG. In the memory circuit shown in FIG. 2, storage area 1 has three memory planes MPI and MP2.
．． Divided into MP3.

In these memory planes, data input/output operations are performed between the data bus 7 and the address specified by the address given from the address bus 5 under the control of the control circuit 3. That is, the memory plane becomes accessible by an enable signal given from the control circuit 3, and an operation mode is designated by a read signal/write signal.

In this way, storage area 1 consisting of three memory planes
The access to the address specified by the address given from the address bus 5 is performed in the operation mode specified by the control circuit 3.

(Problem to be Solved by the Invention) Therefore, in the above-mentioned memory circuit, for example, the read operation for the memory plane 1 and the read operation for the memory plane 2 are difficult.
It was not possible to execute write operations for both at the same timing. That is, it was not possible to access multiple branes at the same time.

Therefore, when such a memory circuit is used as a page memory of a laser beam printer or the like, the contents of the printed memory plane must be erased. Therefore, a write operation for erasing is required. While this loading 03 operation is being performed, even other memory planes cannot be accessed. For this reason, the next execution of the save operation is made to wait until the preemption operation is completed, which takes time to print out.

In this way, the above-described memory circuit can only be accessed in a single operation mode, making it difficult to process data at high speed.

Therefore, this invention was made in view of the above, and its purpose is to enable simultaneous access to multiple different memory planes and contribute to speeding up data processing. The objective is to provide a memory circuit that can

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a plurality of memories that are allocated on the same address and have access data specified by a common address. a plane, a holding means for inputting and holding the first write data, and the memory for selecting and corresponding the first write data held in the holding means or the second tM write data given from the data bus. It is comprised of a selection means for applying to a plane, and a control means that independently controls an access operation to each of the memory planes and controls a selection operation of the selection means.

(Operation) In the above configuration, it is possible to write the first write data and the second write data to different memory planes at the same time.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing the configuration of a memory circuit according to one practical example of the present invention. The memory circuit of this example has 3
Tsume [Librane MP1. This allows MP2 and MP3 to be accessed independently.

In Figure 1, the memory circuit consists of three memory planes M
P1 to MP3, a latch circuit 11, three selector circuits 1.3a to 13C1, and a control circuit 15.

The latch circuit 11 captures and holds data transmitted through the data bus 7. The data retained is
It is applied to each of the selector circuits 13a to 13c.

The selector circuits 13a to 13c are provided corresponding to the respective memory planes MP1 to MP3, and are configured to receive input data from the data bus 7 and the latch circuit 11.
It receives write data given from the controller and selects one of the write data. Selector circuit 13
13c perform selection operations independently.

The write data selected by the selector circuits 13a to 13c are written to the corresponding memory planes MP1 to M.
Given to P3.

The memory planes MP1 to MP3 independently store and hold data, and their storage areas are allocated on the same address. That is, memory plane MPI
~MP3 are accessed in common by the same address.

When a write operation is instructed, data selected by the corresponding selector circuits 138 to 13c is written to the memory planes MPI to MP3. On the other hand, when a read operation is commanded, the written data is output to the output data bus common to each of the memory planes MP1 to MP3 and read out. The interrupt data and read data of each memory plane MPI to MP3 are specified by a common address given from the address bus 5.

The control circuit 15 controls the above-described latch circuit 11, selector circuits 138-130, and memory planes MP1-MP3 based on instructions from an external circuit such as a CPU. The control circuit 15 controls the latch operation of the wrap circuit 11. Further, the control circuit 15 instructs each of the selector circuits 138 to 13c to select data. Furthermore, the control circuit 15 independently specifies an operation mode for each of the memory planes MP1 to MP3, and gives an operation permission command.

As explained above, one embodiment of the present invention is constructed, and the operation of this embodiment will be explained next.

Here, as an example of the operation, the memory plane M l
) 1 and memory plane MP2, the data in memory plane MP1 is erased at the same time as the data in memory plane MP2 is read out, and data is written into memory plane MP3 during this time. do.

First, the erasing data (all 1101+ data) for erasing the data of memory plane M P 1 is
In response to a latch command from the control circuit 15, the data is latched from the data bus 7 to the latch circuit 11.

When the erase data is latched in the latch circuit 11, the control circuit 15 instructs the selector circuit 13C to select the data given from the latch circuit 11, and selects the write data given from the data bus 7. The control circuit 15 issues a command to the selector circuit 13a. As a result, the eraser data latched by the latch circuit 11 is selected by the selector circuit 13c, and the write data applied from the data bus 7 is selected by the selector circuit 13a.

When the occupied data is selected, the CPU or the like instructs the control circuit 15 to perform a read operation on the memory plane MP2, a write operation on the memory plane MP3, and a write operation on the memory plane MP1 along with the read operation of the memory plane MP2. Ru.

After this command, when an address is given to the address bus 5, operation permission is commanded from the control circuit 15 to the memory plane MP1 and the memory plane MP2. Furthermore, a write operation is commanded to memory plane MP1, and a read operation is commanded to memory plane MP2.

As a result, the erase data selected by the selector circuit 13c is sequentially written to the addresses given from the address bus 5. At the same time, memory plane M
Data is sequentially output to the output data bus 17 and read from the address given to the memory plane MP1 in P2. Such an operation is performed from the address bus 5 to the memory plane MP1. The address given to MP2 is +1
It is incremented and executed. On the other hand, during this operation, when the control circuit 15 instructs the memory plane MP3 to enable and occupy the operation, the selector circuit 13a selects the addresses sequentially given from the address bus 7.
The write-in data selected by and given from the data bus 7 is sequentially written.

Therefore, it is possible to erase data stored in memory plane MPI while reading data stored in memory plane MP2.

As a result, data is erased at the time when data is read, so there is no need for extra time to erase data. Therefore, memory circuits can be used efficiently,
It becomes possible to process data at high speed.

Such a memory circuit is suitable for use in a page memory of a laser beam printer or the like in which all data is cleared after reading it.

Note that the present invention is not limited to the above-described embodiment, and the input of the latch circuit 11 may be connected to a data bus other than the data bus 7, for example. In such a case, data provided from the two systems can be stored in different memory planes at the same time. This makes it possible for equipment that reads data with a scanner and prints it out to simultaneously read data from the scanner and develop the read data in CPIJ, etc., processing the data at high speed. You will be able to do this.

[Effects of the Invention] As explained above, according to the present invention, different operations are executed at the same time on the same address in multiple memory planes. As a result, it is possible to shorten the execution time and provide a memory circuit that contributes to the interconnection of data processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a memory circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional memory circuit. 5...Address bus 7...Data bus 11...Latch circuits 138-13c...Selector circuit 15.!・Control circuit MPI to MP3...Memory plane

Claims (1)

[Scope of Claims] A plurality of memory planes allocated to the same address and in which access data is specified by a common address; holding means for inputting and holding first write data; and holding means for holding first write data; selecting means for selecting the first write data provided by the user or second write data provided from the data bus and applying the selected data to the corresponding memory plane; 1. A memory circuit comprising: control means for controlling the selection operation of the selection means.