JPH02165385A - Image memory control system - Google Patents

Abstract

PURPOSE:To attain the rapid operation of image data by writing the contents specifying the bank of an image memory in a bank register included in a memory control part in accordance with operation to be executed by an operation part, controlling the reading operation of the image memory in accordance with the contents of the bank register and successively outputting image data necessary for operation to the operation part. CONSTITUTION:The contents specifying the bank of the image memory 1 are written in the bank register 4 in the memory control part 3 in accordance with the operation to be executed by the operation part 2, the reading operation of the image memory 1 is controlled in accordance with the contents of the register 4 and the image data necessary for the operation are successively outputted to the operation part 2. Even in the case of using the same image data plural times to operate the image data, the same bank can be specified plural times by the bank register 4 without increasing the capacity of the image memory 1 and the memory control part 3 requires only the address control of each bank unit. Consequently the rapid operation of image data can be attained.

Description

[Detailed Description of the Invention] [Summary] Regarding an image memory control method that controls reading of image data from an image memory storing image data related to multiple colors, the present invention relates to an image memory control method that uses the same image data multiple times to calculate image data. without increasing image memory loss even when
In addition, for the purpose of making it possible to perform calculations on image data at high speed, when the calculation unit performs arbitrary calculations on image data regarding multiple colors read from the image memory, the calculation unit In an image memory control method having a memory control unit that controls readout operations of the image memory based on calculations to be performed, the image memory includes banks of a number equal to the number of colors of image data, and the memory control unit controls the read operation of the image memory based on the calculation unit. A bank register is provided in which contents specifying a bank of the image memory are read in accordance with an operation performed in the image memory, and the readout operation of the image memory is controlled by the contents of the bank register to read image data necessary for the performance. is configured to output sequentially to the performance section.

[Industrial application field]

The present invention relates to an image memory control method, and more particularly to an image memory control method for controlling the reading of image data from an image memory storing image data regarding a plurality of colors.

In recent years, when performing predetermined processing on three primary color image data of red (R), green (G), and portrait (B), for example, the three primary color image data are stored in an image memory in order to perform operations corresponding to the predetermined processing. It is common practice to store the three primary color image data a predetermined number of times and read out the three primary color image data depending on the performance. The processed image data is displayed on, for example, a display device.

[Conventional technology]

FIG. 5 schematically shows an example of a conventional image memory control method. Here, as an example, red image data R for one frame is squared and multiplied by green image data G for one frame. The case where this is applied will be explained.

In the conventional system, the read address of the image memory is set equal to the display address on the display device (not shown). Therefore, for example, when one frame's worth of red image data R is read out from the image memory 1001, this one frame's worth of red image data R is displayed as is on the display device. However, when performing the calculation <R2・G as described above, red image data R for one frame is stored in different image memories 100+ and 1002, and green image data G for one frame is stored as an image. It is necessary to store it in the memory 1003. The memory control unit 101 includes the calculation unit 10
The read addresses of the image memories 1001 to 1003 are specified in accordance with the order of the calculations R2·G performed in step 2.

[Problem to be solved by the invention]

Conventionally, when the same image data is used multiple times to perform calculations on the image data, it is necessary to store the same image data in the image memory for the number of times the same image data is used, which increases the capacity of the image memory. Also, since the memory control unit must manage the addresses of each image memory, it is not possible to control the readout of the image memory at high speed, and as a result, the calculation unit cannot perform calculations at high speed. There was also the problem that it was not possible to do so.

The present invention provides an image processing system that can perform image data calculations at high speed without increasing the capacity of an image memory even when the same image data is used multiple times to perform image data calculations. The purpose is to provide a memory control method.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention. In the figure, 1 is an image memory, 2 is a performance section that performs arbitrary calculations on image data regarding multiple colors read from the image memory 1, and 3
Reference numeral 4 denotes a memory control unit that controls the read operation of the image memory 1 based on the calculation performed by the calculation unit 2, and 4 is a bank register provided in the memory control unit 3. Image memory 1
consists of a number of banks equal to the number of colors in the image data.

[Effect]

The bank register 4 of the memory control section 3 is written with contents that specify the bank of the image memory 1 according to the calculation performed by the calculation section 2, and the read operation of the image memory is controlled by the contents of the bank register 4. The image data necessary for the calculation is sequentially output to the calculation unit 2.

Therefore, even when the same image data is used multiple times to perform image data calculations, the capacity of the image memory does not increase by specifying the same bank multiple times using the bank register. Since only address management is required, high-speed calculation of image data is possible.

(Embodiment) Fig. 2 shows main parts of an embodiment of the present invention. In the figure, a memory control section includes an address counter 11, a memory 12 as a bank register, a controller 13, a counter 14, It consists of a flip-flop 15 and a driver 16.A memory action signal ACT from an arithmetic unit (not shown) is supplied to an address counter 11 which is also supplied with a clock signal CLK and a counter full signal FULL output from the counter 14. The address counter 11 is
The bank register address BRA is outputted and supplied to the memory 12 which is also supplied with the bank register data [3RDW and bank register data write signal WE from the arithmetic unit. The bank register data BRDR read from the memory 12 is sent to the flip 7 as preset data.
0 tube 15.

The image memory enable signal MEN from the calculation section is supplied to the controller 13, and the controller 13 outputs a preset signal PST and a count enable signal EN. The preset signal 5ps-r is supplied to the flip-flop 15, and the count enable signal @EN is supplied to the counter 14.

The flip-flop 15 and the counter 14 are supplied with a reset signal RESET, and the counter 14 is also supplied with a clock signal CLK. The bank number output from the flip 70 knob 15 and the in-bank address output from the counter 14 are supplied to an image memory (not shown) via a driver 16 as a memory address MA.

First, the operation of writing bank register data BRDW into the memory 12 will be explained. In this case, as shown in FIG. 3, the memory action signal ACT is at a low level, and the bank register data write signal WE alternately repeats high and low levels. The bank register address BRA is incremented by one from "0" to rnJ as shown in FIG.
0OOJ, roooj, roolJ, ro02J,...
Bank register data BRDW is written from address rOJ to address rnJ of bank register address BRA.

Next, the operation of writing bank register data BRDR from memory 12 will be explained. In this case, the memory action signal ACT becomes high level, and the bank register data write signal WE is fixed at high level. Initially, the bank register address t3RA is set to 10'', so the bank register data BRDR of <rooOJ is supplied to the flip knob 15 as shown in FIG. is preset.

FIG. 4 shows an example of the correspondence between bank register data in the bank register and addresses in the image memory. Here, bank register data "000" specifies the bank from image memory address rooo00J to rOFFFFJ, bank register data rooIJ specifies the bank from image memory address "10000" to rlFFFFJ, and the other bank register data are the same. It corresponds to banks consisting of image memory.

In FIG. 3, when the memory enable signal MEN rises,
The counter 14 outputs a memory address MA called rooooOJ. Therefore, the driver 16 supplies the image memory bank address "0" specified by the flip 70 knob 15 and the memory address "00000" specified by the counter 14 to the image memory.
Image data OJ is read out and output to the calculation section.

In FIG. 3, RAS and CΔS represent the row address strobe n number and column address strobe signal of the image memory.

Next, when the count enable signal EN from the controller 13 rises, the count value of the counter 14 is incremented and the memory address M
A is supplied to the driver 16. As a result, rD-1
Image data J is read from the image memory. Thereafter, the count value of the counter 14 is incremented in the same way, and when the count value reaches rOFFFFJ, the counter full signal FtJLL rises. As a result, the counter value of the address counter 11 is incremented, and the bank register address BRA becomes [1 ].Furthermore, since the preset signal PST also rises, the flip-flop 15 sets the bank address "1" of the image memory to the driver 16.
supply to Thereafter, operations similar to those described above are repeated during the high level period of the memory action signal ACT, so a description thereof will be omitted.

In FIG. 3, rooOJ and ro are stored in bank register addresses BRA of rob, rlJ, and l'2J.

Since bank register data BRDW called OJ and roolJ are occupied, for example, from the image memory bank address rOJ f7)l-00000J to IQFFFF
Red image data R is stored in the memory address MA of J, and from rl 0000] of bank address "1" to rl FF
If green image data G is stored in memory address MA named FFJ, the value of bank register address BRA becomes r.
With OJ, red image data is read out, with "1" the same red image data R is read out, and with "2", green image data G is read out. Therefore, the capacity of the image memory
For example, calculations such as R2.G can be performed without storing the same red image data R twice due to an increase in . Furthermore, the counter 14 allows the memory addresses in each bank of the image memory to be automatically generated, eliminating the need for complex memory address management.

Although the present invention has been described above using examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

According to the present invention, the content specifying the bank of the image memory is loaded into the bank register of the memory control unit in accordance with the calculation performed by the operator, and the read operation of the image memory is controlled by the content of this bank register. The image data necessary for calculation is output to the calculation unit in sequence, so even if the same image data is used multiple times to perform image data calculations, the capacity of the image memory can be increased by specifying the same bank multiple times using the bank register. Since the memory control section only needs to manage addresses on a bank-by-bank basis, high-speed calculation of image data is possible, which is extremely useful in practice.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block system diagram showing the main parts of an embodiment of the present invention, Fig. 3 is a timing chart for explaining the operation of the embodiment, and Fig. 4 is the inside of the bank register. FIG. 5 is a block diagram schematically showing an example of a conventional method. 3 is a memory control unit, 4 is a bank register, 11 is an address counter, 12 is a memory, 13 is a controller, 14 is a counter, 15 is a flip-flop, and 16 is a driver. Patent applicant: Fujitsu Ltd. In Figures 1 to 4, 1 is an image memory, 2 is a calculation unit,

Claims (1)

[Scope of Claims] When the arithmetic unit (2) performs an arbitrary operation on the image data regarding multiple colors read from the image memory (1), the image memory In an image memory control method having a memory control unit (3) that controls the readout operation of the image data, the image memory (1) includes banks of a number equal to the number of colors of the image data, and the memory control unit (3) controls the readout operation of the image data. A bank register (4) is provided in which contents specifying a bank of the image memory are written in accordance with the operation performed in the section (2), and the read operation of the image memory is controlled according to the contents of the bank register necessary for the operation. An image memory control method characterized by sequentially outputting image data to the arithmetic unit (2).