JPH05158791A - Two-port memory - Google Patents

Abstract

PURPOSE:To reduce the program load on random port side microprocessor at the time of dividing the memory cell of a 2-port memory into plural blocks. CONSTITUTION:After a storage in a shift register 33 from a serial port, an access to the memory cell indicated by a serial access cell selecting register 5 is made by an address indicated by a data transfer address preparing part 6. From a random port, the access to the memory cell indicated by a random access cell selecting register 3 is made by an input address from an outside. The contents of the serial access cell selecting register 5 and the random access cell selecting register 3 are managed by the microprocessor connected with the random port side. Thus, it is not necessary to manage the divided blocks by the address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-port memory for storing transfer data between two independent data processing devices.

[0002]

2. Description of the Related Art Conventionally, a 2-port memory for images has been widely used as a 2-port memory for storing transfer data between two independent data processing devices. A 2-port memory for images is described in the following document, for example. "Parallel figure processing", Takayuki Sagishima et al., Corona Publishing Co., Ltd., 1991, 8
Mon, pages 152-154.

The above-mentioned conventional two-port memory will be described below with reference to the drawings. FIG. 3 is a block diagram of a conventional 2-port memory. In FIG. 3, 31 is a memory cell having two data input / output ports, 32 is a random input / output port connected to one of the memory cell 31 that is randomly accessed, and 33 is the other of the memory cells 31. Shift register for inputting / outputting in parallel data lines connected to the ports of the
Is a serial input / output port for serially inputting / outputting data between the shift register 33 and the outside, 35 is an address input port for inputting an address for accessing the memory cell 31,
Reference numeral 36 denotes a random port access control unit for inputting an access request signal from the random input / output port side and controlling access to the memory cell 31, and 37 denotes a serial input / output port 34 and a shift register 33 in synchronization with a clock input from the outside. Is a serial port access control unit that controls data transfer between the memory cell 31 and the shift register 33 according to a data transfer request signal input from the outside.

The operation of the 2-port memory configured as described above will be described below. However, when the serial input / output port 34 is exclusively used for input, a read-only storage device that is sequentially accessed is connected, and the random input / output port 32 is exclusively used for output, an ordinary microprocessor is connected, and random reading is performed. Think

First, data input from the serial port side will be described. The serial port access controller 37 shifts the data sequentially input from the serial input / output port 34 in synchronization with the serial port control clock.
Store to. When the storage of the data string in the shift register 33 is completed, the data transfer request signal is input, the storage control signal is output to the memory cell 31 according to the address input from the address input port 35, and the content of the shift register 33 is stored. By repeating the above series of operations, the data from the memory device is sequentially stored in the memory cell 31. The storage address to the memory cell 31 and the data transfer request signal are output by the microprocessor connected to the random input / output port 32.

Next, the random port access controller 36
When the random access request signal is input, outputs the content of the memory cell 31 to the random input / output port 32 according to the address input from the address input port 35. The read address from the memory cell 31 is output by the microprocessor connected to the random input / output port 32.

By the above operation, the data sequentially read from the storage device connected to the serial input / output port 34 is stored in the memory cell 31, and the random input / output port 32 is provided.
The microprocessor connected to the CPU performs random read processing.

[0008]

However, in the above configuration, the speed at which the data sequentially read from the serial input / output port 34 is stored in the memory cell 31, and the data read from the memory cell 31 to the random input / output port 32 are read. When the memory cell 31 is divided into a plurality of blocks as a countermeasure against the difference in the speeds, the random input / output port 3
The program of the microprocessor connected to 2 must explicitly manage the address according to the block. Further, it is necessary to collectively manage not only the access address from the random port side but also the access address from the serial port side and the update timing thereof, which is very important for the program of the microprocessor connected to the random input / output port 32. There was a problem that a large load was generated.

In view of the above points, an object of the present invention is to provide a 2-port memory which reduces the program load of the microprocessor on the random port side when the memory cell of the 2-port memory is divided into a plurality of blocks. ..

[0010]

In order to solve the above-mentioned problems, a two-port memory according to the present invention has a plurality of memory cells having two data input / output ports and a random port at each one of the plurality of memory cells. Random I / O port commonly connected to the port accessed to the port and the data line commonly connected to the port simultaneously accessed row by row at the other port of each of the plurality of memory cells are input / output in parallel. Shift register, a serial input / output port for serially inputting / outputting data between the shift register and the outside, a random access address input port for inputting an address commonly accessing a plurality of memory cells from the random input / output port, Random I / O port is a lander that stores information to select the memory cell to be accessed from the multiple I / O port side. An access cell selection register, a random port access control unit that inputs an access request signal from the random input / output port side and controls access to the memory cell according to the contents of the random access cell selection register, and a memory cell accessed from the shift register A serial transfer cell selection register that stores information to be selected from multiple memory cells, and a data transfer address that generates an address used for data transfer between the shift register and multiple memory cells and outputs it to multiple memory cells in common. Controls the data transfer between the serial I / O port and the shift register in synchronization with the generator and the clock input from the outside, and multiple memories according to the data transfer request signal input from the outside and the contents of the serial access cell selection register. The memory of one of the cells The serial port access control unit that controls the data transfer between the shift register and the shift register, and the generated address in the data transfer address generation unit, the setting change request signal for the random access cell selection register, and the serial access cell selection A memory cell setting change control unit for inputting a setting change request signal to the register and changing the settings of the contents of the random access cell selection register and the serial access cell selection register is provided.

[0011]

According to the present invention, the memory cell to be accessed from the random port side is set in the random access cell selection register as initialization, the memory cell to be accessed from the serial port side is set in the serial access cell selection register, and further, as initialization. The first address for accessing the memory cell from the serial port side is set in the data transfer address generation unit. When data is input from the serial port side, the serial port access control unit stores the data sequentially input from the serial input / output port in the shift register in synchronization with the serial port control clock. After storing the data string in the shift register,
A data transfer request signal is output to the memory cell set in advance in the serial access cell selection register, and the contents of the shift register are stored according to the address output by the data transfer address generation unit. When the data transfer from the shift register to the memory cell is completed, the data transfer address generation unit generates the next storage address according to the control signal input from the serial port access control unit. By repeating the above series of operations, the data from the serial port side are sequentially stored in the memory cells.

Next, when the random access request signal is input, the random port access control unit outputs a read control signal to the memory cell previously set in the random access cell selection register, and the random access address input port outputs the read control signal. The contents of the memory cell are output to the random input / output port according to the input address.

By the above operation, the program of the microprocessor connected to the random input / output port does not need to explicitly manage the address according to the block, and the access address from the serial port side and its update timing can be set. Need not be managed, and the load on the program of the microprocessor connected to the random input / output port can be reduced.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A two-port memory according to a first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a 2-port memory according to the first embodiment of the present invention. In FIG. 1, reference numeral 32 is a random input / output port, 33 is a shift register, and 34 is a serial input / output port. The above is the same configuration as shown in FIG. 1-1 to 1-n are memory cells having two data input / output ports, 2 is a memory cell 1-1
To 1-n are inputted from the random input / output port 32 through the random access address input port for commonly accessing the random input / output port 32, and 3 is one memory cell to be accessed from the random input / output port 32 side.
The random access cell selection register 4 for storing information selected from n receives an access request signal from the random input / output port 32 side, and controls access to one memory cell according to the contents of the random access cell selection register 3. The random port access control unit 5 is a serial access cell selection register for storing information for selecting one memory cell to be accessed from the shift register 33 from the memory cells 1-1 to 1-n, and 6 is a shift register 33. An address used for data transfer between the memory cells 1-1 to 1-n is generated to generate the memory cell 1-1.
To 1-n are commonly output to the data transfer address generator 7, which controls data transfer between the serial input / output port 34 and the shift register 33 in synchronization with a clock input from the outside, and outputs the data input from the outside. According to the transfer request signal and the contents of the serial access cell selection register 5, one of the memory cells 1-1 to 1-n is controlled to transfer data to and from the shift register 33, and a data transfer address generator is provided. The serial port access control unit for controlling the generated address in 6 receives the setting change request signal for the random access cell selection register 3 and the setting change request signal for the serial access cell selection register 5, and inputs 8 to the random access cell selection register 3. Memory cell setting for changing the contents of serial access cell selection register 5 It is a change control section.

A two-port memory configured as shown in FIG. 1 is connected to a read-only storage device which has a serial input / output port 34 as an input only and is sequentially accessed, and a random input / output port 32 as an output only. The following is a description of the operation in the case of being connected to the microprocessor and being randomly read.

First, as initialization, the microprocessor connected to the random port side outputs a control signal to the memory cell setting change control unit 8 to select the memory cell to be accessed from the random port side as the random access cell selection register 3.
And the memory cell accessed from the serial port side is set in the serial access cell selection register 5.
Further, the first address for accessing the memory cell from the serial port side is set in the data transfer address generation unit 6. When data is input from the serial port side, the serial port access control unit 7 stores the data sequentially input from the serial input / output port 34 in the shift register 33 in synchronization with the serial port control clock. When the storage of the data string in the shift register 33 is completed, a data transfer request signal is output to the memory cells set in the serial access cell selection register 5 in advance, and the shift register is generated in accordance with the address output by the data transfer address generation unit 6. The contents of 33 are stored. When the data transfer from the shift register 33 to the memory cell is completed, the data transfer address generation unit 6 generates the next storage address according to the control signal input from the serial port access control unit 7. By repeating the above series of operations, the data from the serial port side are sequentially stored in the memory cells.

Next, when the random access request signal is input to the random port access control unit 4, the random port access control unit 4 outputs a read control signal to the memory cell previously set in the random access cell selection register 3 to input the random access address. According to the address input from port 2,
The contents of the memory cell are output to the random input / output port.

The memory cell accessed from the serial port side and the memory cell accessed from the random port side used in the above operation are the serial access cell selection register 5 and the random cell connected to the random port side, respectively. It is managed by changing the setting of the contents of the access cell selection register 3.

As described above, according to this embodiment, the program of the microprocessor connected to the random input / output port 32 does not need to explicitly manage the address according to the memory cell, and the load of the program is reduced. It becomes possible.

Next, a two-port memory according to a second embodiment of the present invention will be described with reference to the drawings. Figure 2
FIG. 8 is a block diagram of a 2-port memory according to the second embodiment of the present invention. In FIG. 1, 1-1 to 1
-N is a memory cell, 2 is a random access address input port, 3 is a random access cell selection register, 4 is a random port access control unit, 6 is a data transfer address generation unit, 7 is a serial port access control unit, and above are the figures. The configuration is the same as that shown in FIG. Further, 32 is a random input / output port, 33 is a shift register, and 34 is a serial input / output port. The above is the same configuration as shown in FIG. Reference numeral 11 is a serial access cell selection register for storing information for selecting one memory cell to be accessed from the shift register 33 from among the memory cells 1-1 to 1-n, and 12 is a setting change request signal for the random access cell selection register 3. To change the setting of the contents of the random access cell selection register 3, the random access cell setting change control unit 13 inputs a setting change request signal to the serial access cell selection register 11 to change the settings of the serial access cell selection register 11. In addition, the serial access cell setting change control unit 14 sets the first address for accessing the memory cell from the serial port side to the data transfer address generation unit 6, and 14 is the contents of the random access cell selection register 3 and the random access cell setting change. Control unit 2 is input, the change information output from the serial access cell selection register 11 and the change information output from the serial access cell setting change control unit 13 are input, and one memory cell input / output by the random port side and input / output by the serial port side are input. When a change is made so as to match with one memory cell, the signal for prohibiting the change is output to the random access cell setting change control unit 12 or the serial access cell setting change control unit 13 and the random port side or serial A cell change arbitration unit that outputs a setting change prohibition signal to the port side.

A two-port memory configured as shown in FIG. 2 is connected to a read-only storage device which uses the serial input / output port 34 as an input only and is sequentially accessed, and the random input / output port 32 as an output only. The following is a description of the operation in the case of being connected to the microprocessor and being randomly read.

First, as initialization, the microprocessor connected to the random port side outputs a control signal to the random access cell setting change control unit 12 to set the memory cell accessed from the random port side in the random access cell selection register 3. .. On the other hand, the storage device connected to the serial port side or the reading device of the storage device outputs a control signal to the serial access cell setting change control unit 13, and the memory cell accessed from the serial port side is stored in the serial access cell selection register 11. The data transfer address generation unit 6 sets the first address for accessing the memory cell from the serial port side.
When data is input from the serial port side, the serial port access control unit 7 stores the data sequentially input from the serial input / output port 34 in the shift register 33 in synchronization with the serial port control clock. When the storage of the data string in the shift register 33 is completed, a data transfer request signal is output to the memory cells set in the serial access cell selection register 11 in advance, and the shift register is generated in accordance with the address output by the data transfer address generation unit 6. The contents of 33 are stored. When the data transfer from the shift register 33 to the memory cell is completed, the data transfer address generation unit 6 generates the next storage address according to the control signal input from the serial port access control unit 7. By repeating the above series of operations, the data from the serial port side are sequentially stored in the memory cells.

Next, when the random port access control unit 4 receives the random access request signal, it outputs a read control signal to the memory cell set in the random access cell selection register 3 in advance to input the random access address. According to the address input from port 2,
The content of the memory cell is output to the random input / output port 32.

The memory cell accessed from the random port side used in the above operation is managed by the microprocessor connected to the random port side changing the setting of the random access cell selection register 3. On the other hand, the memory cell accessed from the serial port side is managed by changing the setting of the serial access cell selection register 11. Here, when the contents of the random access cell selection register 3 and the contents of the serial access cell selection register 11 are about to be changed, the cell change arbitration unit 14 detects the change request and tries to change it later. The setting change prohibition signal is output to the port that has been set, and the change is postponed.

As described above, according to this embodiment, the program of the microprocessor connected to the random input / output port does not need to explicitly manage the address according to the memory cell, and the access from the serial port side It is no longer necessary to manage the address and its update timing, and the load on the program of the microprocessor connected to the random input / output port can be reduced.

[0027]

As described above, according to the present invention, it becomes unnecessary for the program of the microprocessor connected to the random input / output port to explicitly manage the address according to the memory cell, and further, from the serial port side. It becomes unnecessary to manage the access address and its update timing, and the load of the program of the microprocessor connected to the random input / output port can be reduced, and the practical effect of the present invention is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a 2-port memory according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a 2-port memory according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a conventional 2-port memory.

[Explanation of symbols]

 1-1 to 1-n memory cell 2 random access address input port 3 random access cell selection register 4 random port access control unit 5 serial access cell selection register 6 data transfer address generation unit 7 serial port access control unit 8 memory cell setting change Control unit 32 Random input / output port 33 Shift register 34 Serial input / output port

Claims (2)

[Claims] 1. A plurality of memory cells having two data input / output ports, a random input / output port commonly connected to a port randomly accessed at one port of each of the plurality of memory cells, and A shift register that inputs and outputs in parallel a data line commonly connected to the ports that are simultaneously accessed row by row at the other port of each of the plurality of memory cells, and data is serially output between the shift register and the outside. The serial input / output port for inputting / outputting, the random access address input port for inputting an address for commonly accessing the plurality of memory cells from the random input / output port, and the memory cell for accessing from the random input / output port side are A random access cell selection register that stores information to be selected from a plurality of memory cells, A random port access control unit for inputting an access request signal from the random input / output port side and controlling access to the memory cell according to the contents of the random access cell selection register; and a memory cell accessed from the shift register, A serial access cell selection register that stores information to be selected from a plurality of memory cells, and an address used for data transfer between the shift register and the plurality of memory cells are generated and commonly output to the plurality of memory cells. The data transfer address generator controls the data transfer between the serial input / output port and the shift register in synchronization with the clock input from the outside, and the data transfer request signal input from the outside and the serial access cell selection register. Multiple memory according to the contents of A serial port access control unit that controls data transfer to and from the shift register for one memory cell of the memory cell, and a generation address in the data transfer address generation unit; and the random access cell selection register. A random access cell selection register and a memory cell setting change control unit for changing the contents of the serial access cell selection register by inputting a setting change request signal for the serial access cell selection register and a setting change request signal for the serial access cell selection register. A 2-port memory characterized in that 2. A plurality of memory cells having two data input / output ports, a random input / output port commonly connected to a port randomly accessed by one port of each of the plurality of memory cells, A shift register that inputs and outputs in parallel a data line commonly connected to the ports that are simultaneously accessed row by row at the other port of each of the plurality of memory cells, and data is serially output between the shift register and the outside. The serial input / output port for inputting / outputting, the random access address input port for inputting an address for commonly accessing the plurality of memory cells from the random input / output port, and the memory cell for accessing from the random input / output port side are A random access cell selection register that stores information to be selected from a plurality of memory cells, A random port access control unit for inputting an access request signal from the random input / output port side and controlling access to the memory cell according to the contents of the random access cell selection register; and a memory cell accessed from the shift register, A serial access cell selection register that stores information to be selected from a plurality of memory cells, and an address used for data transfer between the shift register and the plurality of memory cells are generated and commonly output to the plurality of memory cells. The data transfer address generator controls the data transfer between the serial input / output port and the shift register in synchronization with the clock input from the outside, and the data transfer request signal input from the outside and the serial access cell selection register. Multiple memory according to the contents of A serial port access control unit that controls data transfer to and from the shift register for one memory cell of the memory cell, and a generation address in the data transfer address generation unit; and the random access cell selection register. Of the serial access cell selection register by inputting a setting change request signal to the serial access cell selection register and a random access cell setting change control unit for changing the setting of the contents of the random access cell selection register. Serial access cell setting change control unit for changing settings, contents of the random access cell selection register, change information output by the random access cell setting change control unit, contents of the serial access cell selection register, and the serial access cell Setting When the change information output from the change control unit is input and the memory cell input / output by the random access port and the memory cell input / output by the serial access port are changed to match, A cell change that outputs a change prohibition signal to the random access cell setting change control unit or the serial access cell setting change control unit and outputs a setting change prohibition signal to the random access I / O port side or the serial access I / O port side A two-port memory having an arbitration unit.