JPH0325785A - Memory device - Google Patents

Abstract

PURPOSE:To delete a fast storage element and to effectively use a storage element large in capacity and low in speed by comparing the present input address with its history register by a comparison means, and controlling the storage element based on a comparison result. CONSTITUTION:When an access control signal 1 and address input 2 are supplied and access is started, a preceding row address 9a in a register 9 is compared with a present row address 2a in the input 2 at a comparator 7. When noncoincidence between the addresses 2a and 9a is obtained, the comparator 7 outputs (noncoincidence), and precharges a DRAM 6, and returns the row address 2a and a column address 2b sequentially, and performs prescribed access according to the signal 1. At this time, a control circuit 8 applies the optimum control on the storage element 6, and deletes the fast storage element. The large amount of storage is performed by arranging the memory devices in parallel, and also, memory capacity can be set and changed freely, which attains the effective use of the storage element with low speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a storage device that can appropriately control reading and writing to a storage element based on past history. [Prior Art] In order to efficiently use large-capacity, low-speed memory elements, storage devices that utilize small-capacity, high-speed memory elements have been proposed. Figure 4 shows, for example, rMc68020 User's Manual J (CQ Publishing, June 1986).
This is a simplified block diagram of a conventional storage device shown on page 89 (Monday 1st), where 1 is an access control signal,
2 is an address input, 3 is a data line, 4 is a data memory that holds part of the contents of the storage device, 5 is a tag memory that holds a storage address corresponding to the data memory 4, and 7 is a current address input 2
8 is a control circuit that controls the storage element 6, the tag memory 5, and the data memory 4, and 6 is a storage element. This conventional device uses an access control signal l.
It operates based on address information 2 and exchanges data through data line 3. When the operation is started by the access control signal 1, the address input 2 and the contents of the tag memory 5 are compared by the comparison circuit 7. If the comparison circuit 7 indicates a match and the data corresponding to address 2 among the contents of the storage element 6 has already been copied to the data memory 4, then
The storage device performs a read or write operation on this data memory 4, but does not perform any operation on the storage element 6. Further, if the comparison circuit 7 indicates a mismatch, the data corresponding to the address 2 among the contents of the memory element 6 has not yet been stored in the data memory 4, so the control circuit 8 outputs the address to the memory element 6. 10. By outputting the control output 11, read/write operations are performed according to the access control signal 1, and at the same time, this data is stored.
Update tag memory 5 and data memory 4.

[Problem to be solved by the invention]

As mentioned above, conventional storage devices require high-speed tag memory and data memory, which has the problem of increasing the number of parts. Also, tag memory. When having multiple sets of data memories, it was necessary to add a means to prevent conflicts between them. Furthermore, when the above-mentioned device excluding the memory element is combined into a single chip semiconductor element, there is a problem in that it is difficult to secure sufficient capacity for the tag memory and data memory due to limitations such as the size of the element.

This invention was made in order to solve the above-mentioned problems, and it is possible to eliminate high-speed storage elements such as tag memory and data memory used in conventional storage devices, and also to use large-capacity, low-speed storage elements. The purpose is to obtain a storage device that can be used effectively. [Example] An example of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a storage device according to an embodiment of the present invention. In this figure, numerals 1 to 3.6 and 10.11 are the same as the conventional device shown in FIG. Reference numeral 9 indicates a history register that holds the address from the previous access; 7 indicates a comparison circuit that compares the address of the history register 9 with the current address 2; and 8 indicates a control circuit for controlling the storage element 6 based on the comparison result. This is the control circuit. Here, the memory element 6 is a dynamic type successive memory that gives addresses twice in rows and columns.
It is composed of a writeable semiconductor memory (hereinafter abbreviated as DRAM), and has a high-speed access mode (page mode) that allows access by changing only the column address when the row address is the same. The history register 9 is checked by the row address of the previous access (previous row address) 9a and a valid bit 9b indicating that it is currently valid. The valid bit 1-9b has means for initializing it to indicate "previous row address 9ar invalid" after the device is powered on and before the first access is made.
Address number 2 is a part of the row address of DRAM (
Current row address) 2a and column address (current column address)
Contains 2b.

FIG. 2 is a flowchart showing the operation of the storage device according to the above embodiment. FIG. 3 is a logic circuit diagram showing an example of implementation of the comparison circuit 7.

Next, the operation of the storage device according to this embodiment will be explained. When access control signal (access instruction signal) 1 and address input 2 are given and access to the storage device is started, the previous row address 9a in the history register 9 and address input 2 are input.
The comparison circuit 7 compares the current row address 2a therein.

As shown in FIG. 3, if the valid bit 1-9b indicates that the previous row address 9a is invalid, or if the current row address 2a and the previous row address 9a are not equal, the comparison circuit 7 outputs "no match". On the other hand, valid bit 9
When b indicates that the previous row address 9a is valid and the previous row address 9a and the current row address 2a are equal, the comparison circuit 7 outputs "match j". When the comparison result 7 shows "match",
The row address for memory element 6 is the same as the previous one,
There is no need to issue a new one. Therefore, in this case, by issuing only column address 2b, access can be completed quickly using the high-speed access mode of the DRAM 6.

If the comparison result is "mismatch", the DRAM 6 is once put into a precharge state, and the row address 2a and column address 2b are sequentially sent as in normal access, and the access control signal 1 is sent.
Perform the specified access according to the following.

In this embodiment, past access history is retained in a storage device using a large-capacity, low-speed storage element.
Since the device is structured to provide optimal control to the device, the device can be used quickly and efficiently without adding a high-speed memory device.

In addition, since it does not have the function of copying data like conventional devices, it can support multiple sets of storage elements simply by arranging this storage device in parallel. The complicated control mechanism required in conventional devices can be eliminated.

Similarly, by connecting the required number of storage devices, the storage capacity can be freely set and changed.

Although the above embodiment uses a DRAM as the storage element 6, the present invention is also applicable to other types of semiconductor memory, and can also be applied to storage using other types of storage media such as disk devices. It is also possible to apply it to elements.

Furthermore, in the above embodiment, the memory element 6 is expressed as using individual parts, but this means that a part or the whole of the above embodiment is assembled into a single memory element by means of LSI, etc. It is also possible. Further, in the above embodiment, l sets each of the history register 9, the control circuit 8, and the memory element 6 are used, but it is also possible to provide a plurality of sets of these.

[Effects of the Invention] As described above, according to the present invention, in a storage device using a large-capacity, low-speed storage element, past access history is retained and the current input address and the contents of this history register are stored. Through comparison, we were able to provide optimal control to the elements, which has the effect of allowing the elements to be used quickly and efficiently without the need to add high-speed memory elements. In addition, by simply arranging the storage devices according to the present invention in parallel, it is possible to support multiple sets of storage elements, and to avoid the complicated control mechanism required in conventional devices in order to prevent data inconsistency between data memories. Furthermore, by connecting only the required number of storage devices, you can freely set and store the storage capacity.
It has the effect of allowing changes.

[Brief explanation of drawings]

Fig. i is a block diagram of a storage device according to an embodiment of the present invention, Fig. 2 is a flowchart showing its operation, Fig. 3 is a logic circuit diagram showing an example of implementation of a comparison circuit, and Fig. 4 is a conventional storage device. FIG. 2 is a block diagram of the device. In the figure, 1 is an access control signal, 2 is an address manual, and 2 is an access control signal.
a is the current row address, 2b is the current column address, 3 is the data line, 4
is a data memory, 5 is a tag memory, 6 is a storage element, 7 is a comparison circuit, 8 is a control circuit, 9 is a history register, 9a is a previous row address, 9b is a valid bin 1., IO is an address output, 11
is the control output. Note that the same reference numerals in the figures indicate the same or equivalent parts. Figure 1

Claims (1)

[Claims] (1) A history register that holds a history of previously performed accesses, a comparison means that compares the current input address and the contents of this history register, and a control means that controls the storage element based on the comparison result. A storage device comprising: