JPH06314240A - Cache memory - Google Patents

Abstract

PURPOSE:To provide a cache memory which has drastically large memory capacity and in addition, has comparatively high-speed access time by using a DRAM cell as the cell of the built-in cache of an MPU, and in addition, dispensing with a complicated refresh circuit. CONSTITUTION:A data memory 107 and a tag memory 105 are constituted of first dynamic type memory cells, and a V-bit memory 104 is constituted of second dynamic type memory cells whose discharge time is shorter than that of any first dynamic type memory cell, and it is constituted so as to show that a corresponding data block is valid when the memory cell of the V-bit memory 104 is in a charged state, and show that the corresponding data block is invalid at the time of a discharged state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory, and more particularly to a cache memory effective as a MPU built-in cache memory accommodated in the same chip as a microprocessor (hereinafter referred to as MPU).

[0002]

2. Description of the Related Art The current MPU has an operating speed of over 50 MHz, but a dynamic memory DRAM used as a main memory has a slow access time (70 to 10).
0 nS), which is not suitable for maximizing the performance of MPU.

For this reason, in recent MPUs, an MPU incorporating a cache memory (10 to 20 nS) capable of high-speed access is being put to practical use, but the memory cell is
A static memory SRAM is used.

The memory cell of the SRAM has four transistors 601, 602, 603 and 60 as shown in FIG.
4 and two pull-up resistors 605 and 606.

On the other hand, as shown in FIG. 3, the memory cell of the DRAM is composed of one transistor 301 and one capacitor 302, and the DRAM can be highly integrated, but the access time is slow and it is 70 as described above. ~ 100n
It becomes S.

[0006]

In the above-mentioned conventional cache memory, the access time is short due to the use of SRAM cells, but the occupied area is about four times as large as that in the case of using DRAM cells, so that the storage capacity is small. It has the drawback of This drawback is particularly serious in the MPU built-in cache memory.

An object of the present invention is to use a DRAM cell as a cell of a cache memory and to eliminate the need for a complicated refresh circuit, so that the storage capacity is much larger than that in the prior art and the access is relatively fast. It is to provide a cache memory having time.

[0008]

A cache memory according to the present invention stores a data memory having a DRAM structure for copying main memory data in block units and storing the data, and a main memory address corresponding to the stored block. DRAM
Data stored in the tag memory of the configuration and the data memory is valid (charge) or invalid (discharge)
And a valid display circuit that displays whether or not the data memory and the tag memory are read at the time of access from the processor, and the valid display circuit is set to the limit of a valid display state, and the valid display is performed. The circuit is characterized in that it is in an invalid display state in a time shorter than the discharge time of any memory cell of the DRAM.

[0009]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a cache memory of the present invention.

The cache memory is the tag memory 105, V
It is composed of a bit memory 104, a coincidence comparator 109 and a data memory 107.

The main memory and the cache memory are divided into data transfer units called blocks (16 bytes are one block in this embodiment).

Further, the cache memory has a 1-bit V bit for one block, a tag entry 106 (15 bits in this embodiment) for storing an address, and a data entry 108 (16 in this embodiment for storing data of a block. Bite) and.

In the initial state, all V bits are reset to "0". “0” indicates that the corresponding block of the cache memory does not have valid data. The value "1" of the V bit indicates that the corresponding block holds valid data.

There are a direct map method, a set associative method, a full associative method, etc. as a cache memory configuration method. In this embodiment, the direct map method is used for description.

In the direct map method, blocks of main memory and cache memory are divided into several columns 1.
The cache memory is divided into 13 and 114 (grouped), and the cache memory is limited to one block in the same column of the main memory. In this method, only one match comparator 109 for comparing the addresses held by the tag memory 105 is required.
It has the advantage of a simple structure.

V bit memory 104, tag memory 105
DRAM cells are used for all of the data memory 107, and the tag memory 10 is used for the V-bit memory 104.
5 and a DRAM cell designed to have a shorter discharge time than the memory cell of the data memory 107.

FIG. 5 shows a discharge time distribution 601 of cells of the V-bit memory 104 and a discharge time distribution 602 of cells of the other data memory 107 and tag memory 105. It can be seen that the time distribution 601 is distributed in the shorter side of the time distribution 60.
That is, when simultaneously charged, the DRAM cell used for the V-bit memory 104 is the data memory 1
It is designed such that any one of the DRAM cells used in 07 or the tag memory 105 is completely discharged before being discharged.

Since a normal DRAM cell is guaranteed to hold data of, for example, 4 mS or more, the DRAM cell used for the V-bit memory 104 is designed so that all the cells are discharged within 4 mS.

The discharge state of the V bit cell is made to correspond to "0" (invalid state), and the charge state is made to correspond to "1" (valid state).

Next, the operation of this embodiment will be described.

At the start of MPU instruction access and data read, the block number portion 103 of the MPU address 101
To the decoders 115 and 116 to read the V bit corresponding to the block number, the tag entry 106 and the data entry 108.

The V bit and tag entry 106 are sent to the coincidence comparator 109, and the V bit is "1" (valid state).
And the tag entry 106 is compared to the MPU address 10
1 is compared to the tag address portion 102.

In the initial state, since all V bits are "0", the comparison in the coincidence comparator 109 is non-coincidence, and the hit signal 110 from the coincidence comparator 109 generates "0" indicating non-coincidence. That is, a cache miss occurs.

At the time of a cache miss, the MPU reads one block to which the corresponding address belongs from the main memory and writes the read data to the data directory 108 of the corresponding block number. At the same time, the data is sent to the MPU, and the MPU starts executing the instruction.

On the other hand, if the V bit is in the valid state "1" and the tag entry 106 and the ag address portion 102 match, the hit signal 110 becomes "1" indicating the match.
In this case, since the read data entry 108 holds valid data, it passes through the gate 111, is sent to the data bus 112, and is further sent to the MPU. And M
The PU begins executing instructions.

During this time, the V bit read from the V bit memory 104, the tag entry 106 read from the tag memory 105, and the data entry 108 read from the data memory 107 are written back to their original positions. , Refresh is executed.

The refresh at the time of this read / write is D
This is a function required for the operation of RAM due to the characteristic of destructive read, and is a general operation for all DRAMs.

As described above, the block frequently accessed in the cache memory is automatically refreshed at the time of access, and the block rarely accessed is not refreshed.
After a lapse of time, the V bit "1" valid state is changed to "0" invalid state. Therefore, the block in the cache with high access frequency maintains the valid state, and the block in the cache with low access frequency is automatically invalidated.

As a result, the refresh counter, the refresh controller, etc., which are required when the conventional DRAM cell is used as the memory cell of the main memory or the like, are not required in this embodiment.

The operation for writing data will be further described.

The block number portion 103 of the MPU address 101 is input to the decoders 115 and 116, and the V bit corresponding to the block number, the tag entry 106 and the data entry 108 are read out. The V bit and the tag entry 106 are sent to the coincidence comparator 109 and the V bit is compared with "1", and the tag entry 106 is compared with the tag address portion 102 of the MPU address 101. If the V bit is in the valid state "1" and the tag entry 106 and the doug address 102 match, the hit signal 110 becomes "1" indicating the match.

In this case, since the data entry 108 holds valid data, the write data of the MPU is written in the data entry 108 and at the same time is also written in the main memory.

When the V bit is in the invalid state "0" or the tag entry 106 and the tag address portion 102 do not match, the hit signal 110 becomes "0" indicating the mismatch. In this case, since the data entry 108 does not hold valid data, the write data of the MPU is written only in the main memory.

By the way, in a DRAM packaged in a commercially available package, the address input is divided into a row address and a column address, so the access speed becomes slow, but in the present embodiment, only the block address portion 103 of the MPU address 101 is set to the row address. Since the column address is omitted for the address, relatively high speed access is possible.

Next, a second embodiment of the present invention will be described.

FIG. 2 is a block diagram showing the configuration of the second embodiment of the cache memory according to the present invention. A V bit counter 117 is used instead of the V bit memory 104 in the first embodiment shown in FIG. ing.

As shown in detail in FIG. 5, the V-bit counter 117 is provided for each column and is set to the "invalid" state when all outputs are "0", and the "valid" state is set to "1" or more. To do.

The V bit is designed so that the countdown is completed at 4 mS and the output becomes "0". That is, a normal DRAM cell has four memory cells as in the first embodiment.
Since it is guaranteed to hold data of mS or more,
The V bit is counted down to all "0" within 4 mS and becomes "invalid". all “1” to all
During the period up to "0", the V bit outputs "1" or more, so that the "valid" state is displayed.

In the operation of this embodiment, the V bit memory 104 is refreshed and gradually discharged in the first embodiment, while the V bit counter 11 is used.
There is no difference except that 7 is counted down from all "1" to all "0".

[0041]

As described above, the cache memory of the present invention eliminates the circuits originally required for refreshing, such as the refresh counter and the refresh controller. It has the effect that the capacity can be increased four times. This effect is particularly remarkable in the MPU built-in cache memory in which the MPU and the cache memory are housed in the same chip.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a cache memory of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the cache memory of the present invention.

FIG. 3 is a DRA in the embodiment shown in FIGS. 1 and 2;
It is a structural diagram which shows the structure of M cell.

FIG. 4 is a time distribution diagram showing a distribution of discharge times of a V-bit memory cell and other cells in the embodiment shown in FIG.

5 is a diagram showing a configuration of a V-bit counter in the second embodiment shown in FIG.

FIG. 6 is a structural diagram showing a structure of an SRAM cell in a conventional example.

[Explanation of symbols]

101 SRAM Address 104 V Bit Memory 105 Tag Memory 106 Tag Entry 107 Data Memory 108 Data Entry 109 Match Comparator 117 V Bit Counter 301, 601-604 Transistor 302 Capacitor 401 Discharge Time Distribution of Cell of V Bit Memory 402 Data Memory, Tag Discharge time distribution of memory cells 605, 606 Pull-up resistance

Claims (4)

[Claims] 1. A data memory having a DRAM structure for copying and storing main memory data in block units, a tag memory having a DRAM structure for storing an address of the main memory corresponding to the stored block, and the data memory. And a valid display circuit that indicates whether the data stored in the memory is valid (charge) or invalid (discharge). When the processor accesses, the data memory and the tag memory are read out, and the valid display is performed. A cache memory characterized in that the circuit is set to the limit of a valid display state, and the valid display circuit is set to an invalid display state in a time shorter than a discharge time of any memory cell of the DRAM. 2. The valid display circuit is a second DRAM.
2. The cache memory according to claim 1, wherein the cache memory comprises 3. The valid display circuit is constituted by a counter which is set to "1" at the time of the access, and is counted down thereafter until the display becomes all "0" which is the invalid display state within the time period thereafter, which is a valid display state. The cache memory according to claim 1, wherein 4. The cache according to claim 1, wherein a part of an address supplied from the processor is a row address, and a row of the DRAM is designated only by the row address to read / write data. memory.