JP2005135163A - Device and method for signal processing - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device and a method for signal processing that can perform image processing even when an overlap quantity is small while maintaining arithmetic precision in arithmetic operation such as filter processing by the image processing device. <P>SOLUTION: An SIMD type microprocessor is provided with registers L1 to L3 which are arranged in the order of processor element numbers in a principal processing direction of the image processing and that head processor elements of a plurality of processor elements for processing a plurality of data can access and a memory 14 for reference pixel for quoting data to the registers L1 to L3, the memory 14 for preference pixel being stored with values of registers that processor elements at tail ends have. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a signal processing apparatus and a signal processing method using a single instruction stream multiple data stream (SIMD) type microprocessor that processes a plurality of image data and the like in parallel with one arithmetic instruction, and more particularly to image processing such as digital copying. The present invention relates to a signal processing apparatus and a signal processing method suitable for use in the above.

  In recent years, in digital copying machines, facsimile machines, and the like, improvement of images has been attempted by increasing the number of pixels or by supporting color. As the image is improved, the number of data to be processed has increased. By the way, for example, image processing in a digital copier or the like is processing with a very large amount of data, and the same arithmetic processing is often performed on all pixels. Therefore, a SIMD type microprocessor that frequently performs the same arithmetic processing on a plurality of data with one instruction is frequently used.

  In normal image processing in a SIMD type microprocessor, a plurality of operation units (Processor Elements: processor elements) are arranged in the main direction, and the same operation is simultaneously performed on a plurality of data, thereby enabling high-speed operation processing. It has become.

  Since most conventional SIMD type microprocessors have processor elements larger than the number of pixels in the main scanning direction, the data before image processing stored in the external RAM is arranged in a general-purpose register in the processor element in image processing. Then, after the image processing is performed in the processor element, it is only necessary to output the processed data.

  However, the accuracy of image processing has been improved in recent years, and the number of pixels in the main examination direction is increasing. In particular, in digital copiers and the like, even if the current normal accuracy is 600 DPI (Dot.Per.Inch), the number of processor elements of 7000 pixels or more is required to handle an A4 size image. For this reason, the number of pixels in the main scanning direction is larger than the number of processor elements provided in the SIMD type microprocessor. In this case, the pixels in the main examination direction are divided in units of the number of processor elements, and image processing is repeated for a plurality of times to perform image processing for all the pixels.

  In Patent Document 1, when the number of pixels in the main scanning direction is larger than the number of processor elements provided in the SIMD type microprocessor, a temporary register connected to the main register is provided, and a predetermined number of data is stored in these registers. A technique of cyclically transferring (shifting) between them is disclosed.

  Patent Documents 2 and 3 disclose a data transfer apparatus that can perform data transfer by dividing a pixel when the number of pixels in the main scanning direction is larger than the number of processor elements provided in the SIMD type microprocessor. .

  By the way, when performing image processing such as filter processing, it is necessary to refer to the pixel data of adjacent processor elements, so that the pixel data is prevented from causing problems such as vertical stripes at pixel joints. It is necessary to transfer with overlapping.

  Although it is obvious that the throughput of SIMD microprocessors decreases due to this overlap, the range of reference pixel data tends to expand more and more with filter processing, etc. as the accuracy of image processing devices in recent years has increased. The amount of overlap is increasing.

  For this reason, in Patent Documents 4 and 5 and the like, in order to prevent the invalid pixel data at the edge of the image from adversely affecting the filter processing result in the filter processing, the pseudo pixel obtained by folding the pixel data around the edge of the image is expanded. There is a disclosure of an SIMD microprocessor that has been facilitated.

Further, in Patent Document 6, when the number of pixels in the supervisory direction is larger than the number of processor elements provided in the SIMD type microprocessor, the same configuration SIMD type microprocessor is added to process data. Thus, a technique is disclosed in which image processing can be performed correctly by supplying a plurality of SIMD processors with overlapping pixel breaks.
JP 2000-20705 A JP 2001-134538 A Japanese Patent No. 2862387 JP 2001-344099 A JP-A-8-180177 JP-A-10-326258

  In Patent Documents 4 and 5 and the like, it is easy to expand a pseudo pixel obtained by folding pixel data around an image end so that invalid pixel data at the end of the image does not adversely affect the filter processing result in the filter processing. There is a disclosure of the SIMD type microprocessor. However, this can prevent a decrease in throughput of the SIMD type microprocessor, but there is a problem that a slight error occurs in terms of calculation accuracy.

  Therefore, in view of the above-described problems, the present invention provides a signal processing device and a signal in an image processing device capable of performing image processing even with a small overlap amount while maintaining calculation accuracy in calculations such as filter processing. It aims to provide a processing method.

  According to the first aspect of the present invention, the first processor element of a plurality of processor elements for processing a plurality of data, which is expanded in the main examination direction in the image processing and arranged in the main examination direction in the order of the processor element number, is accessible. A first pixel register and a reference pixel memory for quoting data in the first register, and the second pixel value of the rear end processor element is stored in the reference pixel memory. The signal processing apparatus includes a SIMD type microprocessor configured to store.

  According to a second aspect of the present invention, when the SIMD type microprocessor performs a pixel data calculation process using a plurality of processor elements of the SIMD type microprocessor, each processor element is assigned a processor element having a number lower than its own processor element number. Is issued, the first processor element is referred to the value of the first register, and the data read from the second register is stored in the reference pixel memory. A SIMD type microprocessor that stores the data read from the second register after the reference instruction is issued and stored in the reference pixel memory before the reference instruction is issued in the first register The signal processing apparatus according to claim 1, comprising:

  The invention according to claim 3 includes a third register for designating the processor element number, and the processor element of which processor element number has as data to be stored in the reference pixel memory by the third register. 3. The signal processing apparatus according to claim 1, further comprising a SIMD type microprocessor configured to select whether to store register data.

  According to a fourth aspect of the present invention, the signal processing device according to the first or second aspect is characterized in that the reference pixel memory includes a SIMD type microprocessor which is a data RAM for storing data.

  According to a fifth aspect of the present invention, there is provided a SIMD type microprocessor which controls so that when data having the same capacity as the reference pixel memory is stored in the memory, the data storage is not continued any further. The signal processing device according to item 1 or 2 is provided.

  According to a sixth aspect of the present invention, SIMD microprocessors that perform the same arithmetic processing on a plurality of data with a single instruction, in numerical order in the direction of examination of image processing possessed by the SIMD microprocessor. The value of the second register of the rearmost processor element is stored in the reference pixel memory for quoting data to the first register accessible by the first processor element among the plurality of arranged processor elements The signal processing method includes the step of controlling to do so.

  According to a seventh aspect of the present invention, when the SIMD type microprocessor issues an instruction that refers to a register of a processor element having a smaller processor element number, the first processor element is the first processor element Controlling to reference a value of a register, controlling the SIMD microprocessor to store data read from the second register in the reference pixel memory, and the SIMD microprocessor A step of controlling the processor to store, in the first register, data read from the second register, which is stored in the reference pixel memory before the reference command is issued after the reference command is issued; And a signal processing method according to claim 6.

  According to an eighth aspect of the present invention, the processor element of which processor element number the third register for designating the processor element number provided in the SIMD type microprocessor has as the data to be stored in the reference pixel memory. 8. The signal processing method according to claim 6, further comprising a step of selecting whether to store register data.

  A ninth aspect of the present invention is the signal processing method according to the sixth or seventh aspect, wherein the reference pixel memory is a data RAM for storing data provided in the SIMD type microprocessor.

  The invention according to claim 10 is a step in which the SIMD type microprocessor performs control so as not to continue storing data when the reference pixel memory stores data having the same capacity as the memory capacity. A signal processing method according to claim 6 or 7, comprising:

  According to the present invention, when image processing is performed by dividing pixels in the principal direction, the reference pixel data at the right end when the divided pixel block is processed is transferred to the reference pixel memory. Since the pixel block can be used as reference pixel data at the left end when the next divided pixel block is processed, overlap on the left side of the pixel becomes unnecessary, leading to an improvement in throughput as a processor.

  Further, by adopting a configuration in which the processor element number to be transferred to the reference pixel memory can be designated, the overlap amount can be made variable according to the application.

  Also, by assigning a part of the data RAM to the reference pixel memory according to the required number of overlap amounts, the capacity of the reference pixel memory becomes variable, so that the memory can be effectively used.

  Further, even when there are many instructions that require reference pixel data and there is more data to be stored than the capacity of the reference pixel memory, the processing can be performed correctly.

  One embodiment of a signal processing device according to the present invention is a SIMD type microprocessor in which the top of a plurality of processor elements for processing a plurality of data arranged in the order of processor element numbers in the main direction in image processing. A first register accessible by the processor element and a reference pixel memory for quoting data in the first register are provided, and the second register of the rear end processor element is provided in the reference pixel memory. Configured to store the value of. As a result, the overlap on the left side of the pixel is not necessary, and an improvement in throughput as a processor can be realized.

  A schematic configuration of the SIMD type microprocessor of this embodiment according to the present invention and functions of each block will be described with reference to the accompanying drawings. FIG. 1 is a schematic block diagram of a SIMD type microprocessor according to this embodiment. As shown in FIG. 1, the SIMD type microprocessor of this embodiment includes a global processor 1, a processor element group 4 composed of a plurality of processor elements, and an external interface 5 connected to a memory controller 6. Note that the processor element described above includes a register file 2 and an arithmetic array 3 as shown in FIG.

  The global processor 1 is a so-called SISD (Single Instruction Stream Single Data Stream) type microprocessor. The global processor 1 includes a program RAM and a data RAM, decodes the program, and generates various control signals.

  These various control signals are supplied to the register file 2, the arithmetic array 3, and the memory controller 6 in addition to the control of various built-in blocks. The global processor 1 performs various arithmetic processing and program control processing using a built-in general-purpose register, ALU (arithmetic logic unit), and the like when a GP (global processor) instruction is executed.

  The register file 2 holds data processed by the processor element instruction. The processor element instruction is a single instruction stream multiple data stream (SIMD) instruction, and simultaneously performs the same processing on a plurality of data held in the register file 2.

  Control of reading / writing of data from the register file 2 is performed by control from the global processor 1. The read data is sent to the operation array 3 and processed in the operation array 3, and the operation result is written in the register file 2.

  Further, the register file 2 can be accessed from the memory controller 6 outside the SIMD type microprocessor via the external interface 5, and a specific register is read / written from the outside separately from the control of the global processor 1. Is done.

  The arithmetic array 3 performs arithmetic processing of processor element instructions. Control of this arithmetic processing is all performed from the global processor 1. The memory controller 6 outputs a clock, address, and read / write control to the external port, and outputs a clock, address, and read / write control to the single port memory. Thereby, data transfer is performed between a register of an arbitrary processor element and the single port memory. All control of this processing is performed from the global processor 1.

  Next, the configuration of the SIMD type microprocessor according to the present embodiment will be described in more detail with reference to FIG. FIG. 2 is a block diagram showing the configuration of the SIMD type microprocessor according to this embodiment. As shown in FIG. 2, the global processor 1 includes a program RAM 8 for storing a program and a data RAM 9 for storing operation data of the SIMD type microprocessor of this embodiment.

  Furthermore, the global processor 1 includes a program counter PC that holds a program address, a register G0, a register G1, a register G2, and a register G3 that are general-purpose registers for storing data for arithmetic processing. Stack pointer SP that holds the address of the destination data RAM, link register LS that holds the address of the caller when the subroutine is called, register LI that holds the branch source address at the time of IRQ and NMI, register LN, and processor status And a processor status register P that holds

  The global processor instruction is executed using the above-described registers and an instruction decoder (not shown), ALU, memory control circuit, interrupt control circuit, external I / O control circuit, and global processor operation control circuit.

  The global processor 1 controls the register file 2 and the arithmetic array 3 using an instruction decoder, a register file control circuit, and a processor element arithmetic control circuit (not shown) when executing the processor element instruction.

  As shown in FIG. 2, the register file 2 contains 32 8-bit registers 10 for each processor element. In addition, 256 sets of 8-bit registers 10 in units of one processor element have an array configuration. In addition, each of the 32 registers 10 included in one processor element is referred to as a register R0 to R31.

  Each register 10 has one read port and one write port for the arithmetic array 3, and is accessed from the arithmetic array 3 by an 8-bit read / write bus.

  Of the 32 registers (registers R0 to R31) of the register 10, 24 registers 10 of the registers R0 to R23 can be accessed from the outside of the SIMD type microprocessor via the external interface 5. By inputting a clock, an address, and read / write control from, it is possible to read / write any of the 24 registers 10 of the registers R0 to R23.

  Further, the external access to the 24 registers 10 of the registers R0 to R23 can access one register in each processor element through one external port, and the processor element can be accessed by an address input from the outside. Specify a number (0-255). Therefore, a total of 24 external ports for register access are installed.

  Access from the outside is 16-bit data in one set of even-numbered processor elements and odd-numbered processor elements, and two registers are accessed simultaneously in one access.

  As shown in FIG. 2, the arithmetic array 3 includes a 16-bit ALU 13, a 16-bit register A, and a 16-bit register F. The operation by the processor element instruction is performed by using the data read from the register file 2 or the data given from the global processor 1 as an input on one side of the 16-bit ALU 13 and an input on the other side of the 16-bit ALU 13 Use content. Then, the calculation result by the 16-bit ALU 13 is stored in the register A. Accordingly, the arithmetic array 3 performs an arithmetic operation on the register A and the data supplied from the registers R0 to R31 or the global processor 1.

  A 7 to 1 multiplexer 11 is placed between the register file 2 and the arithmetic array 3. This multiplexer 11 calculates the data of the processor elements 1, 2, and 3 away from the front in the processor element direction, the data of the processor elements 1, 2, and 3 away from the back, and the data of the central processor element. Select as target.

  The 8-bit data of the register file 2 is shifted to the left by an arbitrary bit by the shift & extension circuit 12 and input to the 16-bit ALU 13. Further, the execution / invalidation control of the operation is controlled for each processor element by an 8-bit condition register T (not shown), and only a specific processor element is selected as an operation target.

  Next, the configuration of the SIMD type microprocessor of this embodiment and the function of each block will be described with reference to FIG. FIG. 3 is a block diagram showing the configuration of the SIMD type microprocessor according to this embodiment.

  The SIMD type microprocessor of the present embodiment shown in FIG. 3 has 256 processor elements and uses pixel data equivalent to 16 pixels as an overlap amount of pixel data necessary for image processing. To do. When image processing is performed using the SIMD type microprocessor in this embodiment, processor elements are developed in the main examination direction. For the description of the present embodiment, these processor elements are assigned numbers from the head to the tail in the main examination direction. In this embodiment, when three (processor element PE0, processor element PE1, processor element PE2) having the smallest processor element number refer to data in the register of the front processor element, as shown in FIG. It has three registers (registers L1 to L3) for supplying data.

  These three registers (registers L1 to L3) are used as described below. First, at the time of an instruction to refer to the immediately preceding processor element, the register L1 is referred to by the processor element PE0. At the time of an instruction that refers to the two preceding processor elements, the register L1 is referenced by the processor element PE1, and the register L2 is referenced by the processor element PE0. At the time of an instruction to refer to the three preceding processor elements, the register L1 is referred to by the processor element PE2, the register L2 is referred to by the processor element PE1, and the register L3 is referred to by the processor element PE0.

  Further, the data of the reference pixel memory 14 is input to the three registers L1 to L3, and each time an instruction for referring to the front processor element is issued, the reference pixel memory 14 Is stored after the instruction is executed. The three registers L1 to L3 are supplied with control signals from the global processor 1 and can be set to fixed values such as zero.

  In this embodiment, the reference pixel memory 14 is configured to receive data of register buses of three processor elements of the processor element PE237, the processor element 238, and the processor element 239. Each time an instruction that refers to the preceding processor element is issued, the data read from the registers of these three processor elements is stored in the memory.

  The reference pixel memory 14 is a FIFO memory, and is configured by a dual port memory. Or you may comprise using a single port memory by controlling so that the write and read to a memory may be time-shared.

  In the present embodiment, for simplification of description, the number of pixels of pixel data that need to be overlapped is limited to 16. However, the device configuration can be changed as appropriate according to the number of pixels of pixel data necessary for overlap. For example, the overlap amount can be set from four types of 8, 16, 24, and 32. When the number of pixels of the pixel data necessary for overlap is 8, a multiplexer (not shown) is provided so as to select three processor elements: processor element PE245, processor element PE246, and processor element 247, and a reference pixel memory 14 may be configured to be input.

  Further, when the number of pixels of pixel data necessary for overlap is 16, a multiplexer is provided so as to select three processor elements of processor element PE237, processor element PE238, and processor element 239, and the reference pixel memory 14 is provided. You may comprise so that it may input.

  In addition, when the number of pixel data necessary for overlap is 24, a multiplexer is provided so as to select three processor elements of the processor element 229, the processor element 230, and the processor element 231, and the reference pixel memory 14 is provided. You may comprise so that it may input.

  When the number of pixels of pixel data required for overlap is 32, a multiplexer is provided to select three processor elements of the processor element 221, the processor element 222, and the processor element 223, and input to the reference pixel memory. You may comprise.

  Next, a method for controlling the write / read pointer of the FIFO memory will be described with reference to FIG. FIG. 11 is a diagram for explaining a control method of the write / read pointer of the FIFO memory.

  11 is a data read from the reference pixel memory 14 shown in FIG. 3 to the registers L1 to L3, and L shown in FIG. 11 is data held by the three processor elements PE237 to PE239 shown in FIG. Data write to the reference pixel memory 14 is shown. Further, F shown in FIG. 11 indicates a cycle in which an instruction referring to the front processor element is issued.

  As shown in FIG. 11, both pointers are reset at the head of each SIMD and the first data is read into the registers L1 to L3 shown in FIG. Each time a forward reference command is issued, read / write access to the reference pixel memory 14 shown in FIG. 3 is performed, and the pointer is incremented by one. The write pointer has a value obtained by delaying the read pointer by one clock.

  Next, an address generator of the reference pixel memory 14 shown in FIG. 3 according to this embodiment will be described with reference to FIG. FIG. 5 is a block diagram showing the configuration of the address generator of the reference pixel memory according to this embodiment.

  The address generator of this embodiment is composed of only a 12-bit counter 17 shown in FIG. The counter 17 outputs the counter value as an address as a read pointer, and outputs a value obtained by delaying the counter value by one clock to the reference pixel memory 14 shown in FIG. 3 as an address as a write pointer. The value of the counter is used as an address of the reference pixel memory 14 and becomes an address of reference pixel data up to 4K words.

  A signal for counting up the counter 17 is obtained by decoding the value of the instruction register 15 storing the instruction code read from the program RAM 8 and generating various control signals. Output only when an instruction is issued. The counter 17 may be controlled to be incremented by one after being cleared at the beginning of each SIMD and reading the first reference pixel data into the registers L1 to L3.

  The capacity required for the reference pixel memory 14 varies depending on the amount of processing for performing calculation referring to the pixel data of the preceding and subsequent processor elements such as filter processing. However, considering that the matrix such as the filter is symmetrical, it is sufficient that the capacity is at most half the total number of instructions.

  In this embodiment, since the capacity of the program RAM is 32 bits × 8K words, the capacity of the reference pixel memory 14 is 3 (L1, L2, L3) × 8 bits × 4K words, and the memory address is 12 bits. Is output.

  Next, an example of the instruction format of the SIMD type microprocessor of this embodiment will be described with reference to FIG. FIG. 4 is a diagram illustrating an example of an instruction format of the SIMD type microprocessor according to the present embodiment. To simplify the description, the instruction format is simplified. As shown in FIG. 4, the instruction code is formed of 32 bits.

  The instruction code represents the type of instruction by the fields of bits 31 to 19. If bit 18 is 0, a general register is designated as a source operand, and if bit 18 is 1, a 16-bit immediate value is designated as a source operand.

  In the case of a register operand, bits 17 to 13 are a BSH field, which represents the shift amount of the shifter (shift expander) shown in FIG. Bit 17 is a bit for selecting whether to zero-extend or sign-extend, especially in the case of shift expansion, and determines whether the operation in the ALU is performed without a sign or with a sign.

  Bits 12 to 8 are an Rd field, and designate a register for storing a value after the operation. Bits 7 to 3 are an Rs field, which specifies a source register for calculation. Bits 2 to 0 are PSH fields, which determine from which processor element the source register for the operation is selected.

  In the case of an immediate operand, bit 17 is an S field, and determines whether the operation in the ALU is performed without a sign or with a sign. Bits 15 to 0 are an IMM16 field, and the value specified here is used as an immediate value. In the case of the instruction format shown in FIG. 4, whether or not it is a reference instruction of the front processor element may be a simple configuration because it only needs to decode bit 18 and bits 2 to 0 of the instruction code.

  The effects obtained by the above-described configuration of the SIMD type microprocessor of this embodiment will be described with reference to FIGS. FIG. 7 is a diagram for explaining an image data processing method using the SIMD type microprocessor of this embodiment. FIG. 6 is a diagram for explaining a conventional image data processing method using a SIMD type microprocessor for comparison with FIG.

  As shown in FIG. 6, when the number of pixels in the main scanning direction is larger than the number n of processor elements provided in the SIMD type microprocessor, the number of pixels in the main scanning direction of one line is n units. The image processing is repeated a plurality of times. In FIG. 6, pixel blocks divided every n processor elements are named for convenience as the first SIMD, the second SIMD,...

  As described above, in the case where image processing is performed by repeating a pixel in the main examination direction a plurality of times, when performing operations such as filter processing as described in the background art, reference is made to pixel data of adjacent processor elements. Since it is necessary, a pixel having an invalid operation result is generated at the joint portion of the divided pixels (that is, the processor element portions at both ends). In order not to generate this invalid pixel, the pixel data of the sum of the number of forward reference pixels or the number of backward neighboring pixels referred to in the calculation such as filter processing is overlapped in advance and transferred to the SIMD type microprocessor. (Overlap).

  Next, the image data processing method of this embodiment will be described with reference to FIG. First, in the first SIMD process, as in the conventional image data processing method shown in FIG. 6, the pixel data processed by the processor element is overlapped at both ends of the pixel data by 16 pixels (32 pixels in total). Process with data.

  At this time, the effective pixels are 224 pixels processed by the processor elements PE16 to PE239. When the pixel data of the processor elements PE237 to PE239 (portions painted in gray in FIG. 7) at the rear end of the effective pixel is referred to by the rear processor elements PE240 to 242), the referenced pixel The data is stored in the reference pixel memory 14 shown in FIG.

  Next, the second SIMD processing is performed in a state where pixel data used for overlap is held only at the rear end of the pixel processed by the processor element. The effective pixels are 240 pixels processed by the processor elements PE0 to 239. The data of the processor elements PE237 to 239 at the rear end of the effective pixel is stored in the reference pixel memory 14 when being forward-referenced similarly to the first SIMD.

  Further, regarding the processor elements PE0 to PE2 at the tip of the processor element, when an instruction for referring to the preceding processor element is issued, the data in the gray portion in the first SIMD may be referred to. Therefore, pixel data stored in the reference pixel memory 14 shown in FIG. 3 may be read into the registers L1 to L3 and the values of the registers L1 to L3 may be referred to.

  Further, the data stored at the beginning of the second SIMD and the first of the first SIMD are read into the registers L1 to L3 shown in FIG. When the forward reference instruction is issued, the processor elements PE0 to PE2 refer to the values of the registers L1 to L3, and control to read the data in the reference pixel memory 14 to the registers L1 to L3 after issuing the instruction. Good.

  Subsequently, the third SIMD and subsequent processes are the same as the second SIMD process.

  As described above, according to this embodiment, in the conventional image data processing method shown in FIG. 6, the pixels used for the overlap are the pixels processed by 256 processor elements (processor elements PE0 to PE255). Among these, 32 pixels (processor elements PE0 to PE15, PE240 to PE255) at both ends are pixels to be processed.

  Since these overlapping pixels are not effective pixels, the throughput of pixels processed by 224 processor elements (processor elements PE16 to PE239) is actually limited.

  However, in this embodiment, only the first SIMD needs to overlap at both ends of the pixel processed by the processor element. However, after the second SIMD, only the rear end of the pixel processed by the processor element needs to have an overlap. Therefore, it can be seen that the throughput of pixels processed by 240 processor elements can be obtained.

  In the present embodiment, a configuration is described in which all data in the registers L1 to L3 are stored in the reference pixel memory 14 shown in FIG. 3 each time a forward reference command is issued. However, although not shown in the drawing, the reference pixel memory 14 is divided into three for the register L1, the register L2, and the register L3, and the counter (L1) 17a and the counter (L2) as shown in FIG. ) 17b and an address generator having a counter (L3) 17c may be provided. As shown in FIG. 12, it is obvious that the capacity of the reference pixel memory can be further reduced by controlling the pointers of the three FIFO memories.

  A present Example is described based on an accompanying drawing. FIG. 8 is a block diagram showing the configuration of the SIMD type microprocessor according to this embodiment. In the above-described configuration of the SIMD type microprocessor of the first embodiment, data can only be stored in the reference pixel memory without being limited to a specific processor element.

  However, in this embodiment, by providing a register (processor element selection register: not shown) for selecting a processor element built in the global processor 1, data is stored in the reference pixel memory in each processor element. An address for designating a processor element is supplied, and an arbitrary processor element can be designated by a decoder 18 built in each processor element.

  In the designated processor element, the output enable signal of the bus driver 19 is asserted by the decoder 18. The bus driver 19 has a processor element (4n) read bus for a processor element whose processor element number is a multiple of 4, and a processor element (4n + 1) for a processor element whose processor element number is (multiple of 4 + 1). In the processor element whose processor element number is (multiple of 4 + 2) in the read bus for the processor, in the processor element whose processor element number is (multiple of 4 + 3) in the read bus for the processor element (4n + 2), the processor It is connected to the read bus for the element (4n + 3).

  The four read buses are selected by a multiplexer in accordance with the value of the processor element selection register, and are input to the reference pixel memory.

  According to the configuration described above, the overlap amount can be halved when the number of overlaps varies depending on the application or even when the number of processor elements necessary for processing varies.

    A present Example is described based on an accompanying drawing. FIG. 9 is a block diagram of the SIMD type microprocessor of this embodiment. In this embodiment, the reference pixel memory is constituted by the data RAM 20. The data RAM 20 is a dual port memory, and one port is used as an original data RAM used by the global processor 1 for storing and restoring data, and the remaining ports are used for storing reference pixel data. The reference pixel data is written and read out in a time-sharing manner.

  FIG. 10 is a block diagram showing the configuration of the address generator using the data RAM 20 according to the embodiment of the present invention. The address generator according to this embodiment includes a data address latch 21, a 12-bit counter 22, and an offset register 23 shown in FIG.

  Since the port 1 side address is used as a normal data RAM, the data address is directly output from the data address latch 21 as an address.

  The address on the port 2 side is composed of a 12-bit counter 22 and an offset register 23 having a 4-bit offset value. The offset value may be composed of a register that can be changed by a program.

  According to the present embodiment, the RAM area for the reference pixel can be secured from the data RAM 20 according to the RAM capacity necessary for storing the reference pixel data. Also, in an application that does not require a reference pixel RAM, it can be used as a normal data RAM, thus saving memory.

  A present Example is described based on an accompanying drawing. FIG. 14 is a block diagram showing the configuration of the address generator of the reference pixel memory according to this embodiment. In this embodiment, the address generator of the reference pixel memory has a register 24 indicating the capacity of the reference pixel memory, and has a comparator 25 that compares the value of the register 24 with the address of the counter 17. This is a feature. In this embodiment, when the comparison results are equal, control is performed so as to suppress data write in the reference pixel memory even if a forward reference command is issued.

  According to the present embodiment, when the reference pixel memory becomes full as a result of a large number of forward reference instructions being issued, the subsequent processing can be correctly continued.

  For example, five signal processes that require forward reference pixels such as filter processing (process A with forward reference pixel number a1, process B with forward reference pixel number a2, process C with forward reference pixel number a3, and forward reference pixel number a4 In the process D and the process E) of the forward reference pixel number a5, it is assumed that five processes are performed in the order of processes A to E. Here, when a conventional SIMD type microprocessor is used, (a1 + a2 + a3 + a4 + a5) overlaps are required on both the front side and the rear side of the processor element.

  However, when the SIMD type microprocessors shown in the first to third embodiments are used, when all the forward reference pixel data can be stored in the reference pixel memory, only (a1 + a2 + a3 + a4 + a5) overlaps on the rear side. There is no need for overlap at the front.

  By the way, when the reference pixel memory is full in the process D, for example, in the process D, the SIMD type microprocessor shown in the first to third embodiments is used. In A to C, the forward reference pixel can be correctly reflected, and the forward reference pixel cannot be correctly reflected only in the processes D and E.

  Therefore, in this embodiment, in the reference pixel memory address generator, when the comparison result of the comparator 25 that compares the value of the register 24 indicating the capacity of the reference pixel memory with the address of the counter 17 becomes equal. Even if a forward reference command is issued, control is performed so that data write to the reference pixel memory is inhibited, and processing is performed with only (a4 + a5) overlaps in front. As a result, the process D and the process E can be performed correctly.

1 is a block diagram of a schematic configuration of a SIMD type microprocessor according to a first embodiment of the present invention. 1 is a configuration block diagram of a SIMD type microprocessor in a first embodiment of the present invention. FIG. It is another block diagram of the SIMD type microprocessor in the first embodiment of the present invention. It is a figure which shows the example of an instruction format of the SIMD type | mold microprocessor in 1st Example of this invention. FIG. 2 is a block diagram showing the configuration of a reference pixel memory address generator according to the first embodiment of the present invention. It is a figure explaining the conventional image processing method using a SIMD type | mold microprocessor. It is a figure explaining the image processing method using the SIMD type | mold microprocessor in the 1st Example of this invention. It is a block diagram of the configuration of the SIMD type microprocessor in the second embodiment of the present invention. It is a block diagram of the configuration of the SIMD type microprocessor in the third embodiment of the present invention. It is a block diagram of the configuration of a reference pixel memory address generator using a data RAM in a third embodiment of the present invention. It is a figure for demonstrating the control method of the write / read pointer of the FIFO memory in the 1st Example of this invention. It is a figure for demonstrating the control method of the write / read pointer of the other FIFO memory in 1st Example of this invention. It is another block diagram of the configuration of the reference pixel memory address generator in the first embodiment of the present invention. FIG. 10 is a configuration block diagram of a reference pixel memory address generator in a fourth embodiment of the present invention.

Explanation of symbols

1 Global Processor 2 Register File 3 Arithmetic Array 4 Processor Element Group 5 External Interface 6 Memory Controller 7 Memory 8 Program RAM
9 Data RAM
10 register 11 multiplexer 12 shift & expansion circuit 13 16-bit ALU
14 Memory for Reference Pixel 15 Instruction Register 16 Decoder 17 Counter 18 Decoder 19 Bus Driver 20 Data RAM
21 data address latch 22 counter 23 offset register 24 register 25 comparator A register F register G0 to G3 register L1 to L3 register LS link register LI register LN register P processor status register PC program counter PE0 to 255 processor element SP stack pointer

Claims (10)

A first register accessible by the first processor element of a plurality of processor elements for processing a plurality of data, arranged in the order of processor element numbers in a main examination direction in image processing;
The first register comprises a reference pixel memory for quoting data,
A signal processing apparatus comprising: a SIMD type microprocessor configured to store a value of a second register of a rear end processor element in the reference pixel memory.   When the SIMD microprocessor performs a pixel data calculation process using a plurality of processor elements owned by the SIMD type microprocessor, an instruction for causing each processor element to refer to a register of a processor element having a number lower than its own processor element number is provided. If issued, the first processor element is made to refer to the value of the first register, the data read from the second register is stored in the reference pixel memory, and the reference instruction is issued And a SIMD microprocessor for storing data read from the second register and stored in the reference pixel memory before the reference instruction is issued in the first register. The signal processing apparatus according to claim 1. A third register for designating the processor element number;
A SIMD type microprocessor configured to select, by the third register, data to be stored in a register of a processor element having a processor element number as data to be stored in the reference pixel memory; The signal processing device according to claim 1, wherein   The signal processing apparatus according to claim 1, wherein the reference pixel memory includes a SIMD type microprocessor which is a data RAM provided in advance in the SIMD type microprocessor.   2. A SIMD microprocessor for controlling so that when data having the same capacity as that of the reference pixel memory is stored in the memory, data storage is not continued any more. 3. The signal processing apparatus according to 2.   SIMD microprocessors that perform the same arithmetic processing on a plurality of pieces of data with a single instruction include a plurality of processor elements arranged in numerical order in the main direction of image processing of the SIMD microprocessor. And a step of controlling to store the value of the second register of the rear end processor element in the reference pixel memory for quoting data to the first register accessible by the first processor element. And a signal processing method. When the SIMD type microprocessor issues an instruction that refers to a register of a processor element having a smaller processor element number, the first processor element refers to the value of the first register. A process of controlling
Controlling the SIMD microprocessor to store the data read from the second register in the reference pixel memory;
The SIMD type microprocessor stores, in the first register, data read from the second register, which is stored in the reference pixel memory after the reference instruction is issued and before the reference instruction is issued. The signal processing method according to claim 6, further comprising:   The third register, which is provided in the SIMD type microprocessor, that designates a processor element number stores data of a register of the processor element of which processor element number is stored as data to be stored in the reference pixel memory. The signal processing method according to claim 6, further comprising a selecting step.   8. The signal processing method according to claim 6, wherein the reference pixel memory is a data RAM provided in advance in the SIMD type microprocessor.   The SIMD type microprocessor comprises a step of controlling so that data storage is not continued any more when data having the same capacity as the memory capacity is stored in the reference pixel memory. The signal processing method according to claim 6 or 7.

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