JP2002207707A - Simd type micro-processor having function for selecting constant - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize load processing for a threshold value of a dither matrix in a dither method, in reduced steps, and realize processing upto data loading after conversion, in further reduced steps. SOLUTION: This SIMD type micro-processor includes one global processor, and plural processor elements. In the SIMD micro-processor, plural data buses are arranged from the global processor to the respective processor elements, the each processor element generates a selection signal for assigning selection of any data bus out of the plural data buses, and a signal transmitted from the global processor is stored in a prescribed register in the each processor element via the selected data bus selected by the selection signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a SIMD (Sin
gle Instruction-streamMmul
The present invention relates to a single data-stream type microprocessor.

[0002]

2. Description of the Related Art In a SIMD type microprocessor, the same arithmetic processing can be simultaneously executed on a plurality of data by one instruction. Due to this structure, the calculation is frequently used in applications related to processing (for example, image processing) in which the data amount is very large but the data amount is very large.

[0003] In a normal operation process in a SIMD type microprocessor, a plurality of operation units (Proces) are used.
so Element [PE]; processor element) and execute the same operation on a plurality of data simultaneously.

[0004] The SIMD type microprocessor can sufficiently exhibit its performance in processing in which all PEs operate simultaneously. However, performance cannot be exhibited in a process in which the operation parameters are different for each PE. Examples of "processing in which the calculation parameters differ for each PE" include:
A binarization process using a dither method using a dither matrix may be used.

In the binarization processing by the dither method often used in image processing, a threshold value, which is a criterion for binarization, differs for each pixel. FIG. 4 is an example of a dither matrix of the dither method. This matrix is a 4 × 4 dither matrix. In the binarization processing using the dither matrix, four threshold values are used for one row (line), and the four values are repeated in units of four pixels. More specifically, one line of pixel data sequentially stored in (a predetermined register of) each PE from the end of a number of arranged PEs is compared with the threshold value of one row in FIG. The first line is the threshold of the first line, the second line is the threshold of the second line, the third line is the threshold of the third line, the fourth line is the threshold of the fourth line, the fifth line Is the threshold of the first row..., But within one line, four pixels are compared with four values (the first pixel is the threshold of the first column and the second pixel is the threshold). The second column threshold, the third pixel the third column threshold, the fourth pixel the fourth column threshold, the fifth pixel the first column threshold ...).

When the binarization processing by the dither method is performed by the SIMD type microprocessor, the threshold value stored in a predetermined register of the PE differs depending on the PE. If the number of thresholds is one, the processing in all PEs can be completed by one comparison instruction. However, if the number of thresholds is four as described above, four times are required to complete the processing in all PEs. Is required. As the size of the dither matrix increases, the number of comparison instructions naturally increases accordingly.

In the prior art, in order to cope with the above-mentioned problem, there is a method in which a plurality of threshold values are stored in advance in a register or a local memory of each PE. When a 4 × 4 dither matrix is used, focusing on one PE, four thresholds are repeatedly used for every four lines. Therefore, these 4
The two thresholds are held in (four) registers and used in the comparison instruction. In preparation for the comparison process, in the initialization process, a data transfer instruction is performed four times (or more) per line to store the threshold value for each four pixels in the (PE) register. The storing process is repeated four times (for the number of lines). In the case of this processing, four registers are required in each PE for storing the threshold value. That is,
A problem arises in that hardware resources are consumed considerably.

In some cases, when image data is input from the outside of the microprocessor, a threshold value is input from the outside at the same time. In the case of this method, there is no need to set an instruction for storing the threshold value in the register, so that the processing time for the instruction does not occur (is reduced). However, there remains a problem that a register for storing a threshold value is required for each PE. Further, an extra input port for inputting a threshold value is required.

JP-A-5-67203 and JP-A-6-67203
The SIMD-type microprocessor disclosed in Japanese Patent No. 83787 has a function of inputting data from the outside, and the image data and the threshold value (data) are simultaneously input as described above by utilizing those functions. It is also possible.

JP-A-6-176176 and JP-A-6-176176
In the -259581 (SIMD) processor, each PE is associated with an address in a local memory. The address of the local memory is different for each PE. The data stored in the local memory will be used for processing in the PE. With such a configuration, P
It is not necessary to transfer a different value for each PE in order to load a threshold value into E. At the time of the comparison process with the threshold value, a different local memory address for each PE only needs to be indicated. However, in the initialization processing, it is necessary to load the entire matrix of thresholds, and a memory for holding all of the data is also required.

[0011]

SUMMARY OF THE INVENTION It is an object of the present invention to realize a process of loading a threshold value of a dither matrix in a dither method with a small number of (processing) steps. Further, it is another object of the present invention to realize the processing up to loading of the converted data in fewer steps.

[0012]

SUMMARY OF THE INVENTION The present invention has been made to achieve the above object. The SIMD type microprocessor according to claim 1 of the present invention is a SIMD type microprocessor including one global processor and a plurality of processor elements. That S
In the IMD type microprocessor, a plurality of data buses are provided from the global processor to each processor element, and each processor element specifies which data bus is selected from the plurality of data buses. A selection signal is generated, and a signal transferred from the global processor via the data bus selected by the selection signal is stored in a predetermined register in each processor element.

According to a second aspect of the present invention, in the SIMD type microprocessor, each processor element includes:
Successive serial numbers are sequentially assigned, and in each processor element, a higher digit bit of a predetermined number of digits is replaced with “0” with respect to its own serial number expressed in a binary system,
2. The SIMD microprocessor according to claim 1, wherein a signal formed as a result is the selection signal.

According to a third aspect of the present invention, there is provided a SIMD type microprocessor storing operation result data in each processor element or data derived from the operation result in a predetermined register in each processor element. 2. The SIMD type microprocessor according to claim 1, wherein a signal drawn from said register is used as said selection signal.

According to a fourth aspect of the present invention, there is provided a SIMD microprocessor operated by an instruction code including two or more immediate values. 4. The SIMD according to claim 1, wherein a plurality of immediate values are transmitted.
Type microprocessor.

[0016]

Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a SIMD type microprocessor 2 according to the present invention. The configuration of FIG. 1 is a basic configuration of a SIMD microprocessor 2 according to a first embodiment, a second embodiment, and a third embodiment described later. That is, the first
The SIMD microprocessor 2 according to the second, third, and third embodiments is formed by adding necessary components to the configuration of FIG.

The SIMD type microprocessor 2 shown in FIG.
Generally comprises a global processor 4, a register file 6, and an operation array 8.

(1) Global processor 4 This global processor 4 itself is a so-called SI
It is an SD type processor, and has a built-in program RAM 10 and data RAM 12 (see FIG. 2), decodes a program and generates various control signals. This control signal is also supplied to the register file 6 and the operation array 8 in addition to the various built-in blocks. When a GP (global processor) instruction is executed, various arithmetic processing and program control processing are performed using a built-in general-purpose register, an ALU (arithmetic logic unit), and the like.

(2) Register file 6 This holds data to be processed by a PE (processor element) instruction. PE (processor element) 3
As is well known, SIMD (Single Instrument)
ction-Stream, Multiple Dat
a-Stream) is a structural unit that executes individual operations in a processor. As shown by the register file 6 and the operation array 8 in FIG. 2, the SIMD type microprocessor 2 in FIG. 2 includes 256 PEs 3. The above PE instruction is a SIMD type instruction, and performs the same process on a plurality of data held in the register file 6 at the same time. The read / write control of data from the register file 6 is controlled by the global processor 4.
This is performed by a control signal from. The read data is sent to the operation array 8 and written into the register file 6 after the operation processing in the operation array 8.

The register file 6 is stored in the processor 2
External access is possible, and a specific register is read / written from the outside independently of the control of the global processor 4.

(3) Arithmetic array The arithmetic processing of the PE instruction is performed. All control of the processing is performed by the global processor 4.

FIG. 2 is a block diagram showing a more detailed configuration of the SIMD type microprocessor 2 according to the present invention.

The global processor 4 has a program RAM 10 for storing the program of the processor 2 and a data RAM 12 for storing the operation data.
Further, a program counter (PC) 14 for holding a program address, G0, G1, G2, and G3 registers (16, 18, 20, and 22) as general-purpose registers for storing data for arithmetic processing, A stack pointer (SP) 24 holding an address of the save destination data RAM, a link register (LS) 26 holding an address of a caller when a subroutine is called,
Similarly, IRQ (Interrupt Request;
Interrupt request) and NMI (Non-Maskable)
LI register 28 that holds the branch source address at the time of an interrupt request;
, An LN register 30, and a processor status register (P) 32 that holds the state of the processor.

These registers, (not shown)
Instruction decoder, ALU, SCU (sequential unit), memory control circuit, interrupt control circuit, external I / O
The GP instruction is executed using the control circuit and the GP operation control circuit.

When executing the PE instruction, the instruction decoder, the register file control circuit 56 and the PE operation control circuit 58 are used to control the register file 6 and the operation array 8. Further, it is set so that data can be transferred from the data RAM 12 to the plurality of PE register files 6.

In the register file 6, one P
Thirty-two 8-bit registers 34 are built in E units, and a set of (32) 256 PEs is arranged in an array. The register 34 stores R0, R1,.
R2, ..., R31. Each register 3
Reference numeral 4 denotes one read port and one
It has one write port and 8 bit read /
It is accessed from the operation array 8 by a bus that also serves as a write.
Of the 32 registers, 24 (R0 to R23) can be accessed from outside the processor, and the clock (CLK), address (Address), and read /
By inputting the write control (RWB), it is possible to read and write to an arbitrary register 34. The remaining 8 (R24 ~
The register 34 of R31) is used for temporarily storing operation data of the PE operation.

The operation array 8 includes a 16-bit ALU 36, a 16-bit A register 38, and an F register 40. In the operation by the PE instruction, the data read from the register file 6 or the data given from the global processor 4 is input to one side of the ALU 36, and A
This is performed by using the contents of the register 38 as the other input. The operation result is stored in the A register 38. Therefore, data provided from the R0 to R31 registers 34 or the global processor 4 and A
An operation is performed on the data stored in the register 38.

At the connection between the register file 6 and the operation array 8, a 7to1 (7 to 1) multiplexer 42 is provided. As shown in FIG. 2, when viewed from a certain multiplexer 42, R0 included in three PEs 3 in the left direction
R31 register 34 data and right three PE3
Are set so that the data of the R0 to R31 registers 34 included in the P1 and the data of the R0 to R31 registers 34 included in the PE 3 to which the P3 belongs can be selected as the operation target. The shift / expansion circuit 44 shifts the 8-bit data of the register file 6 by an arbitrary number of bits.
Left shift and input to ALU 36.

Each PE 3 is assigned a serial number called a PE number. The SIMD type microprocessor 2
In this example, since the number of PEs is 256, an 8-bit bit string (that is, 00000000b to 11111111) is used.
256 ways of b. In this specification, the suffix "b" as described above indicates that the binary notation is used. ), Each PE
3 is given as PE number data. The PE number may be given to each PE 3 irrespective of the position of the PE, but in this specification, it is assumed that the PE numbers are assigned in order from the end.

Using this PE number, a specific PE3 can be selected and a predetermined value can be set in the 8-bit condition register 54 (see FIG. 3) included in the operation array 8 of the PE3. With this condition register 54, it is possible to control the execution / non-execution of the operation for each PE3. That is, it is possible to select such that only the specific PE3 performs the calculation.

The above PE number data is stored in each PE3
Is provided by providing an 8-bit input terminal and changing the combination of connecting the terminal to VCC or GND.

The PE number generation circuit 60 shown in FIG.
This is a circuit that can create an E number. Further, the PE number generation circuit 60 is set so as to be able to generate a number (column) forming a predetermined repetitive pattern in accordance with the order of the PE numbers under the control of GP4. That is, for example, PE
The numbers are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
In PE3 marked with 10 ..., those P3
That is, the PE number generation circuit 60 provided in E3 can generate numbers forming a repetitive pattern of 0, 1, 2, 3, 0, 1, 2, 3, 0, 1,. . The repeating pattern is, of course, not limited to the above.

<Binarization Processing of Dither Method Based on Basic Configuration> First, the SI shown in the block diagrams of FIGS.
The binarization process of the dither method using the MD microprocessor 2 will be described with reference to the block diagram of FIG. 3 according to the present invention. In the dither method described below, a 4 × 4 dither matrix is used.

For the purpose of repeatedly associating each PE3 with four values belonging to one row of the dither matrix in units of four PE3s, a plurality of (256)
It is necessary to classify each PE3 into four types in order from the end of the arranged PE3.

First, in each PE, the PE number data is
The A register 38 is loaded from the E number generation circuit 60.
Subsequently, the data stored in the A register 38 is divided by "4" according to an instruction to the processor 2, and the remainder value is obtained. This value replaces the lower two bits of the PE number data with 0 (that is, the PE number data and “0x
3 ").
It is assumed that the operation result is stored in the A register 38. Then, this operation result value becomes, in order from the PE3 with the smallest PE number, 0, 1, 2, 3, 0, 1, 2, 3, 0,... In each PE3, the content of the A register 38 is PE
3 in order from the end (from the PE number with the smallest PE number)
It is a repetition of four types of values.

As described above, under the control of GP4, the PE number generating circuit 60 may generate a number (column) for forming a predetermined repeating pattern in accordance with the order of the PE numbers. That is, for example, if the PE numbers are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
In the PE3 denoted by..., A repetition pattern of 0, 1, 2, 3, 0, 1, 2, 3, 0, 1,... Is formed in the PE number generation circuit 60 provided in the PE3. Alternatively, a number may be created and stored in the A register 38.

Next, an instruction to the processor 2 causes all P
A comparison operation is performed with "1" in the A register 38 of E3. If they match, at that PE3: T1 = 1. Here, the 8-bit condition register 54
In order from the lowermost bit: T0, T1, T2, T3, T4, T5, T6, T7.

In accordance with the following instruction, if a comparison operation is performed with "2" and a match is made, T2 = 1 is set in the PE3, and if a comparison operation is performed with "3" and the match is made, T3 = 1 is set in the PE3.

Each value of the dither matrix is stored in the program RAM 10 or the data RAM 12 in the GP 4. First, in response to an instruction to the processor 2, the threshold value of the first column of the dither matrix is loaded into the A registers 38 of all PEs 3 via, for example, the immediate data bus 53. Next, in accordance with an instruction to the processor 2, the threshold value of the second column of the dither matrix is loaded into the A register 38 of PE3 in which "T1 = 1". Further, the threshold value of the third column of the dither matrix is loaded into the A register 38 of PE3 in which “T2 = 1”. Further, the threshold value of the fourth column of the dither matrix is set to “T3 =
The data is loaded into the A register 38 of PE3 which is "1". By these loading operations, a desired threshold value is stored in the A register 38. In each PE3, these threshold values are compared with data in a register (for example, an R0 register) in which pixel data of an image is stored. According to the comparison result (that is, according to the magnitude relationship between the threshold value and the pixel data), each operation result data is set to “0x
ff ”or“ 0x00 ”. Here, the binarization processing of the dither method for one line is completed.

In arithmetic processing using the SIMD type microprocessor 2, the number of pixels in one line of image data may exceed the number of PEs provided in the processor 2. In that case, one line is divided by the number of PEs, and the same processing is repeated by the number of divisions.

In the binarization processing of the dither method, although the comparison processing between the pixel data of the image and the threshold value is completed by one instruction, the instruction step for loading the threshold value is separately provided as described above. Needed. Moreover, the instruction step must be executed each time the divided processing is repeated. However, the load operation of the threshold is 1
This is performed only in the first division processing of the line processing, the threshold value used at that time is stored in a predetermined register (eg, R1) of the PE, and in the subsequent division processing, the register (R
If the threshold value stored in 1) is used, the number of instruction steps can be reduced. However, even in this case, there remains a problem that some registers of each PE 3 are occupied for storing the threshold value.

<First Embodiment> FIG. 5 shows a SIMD type microprocessor 2 according to a first embodiment of the present invention.
Is shown. Some components are added to the SIMD type microprocessor 2 of FIGS. 1 and 2.

The global processors (GP) 4 to 4
Parameter buses (first parameter bus 62-0,
Via a second parameter bus 62-1, a third parameter bus 62-2, and a fourth parameter bus 62-3)
Four sets of 8-bit data are configured to be supplied to each PE3. In each PE3, the four sets of 8
Four buffer circuits (66-0, 66-1, 66-2, 66-3) are set to receive bit data. These buffer circuits connect the four parameter buses to the internal bus 70 of each PE 3.

Further, four sets of leads (first leads 64-
0, the second lead 64-1, the third lead 64-2, and the fourth lead 64-3) are the four buffer circuits (66-0, 66-1, 66-2, 66-3) of each PE3. ). These leads (64-0, 64-1, 6
4-2, 64-3) is the above-mentioned 8 as described later.
A 1-bit signal that controls the timing at which bit data is output to the internal bus 70 of each PE 3 is supplied.

The above four parameter buses include GP4
The data in the data RAM 12 is transferred. In the present embodiment, the threshold data of the dither matrix is transferred as such.

In each PE 3, four parameter buses (62-0, 62-1, 62-2, 62-3),
That is, four buffer circuits (66-0, 66-1, 66-
2 or 66-3), the PE number generation circuit 60 sends a 2-bit selection signal to the four buffer circuits (66-0, 66-1, 66-2, 66-3). Is entered. Each buffer circuit (collectively denoted by reference numeral 66) decodes this selection signal to determine whether or not the selection is for itself.

It is to be noted that the selection signal is decoded by the PE number generation circuit 66 to be created (for example, the lower 2 bits are decoded to create a 4-bit selection signal), and the decoding is not performed by the buffer circuit 66. Even with such a configuration, the above function can be realized (however, the number of bits of the selection signal increases).

The SIMD type microprocessor 2 shown in FIG. 5 has four parameter buses (collectively indicated by reference numeral 62), but may have more than four, for example, eight parameter buses 62. Is also good. As for the dither method, if the number of parameter buses 62 is large, it is possible to cope with a larger dither matrix. When the number of parameter buses 62 is eight, eight buffer circuits 66 must be set in each PE 3. In this case, for example, the PE number generation circuit 66 of each PE 3 outputs the lower 3 bits of the PE number as a selection signal. Each buffer circuit 66 determines whether or not the selection is for itself by decoding the 3-bit selection signal.

Regarding the read operation (collectively denoted by reference numeral 64), the operations of the four sets are equivalent, and therefore the read operation may be constituted by one set (one). Further, as described above, the PE number generation circuit 60 can generate a number (column) forming a predetermined repetitive pattern in accordance with the order of the PE numbers under the control from GP4.

FIG. 6 shows an example of the configuration of the four buffer circuits 66. FIG. 6A shows the first buffer circuit 66 corresponding to the first parameter bus 62-0 and the first lead 64-0. −0. The bus denoted by reference numeral "68" is a selection signal bus (68), which is composed of two bits. The lower bit is input to “CT0” and the upper bit is input to “CT1”. The lead (first lead 64-0) is shown below the figure. According to the circuit configuration of FIG. 6A, “00b” is input as a selection signal,
When the signal “1b” is input to the first lead 64-0, a signal (data) passing through the first parameter bus 62-0 is output to the internal bus 70.

Similarly, FIG. 6B shows the second parameter bus 62-1 and the second lead 64-1 corresponding to the second parameter bus 62-1.
Of the buffer circuit 66-1. In this circuit configuration, when “01b” is input as the selection signal and the signal “1b” is input to the second lead 64-1,
(Data) passing through the parameter bus 62-1 is output to the internal bus 70.

FIG. 6C shows a third buffer circuit 66-2 corresponding to the third parameter bus 62-2 and the third lead 64-2. In this circuit configuration, when “10b” is input as the selection signal and “1b” is input to the third lead 64-2, a signal (“B”) passing through the third parameter bus 62-2 ( Data) is output to the internal bus 70.

FIG. 6D shows a fourth buffer circuit 66-3 corresponding to the fourth parameter bus 62-3 and the fourth lead 64-3. In this circuit configuration, when “11b” is input as the selection signal and “1b” is input to the fourth lead 64-3, the signal (“B”) passing through the fourth parameter bus 62-3 ( Data) is output to the internal bus 70.

A procedure for performing the binarization process of the dither method using the SIMD type microprocessor 2 of the first embodiment will be described.

The PE number generation circuit 60 of each PE 3 generates a number (column) that forms a predetermined repetitive pattern when viewed in the order of the PE numbers according to an instruction to the processor 2.
The value is given to the buffer circuit 66 as a selection signal.

The number generated by the PE number generation circuit 60 is, for example, the lower two bits of the PE number (expressed in binary). That is, if the PE number is: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
In the PE3 denoted by..., A repetition pattern of 0, 1, 2, 3, 0, 1, 2, 3, 0, 1,... Is formed in the PE number generation circuit 60 provided in the PE3. The number is calculated and given to the buffer circuit 66 as a selection signal.

Also, the same instruction causes the data RAM 12
The upper four “thresholds” are simultaneously transferred to each PE 3 via the four sets of parameter buses 62. In each PE 3, the selection signal provided from the PE number generation circuit 60 is decoded by the buffer circuit 66. As a result, one of the data of the four parameter buses 62 is selected. Data related to the selected parameter bus 62 (ie, “threshold”) is output to the PE internal bus 70.

The data output to the PE internal bus 70 is input to the ALU 36 via the multiplexer 42 and the shifter 44, and is stored in the A register 38.

Here, a threshold to be selected is selected from the four sets of thresholds in the A register 38.
Will be stored in one instruction. Subsequent processing is the same as described above.

With the above-described processing, the loading processing of the threshold value, which has conventionally been performed by the number of threshold values, can be realized in one step (processing). Thus, processing time is reduced.

<Second Embodiment> FIG. 7 shows a SIMD type microprocessor 2 according to a second embodiment of the present invention.
Is shown. The configuration is roughly the same as the configuration of the SIMD type microprocessor 2 (FIG. 5) of the first embodiment.

In the SIMD type microprocessor 2 of the first embodiment, the signals output from the PE number generation circuit 60 are used as the selection signals for the four buffer circuits 66. On the other hand, the SIM of the second embodiment
In the D-type microprocessor 2, the condition register 5
Two bits of 4, for example: (T1, T2) provide the selection signal. The supply source that supplies (generates) the selection signal may be any register that can store an arbitrary value for each PE 3, and is not limited to the condition register 54. For example, the A register 38 and the F register 40
It may be.

A procedure for performing the binarization processing of the dither method using the SIMD type microprocessor 2 of the second embodiment will be described.

In each PE 3, P
An E number is created and loaded into the A register 38. next,
The AND processing is performed on the data loaded into the A register 38 and “0x3”. That is, A register 3
In the data loaded in No. 8, data other than the lower two bits are replaced with “0b”. Then, this data is
Transfer to E register (for example, R2 register).

The data transferred to the R2 register is shifted by one bit to the left (higher order) and loaded into the condition register 54. As described above, in each PE3, the lower two bits (T1, T2) of the condition register 54 excluding the least significant bit
Are set (repeated in order from the end of PE3).

Next, according to an instruction to the processor 2, four "thresholds" are simultaneously set in the four parameter buses 62.
To each of the PEs 3 via the. In each PE 3, the selection signal given from the condition register 54 is decoded by the buffer circuit 66. As a result, the four parameter buses 62
Is selected. The data (ie, “threshold”) associated with the selected parameter bus 62 is P
It is output to the E internal bus 70.

The data output to the PE internal bus 70 is input to the ALU 36 via the multiplexer 42 and the shifter 44 and stored in the A register 38.

Here, the threshold to be selected from the four sets of thresholds is selected and stored in the A register 38. Subsequent processing is the same as described above.

In the above-described example of the processing procedure of the second embodiment, the example of the processing procedure in the above description of the first embodiment is substantially the same as that of the second embodiment. Using the SIMD type microprocessor 2 of
Generation of a repetitive pattern for classifying each PE 3 can be performed more freely. In the configuration of the SIMD type microprocessor 2 according to the first embodiment, it is assumed that the variation of the repetition pattern formed by the PE number generation circuit 60 is not so large. That is, P
Since the E number generation circuit 60 has a simple circuit configuration as described above, the repetition patterns that can be generated are: 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1.
.. 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3
.. 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3,
It is limited to those which repeat a power of 2, such as 4, 5, 6, 7. On the other hand, the configuration of the SIMD type microprocessor 2 according to the second embodiment can also cope with binarization processing by a dither method using a 3 × 3 dither matrix or a 6 × 6 dither matrix. Further, 0, 1, 2, 3, 3, 2, 1, 0, 0, 1, 2, 3,
Patterns such as 3, 2, 1,... Can also be generated.

As described in <Third Embodiment><Binarization Processing of Dither Method by Basic Configuration>
After the threshold value is loaded in each PE3, the image data is compared with the threshold value, and the operation result data (image data) is set to “0xff” for the PE3 equal to or larger than the threshold value, and is set to “0xff” for the PE3 smaller than the threshold value. 0x00 ".

This will be described in more detail. For example, first, the image data is compared in magnitude with a threshold value by an instruction to the processor 2, and in the PE 3 where the image data is equal to or larger than the threshold value,
(In the T1 bit of the condition register 54) "T1 =
1 ", PE3 with image data below the threshold
Then, “T1 = 0” is set. Next, in accordance with the instruction to the processor 2, the data "0xff" is loaded in the PE3 where "T1 = 1", and in response to the instruction to the processor 2, the data "0x0" is loaded in the PE3 where "T1 = 0".
Load 0 ".

As described above, a two-step instruction is required to load data "0xff" and subsequently load data "0x00". The SIMD type microprocessor 2 according to the third embodiment of the present invention performs
This is realized by executing a step command.

Here, the SIMD according to the third embodiment
The configuration of the type microprocessor 2 is substantially the same as the configuration of the SIMD type microprocessor 2 according to the second embodiment. The SIMD type microprocessor 2 according to the third embodiment is configured to be operated by a load instruction code 84 whose mapping is shown in FIG.

The load instruction code (example) 84 in FIG.
For example, two load values (immediate values) to be loaded into the A register 38 are provided. In a normal load instruction code in the prior art, there is only one immediate value. For example, only one immediate value is required such that the immediate value is loaded into the A register 38 only for PE3 in which the value stored in the predetermined bit of the condition register 54 satisfies the predetermined condition. You.

In the SIMD type microprocessor 2 according to the present embodiment, two immediate data are transferred from the first parameter bus 64-0 and the second parameter bus 64- 1 are output. That is, “immediate 0” 80 (FIG. 8) is output to the first parameter bus 64-0, and “immediate 1” 82 (FIG. 8) is output to the second parameter bus 64-1. Selection of output data to the parameter bus 64 (64-0, 64-1) is performed by a multiplexer (not shown) in the register file control circuit 56. In this case, a value stored in the data RAM 12 or an immediate value as described above is selected depending on the type of the instruction related to the load.

In each PE3, the result of the magnitude comparison between the image data and the threshold value is stored in "T1" of the condition register 54 as described above. The data stored in “T1” is provided to the buffer circuit 66 as a selection signal. This selection signal causes the first parameter bus 64-
0 or the second parameter bus 64-1 is P
Selected for each E3. The data related to the selected parameter bus 64 is output to the PE internal bus 70. The data output to the PE internal bus 70 is
2. The data is input to the ALU 36 via the shifter 44 and stored in the A register 38.

As a result, when "T1 = 0", the first parameter bus 64-0 is selected, and when "T1 = 1", the second parameter bus 64-1 is selected. Therefore, data “0x00” is designated as data (immediate value 0) output to the first parameter bus 64-0, and data (immediate value 1) output to the second parameter bus 64-1.
If the data "0xff" is designated as, the binarization process can be performed with only one step instruction.

In the load instruction code shown in FIG. 8, "0x00""0xf" is used as an immediate value (immediate value 0, immediate value 1).
Of course, it is also possible to describe a value other than f ″.

[0080]

The following effects can be obtained by using the SIMD type microprocessor 2 according to the present invention.

By using the SIMD type microprocessor 2 according to the first embodiment, the load processing of the threshold value of the dither matrix of the dither method, which has conventionally required the number of types of threshold values, is performed once. And the processing time can be shortened.

By using the SIMD type microprocessor 2 according to the second embodiment, the load processing of the threshold value, which conventionally takes the number of types of threshold values, can be performed similarly to the first embodiment. This can be realized by one step (processing), and the processing time is shortened. Furthermore, even if the repetition pattern of the threshold value is more complicated, it can be handled.

By using the SIMD type microprocessor 2 according to the third embodiment, each PE selects one of two immediate data (described in one instruction) and performs processing up to loading. The processing can be realized by one step.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a SIMD type microprocessor according to the present invention.

FIG. 2 is a block diagram showing a more detailed configuration of a SIMD type microprocessor according to the present invention.

FIG. 3 is a block diagram showing a basic configuration of a SIMD type microprocessor according to the present invention.

FIG. 4 is an example of a dither matrix of a dither method.

FIG. 5 is a block diagram illustrating a detailed configuration of a SIMD microprocessor according to the first embodiment of the present invention;

FIG. 6 is an example of a configuration of a buffer circuit.

FIG. 7 is a block diagram illustrating a detailed configuration of a SIMD microprocessor according to a second embodiment of the present invention;

FIG. 8 is a mapping diagram of a load instruction code according to the third embodiment of the present invention.

[Explanation of symbols]

2 SIMD microprocessor, 3 processor element, 4 global processor, 6
Register file, 8 ... operation array, 36 ... 1
6-bit ALU, 38 A register, 50 dither matrix, 53 immediate data bus, 54
· Condition register, 56 ··· Register file control circuit, 58 ··· PE operation unit control circuit, 60 ··· PE number generation circuit, 62-0 ··· First parameter bus, 6
2-1 ... second parameter bus, 62-2 ... third parameter bus, 62-3 ... fourth parameter bus, 64-0 ... first read, 64-1 ... second lead, 64-2 ... third lead, 64-3
..The fourth lead, 66-0 ... the first buffer circuit, 66-1 ... the second buffer circuit, 66-2 ...
A third buffer circuit, 66-3... A fourth buffer circuit, 68... A selection signal bus, 70.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 1/405 H04N 1/40 C

Claims (4)

[Claims] 1. An SIMD microprocessor including one global processor and a plurality of processor elements, wherein a plurality of data buses are provided from the global processor to each processor element. Generating a selection signal specifying which data bus is to be selected from the plurality of data buses; and transmitting a signal transferred from the global processor via the data bus selected by the selection signal to each processor element. SIM stored in a predetermined register of
D-type microprocessor. 2. A serial number is sequentially assigned to each processor element. In each processor element, an upper bit of a predetermined number of digits is set to "0" with respect to its own serial number expressed in a binary system. 2. The SIMD type microprocessor according to claim 1, wherein a signal formed as a result is used as the selection signal. 3. An operation result data in each processor element, or data derived from the operation result,
2. The SIMD type microprocessor according to claim 1, wherein said selection signal is stored in a predetermined register in each processor element, and a signal extracted from said register is used as said selection signal. 4. An SIMD microprocessor operated by an instruction code including two or more immediate values, wherein the plurality of immediate values are transmitted to the plurality of data buses. 4. The SIMD type microprocessor according to 3.