JP7225904B2 - Vector operation processing device, array variable initialization method by vector operation processing device, and array variable initialization program by vector operation processing device - Google Patents

Description

The present invention relates to a technique for initializing array variables by an information processing device capable of executing vector operations.

2. Description of the Related Art In recent years, as software becomes more sophisticated in various technical fields, the scale of software is rapidly increasing. Since the array variables (array data) used in such software are also becoming large-scale, there is a need for a technique for efficiently and quickly initializing and setting data for large-scale array variables.

As a technology related to such a technology, Patent Document 1 discloses that when a plurality of processors processes data assigned to their own devices, data input from an input device or arrangement data stored in a storage device is processed. A distributing/collecting processor for array data is disclosed which divides all or part of it and allocates it to each storage space or each processor. This device creates a transfer table having information about the range of each dimension, corresponding to divided blocks divided in one or more arbitrary dimensions to be allocated to each storage space or each processor. This device transfers data to each storage space or each processor for each divided block based on the created transfer table. This device then automatically distributes data according to arbitrary transfer patterns.

Further, Patent Document 2 discloses a constant assignment method that can perform array initialization processing at high speed without consuming a large amount of memory resources. In this method, a physical memory block storing "0" values for pseudo-clearing the array space to 0 is prepared in advance in the physical memory. In this method, a table of physical memory pages indicating physical memory blocks is prepared in advance. In this method, even if a user program is started and an array appears, no physical memory block (physical memory page) is specifically reserved for the array space. In this method, each array space is set to be linked with a physical memory block (physical memory page) in the initialization state.

JP-A-04-321158 Japanese Patent Application Laid-Open No. 2004-030353

A vector arithmetic processing unit capable of executing vector arithmetic, such as a supercomputer, generally initializes array variables by issuing a vector store instruction, which is a vector arithmetic instruction for writing to memory. . That is, in the vector processor, predetermined initial values are written to the array variables stored in the memory by vector store instructions. Initialization of array variables is usually performed intensively when software execution is started. When executing vector operation instructions, a certain amount of overhead (the cost associated with executing processing) is usually incurred. Therefore, when executing software that uses many large array variables, array variables A vector store instruction that initializes may stay in the arithmetic core.

In such a case, the subsequent vector operation instruction is not executed and stays in the operation core, resulting in a problem of performance degradation. That is, the problem is how to perform processing for initializing array variables at high speed in a vector arithmetic processing device. Patent documents 1 and 2 mentioned above do not refer to this problem. A main object of the present invention is to provide a vector arithmetic processing device or the like that solves this problem.

A vector operation processing apparatus according to one aspect of the present invention includes vector control means for controlling execution of operations on array variables stored in a memory by vector operation instructions; and a scalar operation instruction for accessing the memory in the same manner as the vector operation instruction without using the vector operation instruction. and an execution means for executing by converting the

In another aspect of achieving the above object, according to an aspect of the present invention, there is provided an array variable initialization method by a vector operation processing device, in which the vector operation processing device performs operations on array variables stored in a memory using vector operation instructions. to control the execution of the vector It is executed by converting it into a scalar operation instruction that accesses the memory in the same manner as an operation instruction.

In a further aspect of achieving the above object, an array variable initialization program by a vector operation processing device according to one aspect of the present invention performs operations on array variables stored in a memory using vector operation instructions. a determination process for determining whether or not an instruction to be executed is an initialization instruction for initializing the array variable; and a process for executing the initialization instruction without using the vector operation instruction. , and an execution process executed by converting the vector operation instruction into a scalar operation instruction for accessing the memory in the same manner as the vector operation instruction.

Furthermore, the present invention can also be realized by a computer-readable, non-volatile recording medium storing an array variable initialization program (computer program) by the vector processing device.

INDUSTRIAL APPLICABILITY The present invention makes it possible to execute processing for initializing array variables at high speed in a vector processing device.

1 is a block diagram showing the configuration of a vector arithmetic processing device 10 according to a first embodiment of the present invention; FIG. 4 is a diagram illustrating an address range accessed by the vector processing device 10 according to the first embodiment of the present invention to access the memory module 161 when initializing array variables stored in the memory 16. FIG. 4 is a flow chart showing an operation of initializing array variables by the vector processing device 10 according to the first embodiment of the present invention; 4 is a time chart (1/2) of initialization processing of array variables by the vector processing device 10 according to the first embodiment of the present invention; 4 is a time chart (2/2) of initialization processing of array variables by the vector processing device 10 according to the first embodiment of the present invention; FIG. 3 is a block diagram showing the configuration of a vector arithmetic processing device 20 according to a second embodiment of the present invention; 1 is a block diagram showing the configuration of an information processing device 900 capable of executing a vector arithmetic processing device according to each embodiment of the present invention; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment>
FIG. 1 is a block diagram showing the configuration of a vector arithmetic processing device 10 according to the first embodiment of the present invention. The vector processing device 10 is an information processing device, such as a supercomputer, capable of executing vector processing. The vector arithmetic processing device 10 is roughly divided into one or more arithmetic cores 11 , a memory access controller 15 and a memory 16 .

The arithmetic core is, for example, a CPU (Central Processing Unit), reads and executes a program (software) stored in the memory 16 which is the main memory, and stores the execution result in the memory 16 . The memory access control unit 15 controls access (reading or writing of data) from the arithmetic core 11 to the memory 16 .

The arithmetic core 11 includes a vector control section 12 , an instruction processing section 13 and an address control section 14 . In this embodiment, the instruction processing unit 13 and the address control unit 14 may be collectively referred to as an execution unit.

The instruction processing unit 13 includes a determination unit 131 and a scalar register 132 . The instruction processing unit 13 fetches instructions included in a program to be executed, decodes the fetched instructions, and executes the decoded instructions.

The instructions executed by the instruction processing unit 13 according to this embodiment are roughly classified into vector operation instructions and scalar operation instructions. However, the vector operation instruction is, for example, an operation instruction that performs similar operations on a plurality of elements included in an array variable by pipeline processing. On the other hand, a scalar operation instruction is an operation instruction other than the vector operation instruction described above, for example, an operation instruction that performs an individual operation on a variable that is not an array variable (does not contain multiple elements). The instruction processing unit 13 can determine whether the instruction to be executed is a vector operation instruction or a scalar operation instruction by information (instruction code) indicating the instruction type included in the instruction to be executed.

In this embodiment, the write operation (store operation) of data to the memory 16 by a scalar operation instruction or a vector operation instruction will be described below.

When the instruction to be executed is a scalar operation instruction (store instruction), the instruction processing unit 13 stores information about the instruction, including data to be written to the memory 16 by the instruction and the write destination address, in the scalar register 132. . The instruction processing unit 13 transmits to the address control unit 14 information instructing to generate a memory access request to be stored in the memory 16 based on the information about the instruction stored in the scalar register 132 .

When the instruction to be executed is a vector operation instruction (vector store instruction), the instruction processing unit 13 transfers the vector store instruction to the vector control unit 12 to obtain vector data to be written to the memory 16 by the vector store instruction. Alternatively, the vector control unit 12 is instructed to generate. The instruction processing unit 13 transmits to the address control unit 14 information instructing to generate a memory access request for storing the vector data in the memory 16 . Note that the vector control unit 12 transmits the vector data to the address control unit 14 through processing described later.

The vector control unit 12 includes a vector calculator 121 and a vector register 122 . The vector control unit 12 acquires or generates vector data to be written to the memory 16 according to the vector store instruction transferred from the instruction processing unit 13 and stores the vector data in the vector register 122 . The vector calculator 121 has a function of executing vector calculation using vector data stored in the vector register 122 . The vector control unit 12 transmits vector data stored in the vector register 122 to the address control unit 14 .

The address control unit 14 generates a memory access request for writing data to the memory 16 based on the information received from the instruction processing unit 13 as described above. When the instruction to be executed is a store instruction, the address control unit 14 receives write data for the memory 16 from the instruction processing unit 13. When the instruction to be executed is a vector store instruction, the address control unit 14 receives write data for the memory 16 as a vector. Received from the control unit 12 . The address control unit 14 transmits the generated memory access request to the memory access control unit 15 .

The memory access control unit 15 transmits memory access requests received from the address control unit 14 to four access ports in the memory 16 having four memory modules 161 to 164 . The number of memory modules and access ports provided in the memory 16 is not limited to four. Memory 16 may comprise other than four memory modules and access ports.

The memory access control unit 15 has a routing control unit 150 and memory controllers 151 to 154 . The memory controllers 151 to 154 are communicably connected to the memory modules 161 to 164 via four access ports of the memory 16 . Details of the routing control unit 150 and the memory controllers 151 to 154 will be described later.

Next, the operation of the vector processing device 10 according to this embodiment to initialize the array variables stored in the memory 16 will be described.

The determination unit 131 in the instruction processing unit 13 determines whether or not the instruction fetched by the instruction processing unit 13 is an initialization instruction for array variables stored in the memory 16 . However, in the program executed by the vector processing unit 10 according to this embodiment, the initialization instruction for the array variable sets a predetermined initial value (for example, "0") to all the elements included in the array variable. shall be represented by a vector store instruction that

For example, when the fetched instruction indicates that the values to be written to all the elements included in the array variable are "0", the determination unit 131 determines that the instruction is an initialization instruction for the array variable. do. Alternatively, for example, when the instruction type indicated by the fetched instruction indicates an initialization instruction for array variables, the determination unit 131 may determine that the instruction is an initialization instruction for array variables. However, in this case, it is assumed that information (instruction code) representing an instruction type capable of identifying an initialization instruction for an array variable is defined in the instruction system.

When the determination unit 131 determines that the fetched instruction is an initialization instruction for an array variable, the instruction processing unit 13 determines to process the instruction as a scalar operation instruction instead of a vector operation instruction. That is, the instruction processing unit 13 converts the initialization instruction from a vector operation instruction to a scalar operation instruction.

The instruction processing unit 13 stores information about the initialization instruction including the initial value “0” to be used in the scalar register 132 . However, the information about the initialization instruction includes, for example, the base address (head address) for initialization in the memory 16 and the number of elements of the array variables to be initialized. The instruction processing unit 13 transmits information regarding the initialization instruction including the initial value “0” stored in the scalar register 132 to the address control unit 14 .

The address control unit 14 generates a memory access request for accessing the four access ports in the memory 16 based on the information regarding the initialization command received from the command processing unit 13 . At this time, the address control unit 14, for example, while changing the address of the access destination for each operation cycle of the vector processing unit 10, sends a memory access request for accessing the memory 16 by the address of the access destination, Generate continuously. That is, access to the memory 16 by an initialization instruction converted into a scalar operation instruction is the same as access to the memory 16 by an initialization instruction executed as a vector operation instruction.

The address control unit 14 transmits the generated memory access request for each access port to the memory access control unit 15 .

FIG. 2 is a diagram exemplifying the range of addresses accessed by the vector processing device 10 according to the present embodiment to the memory module 161 when initializing the array variables stored in the memory 16. As shown in FIG. In FIG. 2, one rectangle represents an 8-byte memory area representing one element of an array variable. The upper value in each rectangle represents the address in the entire memory 16 and the lower value in each rectangle represents the local address in the memory module 161 .

In the example shown in FIG. 2, for example, addresses "0" to "127" in the memory 16 are assigned to the memory module 161, addresses "128" to "255" in the memory 16 are assigned to the memory module 162, and Addresses “256” to “383” are assigned to memory module 163 , and addresses “384” to “511” in memory 16 are assigned to memory module 164 . Addresses after address "512" in the memory 16 are also assigned to the memory modules 161 to 164 according to the same rule.

In FIG. 2, shaded rectangles represent memory areas where initialization takes place. That is, in the example shown in FIG. 2, the vector processing unit 10 initializes 128 elements from the first element whose address is "64" in the memory module 161. In the example shown in FIG. Since the vector processing unit 10 similarly initializes the elements of the array variables stored in the memory modules 162 to 164, the total number of elements of the array variables to be initialized in this case is 512. .

In the case of the example shown in FIG. 2, the address control unit 14 assigns addresses "64" to "4159" in the memory 16 to the access port to the memory module 161 (that is, local addresses "64" to "1087" in the memory module 161). ) to write '0'. When the unit of access to the memory module 161 according to this embodiment is, for example, 128 bytes (that is, the memory area indicated by the rectangle for one row in FIG. 2), the address control unit 14 changes the shaded rectangle to One memory access request is generated for the memory area for nine rows including The address control unit 14 similarly generates memory access requests for access ports to the memory modules 162 to 164 .

The memory access control unit 15 receives from the address control unit 14 memory access requests for access ports to the memory modules 161 to 164 generated by the address control unit 14 . A routing control unit 150 in the memory access control unit 15 inputs a memory access request for an access port to the memory module 161 to the memory controller 151 . The routing control unit 150 sequentially inputs memory access requests for access ports to the memory modules 162 to 164 to the memory controllers 152 to 154 .

The memory controller 151 stores the memory access request for the access port to the memory module 161 input from the routing control unit 150 in a buffer (not shown) provided in the memory controller 151 . After that, the memory controller 151 transmits the memory access request to the memory module 161 . When the unit of access to the memory module 161 according to the present embodiment is, for example, 128 bytes as described above, the memory controller 151, with one memory access request, reads nine rows including the shaded rectangle in FIG. memory access to the memory area of Thereby, the memory controller 151 initializes the elements of the array variables stored in the memory module 161 .

Similarly, the memory controllers 152 to 154 store memory access requests for access ports to the memory modules 162 to 164 input from the routing control unit 150 in buffers (not shown) provided in the memory controllers 152 to 154 . After that, the memory controllers 152 to 154 send the memory access requests to the memory modules 162 to 164 in order. As a result, the memory controllers 152-154 initialize the elements of the array variables stored in the memory modules 162-164.

Next, with reference to the flowchart of FIG. 3, the operation (processing) of initializing the array variables by the vector processing device 10 according to the present embodiment will be described in detail.

The determination unit 131 in the instruction processing unit 13 determines whether or not the fetched instruction is an initialization instruction for array variables stored in the memory 16 (step S101). If the fetched instruction is not an initialization instruction for an array variable (No in step S102), the entire process ends.

If the fetched instruction is an initialization instruction for an array variable (Yes in step S102), the instruction processing unit 13 converts the initialization instruction from a vector operation instruction to a scalar operation instruction, and converts the initialization instruction including the initial value "0". Information about the initialization instruction is stored in the scalar register 132 (step S103). The instruction processing unit 13 transmits information regarding the initialization instruction including the initial value "0" to the address control unit 14 (step S104).

The address control unit 14 generates a memory access request for accessing four access ports in the memory 16 based on the information regarding the initialization instruction received from the instruction processing unit 13, and generates a memory access request for each of the generated access ports. is sent to the memory access control unit 15 (step S105).

The memory access control unit 15 initializes array variables stored in the memory 16 by transmitting memory access requests for each access port received from the address control unit 14 to the memory modules 161 to 164 in the memory 16 ( Step S106), the whole process ends.

The vector arithmetic processing device 10 according to the present embodiment can execute processing for initializing array variables at high speed. The reason for this is that the vector operation processing unit 10 converts an initialization instruction for initializing an array variable into a scalar operation instruction that accesses memory in the same manner as a vector operation instruction without using a vector operation instruction. because it is executed by

The effects realized by the vector arithmetic processing device 10 according to this embodiment will be described in detail below.

2. Description of the Related Art A vector operation processor capable of executing vector operations generally initializes array variables by issuing a vector store instruction and writing predetermined initial values to the array variables. Initialization of array variables is usually performed intensively when software execution is started. When executing vector arithmetic instructions, a certain amount of overhead is usually generated. Therefore, when executing software that uses a large number of large-scale array variables, the vector store instruction that initializes the array variables must be executed by the arithmetic core. may stay inside. In this case, the subsequent vector operation instruction is not executed and stays in the operation core, resulting in a problem of performance degradation.

In order to solve such problems, the vector operation processing device 10 according to the present embodiment includes a vector control unit 12, a determination unit 131, and an execution unit (instruction processing unit 13 and address control unit 14). It operates as described above with reference to FIGS. That is, the vector control unit 12 controls execution of operations on array variables stored in the memory 16 by vector operation instructions. The determination unit 131 determines whether the instruction to be executed is an initialization instruction for initializing the array variable. Then, the execution unit executes the initialization instruction by converting it into a scalar operation instruction that accesses the memory 16 in the same manner as the vector operation instruction without using the vector operation instruction.

4A and 4B are diagrams illustrating time charts of initialization processing of array variables by the vector processing device 10 according to the present embodiment. Also, FIGS. 4A and 4B show the time chart and the vector processing device 10 similar to a general vector processing device in order to clarify the effects achieved by the vector processing device 10 according to the present embodiment. shows the result of comparison with the time chart of initialization processing when array variables are initialized using vector operation instructions. The horizontal axis in the time charts shown in FIGS. 4A and 4B represents the elapsed time from the start of execution of the initialization instruction by the operation cycle T of the vector processing unit 10. FIG. However, the operating cycle T is, for example, a clock period during which the vector arithmetic processing unit 10 operates.

When the vector operation processing unit 10 initializes an array variable using a vector operation instruction (vector store instruction) like a general vector operation processing unit, as shown in FIGS. 4A and 4B, the instruction processing unit 13 A process of transferring an initialization instruction to the vector control unit 12 occurs. In this case, in addition, processing by the vector processing unit 12 to expand the initial value “0” to the vector register 122 and processing to transmit the vector store data expanded in the vector register 122 to the address control unit 14 also occur. .

When the vector operation processing unit 10 initializes the array variables stored in the memory 16 using the vector operation instruction, as shown in FIGS. Complete initialization.

On the other hand, when the vector arithmetic processing unit 10 initializes the array variables stored in the memory 16 using a scalar arithmetic instruction, as shown in FIGS. After 18T, the initialization of array variables is completed. That is, the vector processing device 10 according to the present embodiment initializes the array variables 10T earlier than the case where the array variables are initialized using vector processing instructions as in a general vector processing device. can be completed.

The reason why the vector operation processing device 10 according to the present embodiment can complete the initialization of the array variables earlier than when the array variables are initialized using vector operation instructions is as follows. In other words, in the execution of a certain program, the result of an operation on an array variable generally has a different value for each element. Therefore, in order to store the operation result in memory at high speed, a vector register storing a different value for each element is used. It is necessary to perform vector arithmetic processing (vector store) using the provided vector control unit. However, in that case, as described above, overhead (processing for transferring data, processing for developing data in a vector register, etc.) associated with performing vector arithmetic processing using the vector control unit occurs.

The vector operation processing device 10 according to the present embodiment has a configuration focused on the characteristic that when an array variable is initialized, the values (initial values) to be written to the array variables are all the same value (for example, "0"). In addition, without using the vector control unit 12, memory access requests for writing the same values to the elements of array variables all at once are continuously issued by scalar operation instructions. That is, the vector processing unit 10 initializes array variables by successively accessing the memory 16 in the same manner as accessing the memory 16 by a vector store instruction without generating the overhead described above. As a result, the vector operation processing device 10 according to the present embodiment can execute processing for initializing array variables at high speed.

In addition, the memory access according to the present embodiment by a store instruction that writes the initial value "0" to the memory area in which the array variables are stored all at once is a vector store instruction that writes the initial value "0" for each element of the array variables. It is possible to reduce the number of memory access requests sent from the arithmetic core 11 to the memory access control unit 15, compared to the memory access by . As a result, the vector processing device 10 according to the present embodiment can suppress the occurrence of congestion related to memory access requests in the memory access control unit 15, so that the process of initializing array variables can be executed at high speed. can. In addition, in the memory access control unit 15, the effect of suppressing the occurrence of memory access request congestion can be expected to increase as the number of operation cores 11 included in the vector operation processing device 10 increases.

Further, since the vector arithmetic processing device 10 according to the present embodiment does not add functions specific to the present embodiment with respect to the memory 16, existing products such as general-purpose products can be used. That is, the vector arithmetic processing device 10 according to the present embodiment can realize a configuration for executing the processing for initializing the array variables described above at high speed at low cost <Second Embodiment>
FIG. 5 is a block diagram showing the configuration of the vector arithmetic processing device 20 according to the second embodiment of the present invention.

A vector arithmetic processing device 20 according to this embodiment includes a vector control unit 21 , a determination unit 22 , and an execution unit 23 .

The vector control unit 21 controls execution of operations on array variables 240 stored in the memory 24 by vector operation instructions 210 .

The determination unit 22 determines whether the instruction 200 to be executed is the initialization instruction 220 for initializing the array variable 240 .

The execution unit 23 executes the initialization instruction 220 by converting it into a scalar operation instruction 230 that accesses the memory 24 in the same manner as the vector operation instruction 210 without using the vector operation instruction 210 .

The vector arithmetic processing device 20 according to this embodiment can execute processing for initializing array variables at high speed. The reason for this is that the vector operation processing unit 20 uses the initialization instruction 220 for initializing the array variable 240 without using the vector operation instruction 210 and accessing the memory 24 in the same manner as the vector operation instruction 210. This is because it is executed by converting it into an instruction 230 .

<Hardware configuration example>
Each unit in the vector arithmetic processing device shown in FIGS. 1 and 5 in each of the above-described embodiments can be realized by a dedicated HW (Hardware) (electronic circuit). In addition, in FIGS. 1 and 5, at least the following configuration can be regarded as a functional (processing) unit (software module) of the software program.
vector control units 12 and 21,
- Instruction processing unit 13,
- Determining units 131 and 22,
- Address control unit 14,
・execution unit 23,
• Memory access control unit 15 .

However, the division of each part shown in these drawings is a configuration for convenience of explanation, and various configurations can be assumed upon implementation. An example of the hardware environment in this case will be described with reference to FIG.

FIG. 6 is a diagram illustrating the configuration of an information processing device 900 (computer) capable of executing the vector arithmetic processing device according to each embodiment of the present invention. That is, FIG. 6 shows the configuration of a computer (information processing device) capable of realizing the vector arithmetic processing device shown in FIGS. represents

The information processing apparatus 900 shown in FIG. 6 has the following components as components.
CPU (Central_Processing_Unit) 901,
ROM (Read_Only_Memory) 902,
RAM (Random_Access_Memory) 903,
- Hard disk (storage device) 904,
a communication interface 905;
- Bus 906 (communication line),
A reader/writer 908 capable of reading and writing data stored in a recording medium 907 such as a CD-ROM (Compact_Disc_Read_Only_Memory);
- An input/output interface 909 such as a monitor, a speaker, and a keyboard.

That is, the information processing apparatus 900 having the above components is a general computer in which these components are connected via a bus 906 . The information processing apparatus 900 may include a plurality of CPUs 901 or may include CPUs 901 configured by multi-cores.

The present invention, which has been described with the above-described embodiment as an example, supplies a computer program capable of realizing the following functions to the information processing apparatus 900 shown in FIG. The function is the above-described configuration in the block configuration diagrams (FIGS. 1 and 5) referred to in the description of the embodiment, or the function of the flowchart (FIG. 3). The present invention is then achieved by having the computer program read out by the CPU 901 of the hardware, interpreted and executed. Further, the computer program supplied to the apparatus may be stored in a readable/writable volatile memory (RAM 903) or a nonvolatile storage device such as ROM 902 or hard disk 904.

Also, in the above case, a general procedure can be employed at present as a method of supplying the computer program into the hardware. The procedure includes, for example, a method of installing in the device via various recording media 907 such as a CD-ROM, and a method of downloading from the outside via a communication line such as the Internet. In such a case, the present invention can be considered to be constituted by the code that constitutes the computer program or the recording medium 907 that stores the code.

The present invention has been described above using the above-described embodiments as exemplary examples. However, the present invention is not limited to the embodiments described above. That is, within the scope of the present invention, various aspects that can be understood by those skilled in the art can be applied to the present invention.

REFERENCE SIGNS LIST 10 vector arithmetic processing unit 11 arithmetic core 12 vector control unit 121 vector arithmetic unit 122 vector register 13 instruction processing unit 131 determination unit 132 scalar register 14 address control unit 15 memory access control unit 150 routing control unit 151 to 154 memory controller 16 memory 161 to 164 memory module 20 vector operation processing unit 200 instruction to be executed 21 vector control unit 210 vector operation instruction 22 determination unit 220 initialization instruction 23 execution unit 230 scalar operation instruction 24 memory 240 array variable 900 information processing device 901 CPU
902 ROMs
903 RAM
904 hard disk (storage device)
905 communication interface 906 bus 907 recording medium 908 reader/writer 909 input/output interface

Claims (10)

vector control means for controlling execution of operations on array variables stored in memory by vector operation instructions;
determining means for determining whether an instruction to be executed is an initialization instruction for initializing the array variable;
execution means for executing the initialization instruction by converting it into a scalar operation instruction that accesses the memory in the same manner as the vector operation instruction without using the vector operation instruction;
A vector processing unit comprising The execution means converts the initialization instruction into a scalar operation instruction that accesses the memory while changing an access destination address for each operation cycle of the device itself.
2. The vector arithmetic processing device according to claim 1. The execution means includes a scalar register for storing write data to the memory by the scalar operation instruction, and stores the write data indicated by the initialization instruction in the scalar register.
3. The vector arithmetic processing device according to claim 1 or 2. the execution means converts the initialization instruction into the scalar operation instruction including an access instruction for a plurality of access ports provided in the memory;
4. The vector arithmetic processing device according to any one of claims 1 to 3. further comprising memory access control means for executing the initialization instruction converted into the scalar operation instruction by accessing a plurality of access ports provided in the memory;
5. The vector arithmetic processing device according to claim 4. The determination means determines that the instruction to be executed is the initialization instruction when a value written to an element included in the array variable is a predetermined value in the instruction to be executed.
The vector arithmetic processing device according to any one of claims 1 to 5. The determining means determines whether or not the instruction type indicated by the instruction to be executed indicates the initialization instruction.
The vector arithmetic processing device according to any one of claims 1 to 5. further comprising the memory;
The vector arithmetic processing device according to any one of claims 1 to 6. With the vector arithmetic processing unit,
controlling execution of operations on array variables stored in memory by vector operation instructions;
determining whether the instruction to be executed is an initialization instruction for initializing the array variable;
executing the initialization instruction by converting it into a scalar operation instruction that accesses the memory in the same manner as the vector operation instruction without using the vector operation instruction;
Array variable initialization method by vector arithmetic processing unit. Vector control processing for controlling execution of operations on array variables stored in memory by vector operation instructions;
Determination processing for determining whether an instruction to be executed is an initialization instruction for initializing the array variable;
execution processing executed by converting the initialization instruction into a scalar operation instruction that accesses the memory in the same manner as the vector operation instruction without using the vector operation instruction;
Array variable initialization program by the vector processing unit for causing the vector processing unit to execute

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