JP2002297378A - Signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the description of an instruction for designating the prescribed start address of a memory accessing a program at the time of repetitively performing the program including the instruction for accessing the memory from the prescribed start address, to avoid the repetitive performance of the instruction and to reduce the processing quantity of the program. SOLUTION: A signal processor (25) is provided with the memory (19) and it repetitively performs the program. The processor is provided with a storage means (23) storing the memory address for accessing the memory (19). When the memory access instruction for accessing the memory (19) from the prescribed start address is included in the program which is repetitively performed, the start address is stored in the storage means (23), and access to the memory (19) corresponding to the address stored in the storage means (23) is realized whenever the program is repetitively performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device such as a microcomputer, a microprocessor, and a digital signal processor, and more particularly to a signal processing device having a loop control mechanism for controlling repetitive execution of a plurality of instructions.

[0002]

2. Description of the Related Art FIG. 4 shows the configuration of a digital signal processor (hereinafter referred to as a DSP) as a conventional signal processing device.

In FIG. 4, (31) is a configuration of a DSP having a loop control mechanism, (12) is a program memory, (13) is an instruction register IR for storing an instruction output from the program memory, and (14)
Is a decoder that decodes the instruction output from the instruction register IR (13), (19) is a data memory, (15) is an arithmetic unit that performs arithmetic operation, logical operation, and the like.
(16) is a pointer a0 for storing the address of the data memory to be accessed, (17) and (18) are a register ax and a register r0h, respectively,
This is a general-purpose register for storing the output from 5) or the output from the data memory (19).

[0004] (30) is a loop control mechanism having the following configuration.

[0005] (3) is a register LCR (5) described later.
Subtractor "SUB" for subtracting "1" from the output from (4)
Is a zero determination circuit ZERO that determines whether the output of the subtractor SUB (3) is zero.
A register LCR for storing the output of (3) is a register LER for storing a repetition end address of a program for performing repetitive execution, and (7) is an adder A to be described later.
A comparator COMP for comparing the output from the DD (9) with the output from the register LER (6), (8) is a register LSR for storing a repetition start address of a program for executing repetition, and (9) An adder ADD (10) that adds "1" to an output from a program counter PC (11), which will be described later, and outputs the result, outputs from the comparator COMP (7) and from the zero determination circuit ZERO (4). A selector SEL2 that selects an output from the register LSR (8) or an output from the adder ADD (9) according to the output.
(11) is a pointer that points to a program area stored in the memory in advance, and is a program counter PC that stores an output from the selector SEL2 (10).

In the loop control mechanism (30), when a loop instruction for repeatedly executing a program is executed,
Number of repetitions, register LER in register LCR (5)
(6) Repeat end address, register LSR (8)
Stores the repetition start address.

Every time the program is repeatedly executed, the number of repetitions stored in the register LCR (5) becomes:
"1" is subtracted by the subtractor SUB (3), and the result is stored again in the register LCR (5).

In the zero determination circuit ZERO (4), it is determined whether or not the result of the subtraction by the subtractor SUB (3) is "0". If the result is "0", "1" is replaced by "0". , "0" is output and input to the selector SEL2 (10).

On the other hand, during the execution of the program, the program counter PC (11) is incremented by the adder ADD (9) and stored again in the PC (11) via the selector SEL2 (10). Also, every time the program counter PC (11) is incremented, the register LER is set in the comparator COMP (7).
It is compared with the loop end address stored in (6), and if the comparison result matches, “1” is output; otherwise, “0” is output and input to the selector SEL2 (10). You.

In the selector SEL2 (10), the comparator C
The input from the OMP (7) is "1" and the zero determination circuit ZE
When the input from RO (4) is "0", register LSR
(8) is output, otherwise the result of the adder ADD (9) is output.

The program counter PC (11) matches the loop end address and the number of repetitions is "0".
At this time, the repetitive execution of the above program ends.

Here, the program to be repeatedly executed includes an instruction to access the memory from a predetermined start address. When the program is executed a plurality of times, the memory to be accessed is included in the program to be repeatedly executed. Must be described. Therefore, the instruction specifying the start address is also executed by the number of repetitions.

FIG. 5 shows a description example of a conventional DSP when a program including an instruction for accessing a memory from a predetermined start address is repeatedly executed. In FIG. 5, the instruction “lp 10 END;” is a loop instruction. When this instruction is executed, the instruction “a0 = 8000;” is used as the repetition start address, and the instruction “ax = ax−r0h * r0h; Are stored in the register LSR (8), the register LER (9), and the register LCR (5), respectively, and the instruction “a0 = 800” is stored.
0; ”to the instruction“ ax = ax−r0h * r0h; ”are repeatedly executed ten times, of which the instruction“ a0 = 8000; ”is stored in the pointer a0 (16) of the data memory to be accessed. This is an instruction to store the address "8000" which is the access start address, and this instruction is also repeatedly executed ten times.

[0014]

As described above, the instruction "a
0 = 8000; ", an instruction that stores only the same value in the pointer a0 is executed by the number of repetitions.
This has led to an increase in the processing amount of the program, and has a disadvantage of causing a reduction in the processing speed.

The present invention has been made in order to solve such inconvenience, and avoids the description of an instruction designating a predetermined start address of a memory to be accessed at each repetition, and furthermore, the repetition of the instruction. The purpose is to avoid execution and reduce the amount of processing of the program.

[0016]

The signal processing device of the present invention comprises:
A signal processing device including a memory and capable of repeatedly executing a program, including a storage unit that stores a memory address for accessing the memory. In the present invention, when a memory access instruction for accessing a memory from a predetermined start address is included in a program to be repeatedly executed, the start address is stored in the storage unit, and each time the program is repeatedly executed. , Enabling access to a memory corresponding to the address stored in the storage means.

[0017]

FIG. 1 shows a configuration of a DSP as a signal processing device according to one embodiment of the present invention. 4, the same components as those shown in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted.

In FIG. 1, (25) shows the configuration of the DSP according to the present embodiment having a loop control mechanism.

(24) shows the DSP according to the present embodiment.
This is the configuration of the loop control mechanism, which will be described in detail below.

(20) is a register ASR for storing a start address of a memory accessed by a repeatedly executed program, and (21) is a pointer A0 (2) to be described later.
An adder / subtractor ADSB that performs addition / subtraction of an integer value with respect to the output value from 3). The selectors SEL3 and (23) for selecting an output from (21) or an output from a pointer P0 (23), which will be described later, are memory pointers P0 in a repeatedly executed program.
Store the output from (22).

Next, the operation of the loop control mechanism used in the present invention will be described with reference to the flowchart of FIG.

First, in step S11, a loop instruction for controlling the repetitive execution of the program is executed, and the number of repetitions is stored in the register LCR (5) and the register LER (6).
To the register LSR (8), the register ASR (20), and the pointer P0 (23) to store the start address of the memory accessed by the repeatedly executed program.

In step S12, the program counter PC (11) is incremented by the adder (9) and stored again in the program counter (PC) via the selector SEL2 (10).

In step S13, the instruction stored in the memory area pointed to by the PC (11) is executed. If the instruction to be executed is an instruction for accessing a memory area, the pointer P
It is possible to access the memory area pointed to by 0 (23).

The pointer P0 (23) can add / subtract the integer value specified by the adder / subtracter (21) and store it again in the pointer P0 (23).

In step S14, the value of the program counter PC (11) is compared with the value of the register LER (6) by the comparator COMP (7). If they match, the process proceeds to step S15.

In step S15, the register LCR (5) in which the number of repetitions is stored is decremented.
Proceed to 6.

In S16, the zero determination circuit ZERO (4)
In, it is determined whether or not the result of the subtraction by the subtractor SUB (3) is zero.
To repeat the execution. If not zero, the process proceeds to step S17.

At step S17, the loop start address is set in the selector SEL2 (1) from the register LSR (8).
0) is input to the program counter PC (11).

In step S18, the register ASR (2
0), the start address of the memory accessed by the memory access instruction in the program is determined by the selector SEL3 (2
After 2), it is stored in the pointer P0 (23), and is repeatedly executed again from step S12.

Next, FIG. 3 shows an example of program description in the DSP of the embodiment of the present invention.

In FIG. 3, the instruction "lp 10 800
0 END ”is a description format of a loop instruction in the DSP. When this is executed, the first time the instruction“ r0h = [p0 ++]; ”as the repetition start address and the instruction“ ax = ax− ”as the repetition end address r
0h * r0h; ”and the number of repetitions“ 10 ”are stored in the register LSR (8), the register LER (6), and the register LCR (5), respectively.
Further, the start address “8000 address” of the memory accessed by the repeatedly executed program is stored in the register A
It is stored in the SR (20) and the pointer P0 (23).

As a result, the first instruction “r0h =
[P0 ++]; ”, the instruction“ ax = ax−r0h * r
0h; "are repeated 10 times.

The first instruction “r0h = [p0 +
+]; ”, The initial value of the pointer p0 (23) of the data memory to be accessed uses“ 8000 ”stored in the ASR (20), and the adder / subtracter ADSB (21)
Is incremented by the pointer p0 (2
3) stores “8001” and the register r0h (1
8) stores the value stored at address 8000 of the data memory (19), and the second instruction “r0h =
[P0 ++]; ", the value of the pointer p0 (23) of the data memory to be accessed is added to the adder / subtractor ADSB (2
The value is incremented by 1), and the pointer p0
“8002” is stored in (23), and the register r0h is stored.
(18) stores the value stored at the address 8001 in the data memory (19).

The instruction "r0h = [p0--];" causes the pointer p0 (2
The value of 3) is decremented by the adder / subtractor ADSB (21), and “800” is added to the pointer p0 (23).
1 "is stored, and the value stored at address 8002 of the data memory (19) is stored in the register r0h (18).

Further, from the end address of the repetition (the address of the instruction “ax = ax−r0h * r0h;”),
Start address of repetition (first instruction "r0h =
When returning to [p0 ++]; address), “8000” stored in the register ASR (20) is stored again in the pointer p0 (23).

Therefore, in a repeatedly executed program, a memory access from a predetermined start address and an instruction "r0h = [p0 +
+]; ”Or the instruction“ r0h = [p0−−]; ”, the address of the data memory to be accessed is incremented.
Alternatively, since it can be decremented and pointed to the next address, the processing amount of the program can be reduced.

[0038]

According to the signal processing device of the present invention, when a program to be repeatedly executed includes a memory access instruction for accessing a memory from a predetermined start address, the start address of the memory to be accessed is included in the program. Since there is no need to write an instruction for designating and repeatedly executing the instruction, it is effective to improve the processing speed by reducing the processing amount of the program.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a signal processing device including a loop control mechanism according to the present invention.

FIG. 2 is a flowchart at the time of executing a loop instruction by a signal processing device having a loop control mechanism according to the present invention.

FIG. 3 is a program description example for repeatedly executing a program including an instruction to access a memory from a predetermined start address in a signal processing device including a loop control mechanism according to the present invention, and a description thereof.

FIG. 4 is a configuration diagram of a signal processing device provided with a conventional loop control mechanism.

FIG. 5 is a program description example for repeatedly executing a program including an instruction for accessing a memory from a predetermined start address in a signal processing device having a conventional loop control mechanism, and a description thereof.

[Explanation of symbols]

 24 loop control mechanism 25 signal processing device

Claims (1)

[Claims] 1. A signal processing apparatus comprising a memory and capable of repeatedly executing a program, comprising a storage means for storing a memory address for accessing the memory, wherein a predetermined start is included in the repeatedly executed program. When a memory access instruction for accessing a memory from an address is included, the start address is stored in the storage unit, and each time the program is repeatedly executed, the start address is stored in the memory corresponding to the address stored in the storage unit. A signal processing device comprising a loop control mechanism, which enables access.