JPH05181667A - Microprogram control part - Google Patents

Abstract

PURPOSE:To reduce a step and accelerate a processing speed by suppressing a microinstruction excepting for the next. microprogram extracting operation without any branch during microprogram execution. CONSTITUTION:When a microinstruction A not to execute any branching operation is executed, first of all, the branching microinstruction signal of the microinstruction A is outputted from a branch register 4 to a next address generation circuit 6, command control circuit 7 and microinstruction execution suppress circuit 8. The next address generation circuit 6 generates an address according to the branching microinstruction signal. The command control circuit 7 decodes the microinstruction A judges suppressing conditions or the like and outputs the result to the next address generation circuit 6, etc., as various condition signals 10. When the branching microinstruction signal of the microinstruction A and the various condition signals 10 are inputted to the microinstruction execution suppress circuit 8, the microinstruction execution suppressing signal 9 is outputted, in this step, the microinstruction execution excepting for the next microprogram extracting operation can be suppressed.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a microprogram controller.

[0002]

2. Description of the Related Art A conventional microprogram control unit includes a control memory storing a microprogram, a microinstruction word register capable of storing the microprogram extracted from the control memory for each function, and a hardware for decoding the microinstruction. And a next address generation circuit for generating an address of the next microprogram.

In such a microprogram control unit, the microprogram fetched from the control memory in order to execute a software instruction or the like is stored in the microinstruction word register. The micro instruction stored in the micro instruction word register is decoded by the command control circuit,
It outputs a control signal to the hardware to control the hardware operation. Also, an address is generated to retrieve the microprogram to be executed next from the control memory. Therefore, the next address generation circuit generates the address of the next microprogram according to each control signal based on the value of the address register.

Furthermore, by performing the branch operation, it is possible to suppress microinstructions other than the branch operation. To this end, whether the branch condition is "Yes" or "No" is designated by a microinstruction instructing a branch operation. If the branch result matches the branch condition, the microinstruction operation other than the branch operation in the same step is suppressed.

FIG. 3 is a flow chart for specifically explaining the two operations of the conventional example. In FIG. 3A, the inhibition command is executed in the process B after the process A is executed.
"Yes" or "No" is designated as the branch condition, and when the branch condition result and the condition designation match, the process B is not performed and the process proceeds to the next process C. In other cases, the process B is performed and then the process C is performed. Further, in FIG. 3-2, although not related to the inhibition operation, after execution of the process A, the condition is judged in the process B, and the process is branched only to the process D or the process C and the process D. ..

[0006]

In the above-described conventional microprogram control unit, since the branch is always involved, the branch must be branched even when the branch is not required, and therefore unnecessary steps may increase. Had a problem that performance could not be improved.

[0007]

A microinstruction control unit of the present invention includes a microprogram execution inhibiting circuit capable of inhibiting a microinstruction other than the next microprogram fetch operation depending on conditions such as a flag register, a flag register condition designation and It is characterized by having a microinstruction that can inhibit execution of a microinstruction other than the next microprogram fetch operation by designating a deterrent condition.

[0008]

The present invention will be described below with reference to the drawings.

FIG. 1 shows a microprogram controller according to an embodiment of the present invention.

In this embodiment, first, the software instruction stored in the software instruction word register 1 causes
The start address of the microprogram stored in the control memory 2 is designated. Then, the read first microprogram is stored in the microinstruction word register 3.

The microinstruction word register 3 is a group of a plurality of registers and is classified by performance. The branch microinstruction controlling the branching operation and fetching of the next microprogram is stored in the branch register 4 of the microinstruction word register 3, and the branch microinstruction is used for designating a branch condition or fetching the next microprogram. It has the function of address generation. In the present embodiment, the description will focus on the branch control of the microprogram.

The branch micro instruction signal 5 is output to the next address generation circuit 6, the command control circuit 7 and the micro instruction execution inhibiting circuit 8. In addition, various condition signals 10 and an address register 12 storing the address of the micro program being executed are input to the next address generation circuit 6. The next address generation circuit 6 generates an address for fetching the next microprogram from the control memory 2 by the branch microinstruction signal 5, various condition signals 10, each data of the software instruction word register 1 and the address register 12, and controls and stores it. 2 and address register 1
Output to 2. Then, the microprogram corresponding to this address is output from the control memory 2.

The microprogram is executed in the above cycle. The command control circuit 7 controls the operation of other micro instructions in addition to the condition determination of the branch micro instruction. The microinstruction execution inhibiting circuit 8 outputs a microinstruction execution inhibiting signal 9 according to the branch microinstruction signal 5 and various condition signals 10. The microinstruction execution inhibition signal 9 is a signal that can inhibit a microinstruction other than the next microprogram fetch operation.

A micro instruction A is set as a micro instruction capable of controlling the micro instruction execution inhibiting circuit 8. The microinstruction A is a branch microinstruction that can specify a deterrent condition and does not perform a branch operation.

The circuit configuration as described above and the operation according to the micro instruction A will be described. When the microinstruction A is executed in a certain step during execution of the microprogram, the branch microinstruction signal 5 of the microinstruction A is first sent from the branch register 4 to the next address generation circuit 6, the command control circuit 7, and the microinstruction execution inhibition circuit 8. Is output.

In the next address generation circuit 6, the branch microinstruction signal 5 is used to generate an address, for example, by adding "+1" to the current address. The command control circuit 7 decodes the microinstruction A, determines the inhibition condition, etc., and outputs it as various condition signals 10 to the next address generation circuit or the like.

When the branch microinstruction signal 5 of the microinstruction A and various condition signals 10 are input to the microinstruction execution inhibition circuit 8, the microinstruction execution inhibition signal 9 is output. That is, the microinstruction execution inhibit signal 9 is output when the inhibit condition designated by the microinstruction A and the various condition signals 10 match. By the series of operations described above, it is possible to suppress the execution of microinstructions other than the fetch operation of the next microprogram in the same step without branching.

Next, a more detailed description will be given with reference to FIG.

FIG. 2A is a flowchart of a process corresponding to the process according to the conventional example shown in FIG. First,
After the process A is executed, the process A is executed in the process B to perform a series of operations, and then the process C is performed. In this example, the processing speed does not change, but the number of processes, that is, the amount of microprogram can be reduced. 2-2
3 is a flowchart of a process corresponding to the process according to the conventional example shown in FIG. 3-2, and the same process as in FIG. 3-2 can be executed by three processes. This can not only reduce the number of processes but also increase the processing speed.

[0020]

As described above, the present invention does not branch during execution of a microprogram by a branch microinstruction accompanied by a deterrent condition for operating the microinstruction execution deterrence circuit, and does not perform a next microprogram fetch operation. By suppressing the micro instruction, it is possible to reduce the steps of the micro program and to improve the processing speed.

[Brief description of drawings]

FIG. 1 is a block diagram of a micro program control circuit according to an embodiment of the present invention.

FIG. 2 is a flowchart for two processes according to the present invention.

FIG. 3 is a flowchart of a conventional example for the two processes shown in FIG.

[Explanation of symbols]

 1 software instruction word register 2 control memory 3 micro instruction word register 4 branch register 5 branch micro instruction signal 6 next address generation circuit 7 command control circuit 8 micro instruction execution inhibition circuit 9 micro instruction execution inhibition signal 10 various condition signals 11 next address 12 Address register

Claims (1)

[Claims] 1. A microprogram execution inhibiting circuit capable of inhibiting a microinstruction other than the next microprogram fetching operation depending on conditions such as a flag register, and a microprogram fetching operation other than the next microprogram fetching operation by specifying a flag register condition and a restraint condition. A microprogram controller having a microinstruction capable of suppressing execution of the microinstruction.