JPH05224925A - Instruction prefetching system - Google Patents

Abstract

PURPOSE:To suppress disorder of a pipeline caused by a conditional branch instruction by designating in advance the prefetching direction of a succeeding instruction of the conditional branch instruction by a software instruction. CONSTITUTION:The contents of a read data register 1-3, read out of an instruction cache memory 1-1 are decoded by a decoder 104, and in the case where the contents are an instruction for indicating the prefetching direction of a succeeding instruction of a conditional branch instruction, the indicated direction is held in a branch direction indicating register 1-13. Also, as a result of decoding the contents of the read data register 1-3, in the case where the contents are the conditional branch instruction, with respect to an address set to a read- out address register 1-2 for referring to the instruction cache memory 101 in accordance with a value of the branch direction indicating register 1-13, one of a branch success side or an unsuccess side is selected, and prefetch of the succeeding instruction is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction prefetch system for a preceding control device used in an information processing device.

[0002]

2. Description of the Related Art A conventional instruction prefetching method of this kind stores a branch direction and a branch destination address when a conditional branch instruction is executed and stores the same conditional branch when the conditional branch instruction is taken out. For instructions, a method that fetches subsequent instructions based on the same direction as the previous time or the branch destination address,
Alternatively, there is a method of fetching a subsequent instruction based on either the branch success side or the branch failure side.

[0003]

In the above-mentioned conventional instruction prefetching method, in the case of the method of storing the same branch destination direction or the same branch destination address as the previous one, the amount of hardware to realize becomes enormous. There is a drawback. Moreover, if the fetched conditional branch instruction is not registered in the table that stores the branch destination direction or the branch destination address, the effect is halved.

Further, in the case of the method of prefetching the instruction subsequent to the conditional branch instruction based on the direction of either the branch successful side or the branch unsuccessful side, as a result of executing the conditional branch instruction, the prefetch is performed. There is a drawback in that the performance decreases when a program is executed in many cases in the opposite direction to the above direction.

[0005]

According to the instruction prefetching method of the present invention, when the instruction is prefetched and the fetched instruction is a conditional branch instruction, either the branch success side or the branch unsuccessful side is directed. In the instruction prefetching method in the information processing device that predicts and prefetches the subsequent instruction, a function of instructing the prefetching direction of the instruction subsequent to the conditional branch instruction in the instruction group executed by the information processing device is provided. Having a command that has, and based on the direction previously designated by the command,
It is characterized in that the instruction subsequent to the conditional branch instruction is prefetched.

[0006]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram of an information processing apparatus having a pipeline structure to which the present invention is applied.

In FIG. 2, 2-1 is a preceding control unit, which is composed of an instruction fetch unit 2-2 and an address calculation unit 2-3. The instruction fetch unit 2-2 has an instruction cache memory and supplies it to the address calculation unit 2-3 which fetches an instruction.
The address calculation unit 2-3 calculates the logical address of the operand to fetch the operand.

An address conversion unit 2-4 is supplied with the logical address of the operand obtained by the address calculation unit 2-3 and converts it to an absolute address. The converted absolute address is operand cache 2
If the instruction fetched by the instruction fetch unit 2-2 is a branch instruction, it is fed to the instruction fetch unit 2-2 as a branch destination address.

The operand cache 2-5 indexes the operand cache based on the absolute address of the operand obtained by the address translation unit 2-4 and fetches the operand.

Reference numeral 2-6 is an operation execution unit, which receives operands from the operand cache 2-5 and executes the operation. When the instruction to be executed is a conditional branch instruction, branch determination information is sent to the instruction fetch unit 2-2.

FIG. 1 is a detailed block diagram of the instruction fetch unit 2-2 shown in FIG. 2, showing an embodiment of the present invention.

In FIG. 1, reference numeral 1-1 is an instruction cache memory in which an instruction is stored, which is indexed by the output of the read address register 1-2, the output of which is stored in the read data register 1-3. It is supplied to the address calculation unit 2-3. The address calculation unit 2-3 of FIG. 2 is stored in the read data register 1-3.
Is supplied to. The decoder 1-4 stores an instruction stored in the read data register 1-3 as an unconditional branch instruction, a conditional branch instruction, or an instruction indicating a prefetch direction of an instruction subsequent to the conditional branch instruction or a decode instruction. If the instruction indicates the prefetch direction of the instruction subsequent to the conditional branch instruction, the value of the designated direction is set in the register 1-13. Further, as a result of decoding, the subsequent instruction fetch operation differs as described below depending on whether the instruction stored in the read data register 1-3 is an unconditional branch instruction, a conditional branch instruction, or neither of them. ..

When the result of decoding is neither an unconditional branch instruction nor a conditional branch instruction, the value of the read address register 1-2 is incremented by +1 by the adder 1-5 as an input of the read address register 1-2. The added value is selected by the selector 1-6, and subsequent instructions are sequentially fetched. At this time, the selection signal 1-7 of the selector 1-6 is generated by the logic circuit 1-8.

Next, if the instruction is an unconditional branch instruction,
A decode signal 1-9 indicating that is input to the logic circuit 1-8, and the selector 1-6 selects the branch address destination signal 1-10 from the address conversion unit 2-4 so that the selection signal 1- 7 is generated and until the absolute address of the branch destination of the unconditional branch instruction is obtained by the address calculation unit 2-3 and the address conversion unit 2-4 in FIG.
After waiting, the subsequent instruction is fetched.

Finally, the case of a conditional branch instruction will be described.

When the instruction stored in the read data register 1-3 is a conditional branch instruction by the decoder 1-4, a decode signal 1-11 indicating that is applied to one input of the AND gate 1-12. To be done. AND gate 1-
The other input of 12 is connected to the branch direction instruction register 1-13.
Is applied and the logical product of these is input to the logic circuit 1-8.

Here, the value of the branch direction instruction register 1-13 means "1" to preempt the branch successful side and "0" to preempt the branch unsuccessful side. Therefore, if the value of the branch direction instruction register 1-13 is "0", the AND gate 1-1
The output of 2 becomes "0" regardless of the value of the decode signal 1-11, and the selection signal 1-7 generated by the logic circuit 1-8.
Thus, the output of the adder 1-5 is selected as the input of the selector 1-6, and the subsequent instructions are sequentially prefetched in the same manner as in the case of neither the unconditional branch instruction nor the conditional branch instruction.

When the value of the branch direction instruction register 1-13 is "1", the decode signal 1-11 is "1".
If so, the output of the AND gate 1-12 becomes "1", and the branch destination address signal 1 from the address conversion unit 2-4 is input as the input of the selector 1-6 by the selection signal 1-7 generated by the logic circuit 1-8. When -10 is selected, as in the case of the unconditional instruction, the address translation unit 2-4 waits until the absolute address of the branch destination is obtained, and then the subsequent instruction is prefetched.

When the instruction subsequent to the conditional branch instruction is prefetched as described above, the address in the direction opposite to the predicted direction, that is, when the branch successful side is predicted, the branch unsuccessful side is detected. When the branch unsuccessful side is predicted, the address of the branch successful side is selected by the output result of the AND gate 1-12 in the selector 1-14, buffered in the buffer 1-15, and the predicted direction Buffer in buffer 2-15.

The information necessary for the branch judgment of the conditional branch instruction is the branch judgment information signal 1-from the operation execution unit 2-6 when the conditional branch instruction is executed by the operation execution unit 2-6 of FIG. Instruction fetch unit 2-2 as 16
Sent to the buffer 1-15 and the predicted direction buffered in the buffer 1-15 are compared in the logic circuit 1-8 to make a branch decision. As a result of this branch determination, if the predicted direction and the actual branch direction match, the fetching of the subsequent instruction continues as it is, and if they do not match, the fetched instruction in the predicted direction is canceled and the logic circuit is canceled. The buffer 1-15 is input to the selector 1-6 at 1-8.
The select signals 1-7 are generated to select the address on the opposite side of the prediction stored in, and the refetch of the instruction in the correct direction is performed.

As described above, according to the present invention, the prefetch direction of the instruction subsequent to the conditional branch instruction can be specified by the instruction. Therefore, the branch direction statistics of the conditional branch instruction in a certain program can be obtained, or If a branch is successful or unsuccessful, whichever is more frequent, is specified in advance by an instruction to instruct the designated direction when the program is created, the frequency of misprediction is reduced, and the condition of the pipelined information processing device is conditional. It is possible to reduce the disorder of the branch instruction and improve the performance.

[0023]

As described above, according to the present invention, since it is possible to specify the prefetch direction of the instruction subsequent to the conditional branch instruction for each program, the condition can be satisfied even in the information processing apparatus having the pipeline structure. It is possible to reduce the disturbance of the pipeline due to the branch instruction and improve the performance with a very small amount of hardware.

[Brief description of drawings]

FIG. 1 is a block diagram of an instruction fetch unit according to an embodiment of the present invention.

FIG. 2 is an overall block diagram of an information processing apparatus to which the present invention is applied.

[Explanation of symbols]

 1-1 Instruction cache memory 1-2 Read address register 1-3 Read data register 1-4 Decoder 1-5 Adder 1-6 Selector 1-7 Selection signal 1-8 Logic circuit 1-9 Decode signal 1-10 Branch Destination address signal 1-11 Decode signal 1-12 AND gate 1-13 Branch direction instruction register 1-14 Selector 1-15 Buffer 1-16 Branch determination information signal

Claims (1)

[Claims] 1. Information that prefetches an instruction and, when the fetched instruction is a conditional branch instruction, predicts the direction of either the branch successful side or the branch unsuccessful side and prefetches the subsequent instruction. In an instruction prefetching method in a processing device, a group of instructions executed by the information processing device has an instruction having a function of instructing a prefetching direction of an instruction subsequent to the conditional branch instruction, and is preliminarily designated by the instruction. The instruction prefetching method is characterized in that the instruction following the conditional branch instruction is prefetched based on the direction.