JPS6113258B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device controlled by a microprogram, and more particularly to a microprogram control device equipped with a subroutine function.

Generally, in addition to a main routine, this type of information processing device often includes frequently used routines as subroutines in order to reduce the number of steps in a microprogram. When using a subroutine, it is necessary to branch from the main routine to the subroutine using a branch microinstruction, and to save the address to be executed after subroutine processing as the return address from the subroutine.

Conventionally, a method has been adopted in which the address following the aforementioned branch microinstruction (branch microinstruction address +1) is saved in an address saving register as the return address from the subroutine. In this method, when the subroutine processing is completed, a return microinstruction is used to branch to the return address held in the address save register, thereby allowing the processing to proceed to the main routine.

On the other hand, subroutine processing is often repeated many times. When processing the same subroutine repeatedly, the conventional method of holding the address next to the branch microinstruction as the return address does not directly
It is not possible to branch to a subroutine. For this reason, a microinstruction that tests the number of repetitions is provided at the return address, and according to the execution result of this microinstruction, the program branches again to the address of the microinstruction for branching to the subroutine, and then branches to the subroutine again. . Therefore, there is a drawback that the number of steps required per repetition increases, and the larger the number of repetitions, the greater the effect on processing time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprogram control device that can reduce processing time when subroutines are used repeatedly.

In the present invention, when a branch microinstruction in a main routine causes a branch to a subroutine, and the subroutine is repeatedly used two or more times in succession, the address of the branch microinstruction itself is saved in the address save register, and the address of the branch microinstruction itself is saved once. When the subroutine is only used, a microprogram control device is obtained which saves the branch microinstruction plus a certain number of addresses, and changes the return address from the subroutine depending on processing conditions.

According to the present invention, in a microprogram-controlled electronic computer, particularly in a device having a subroutine function, the internal memory of the device can be used to change the return address from a subroutine depending on whether the subroutine is executed repeatedly or only once. means for selecting the address of the branch microinstruction itself or an address plus a certain number depending on the state; address saving means for storing the selected address; and address saving means for storing the address saved in the saving means. At the end of the subroutine, a microprogram control device is obtained which includes means for using as the next microprogram address to be executed in accordance with the designation of the microinstruction.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1, one embodiment of the invention comprises a control memory 1 that stores microprograms including main routines and subroutines. This control memory 1 is a read address that specifies the address of the microinstruction to be read.
Read the microinstruction from the specified address by AD. The read microinstruction is set in the control register 2 according to a microcontroller (not shown), and the operation of each part is controlled by this output. As will be described later, in this embodiment, several registers are provided in addition to the control register 2, and these registers are operated by the clock and set the input state when the clock arrives. Therefore, the state set in a register at one clock will be held until the arrival of the next clock.

Next, in this embodiment, an address register 3 is provided. The contents of the address register 3 are supplied to the control store 1 and the adder 5 as a read address AD via the switching circuit 4, and are also supplied to the switching circuit 7 via the subtracter 6 or directly. The output of this switching circuit 7 is sent to the switching circuit 4 through an address save register 8.

The switching circuit 4 is controlled by a field representing the type of instruction in the control register 2, and has a function of selecting an address to be used as the read address AD. First, when the microinstruction set in the control register 2 is a branch instruction, the switching circuit 4
Select the output of , and send the branch destination address as the read address AD. When the microinstruction is a return instruction, the switching circuit 4 selects the address held in the address save register 8 as the read address AD. At other times,
The contents of the address register 3 are selected by the switching circuit 4, and when the contents of the address register 3 are continuously selected, the previous read address
The address added by "+1" to AD is supplied as the next read address AD.

In the system according to the present invention, as described above,
The address selected by the switching circuit 7 is saved in the address save register 8. Therefore, the address save register 8 holds the contents of the address register 3 or a value obtained by subtracting "-1" from the contents.

The contents of this address save register 8 represent the address to return to at the time of exiting the subroutine.

On the other hand, in order to determine the selection conditions of the switching circuit 7,
In this embodiment, the number of consecutive repetitions of a subroutine is set in a predetermined field of a microinstruction that is processed prior to the subroutine, and the number of repetitions in this field is set in a register 9.
It is configured so that it is set to . The contents of register 9 are subtracted by "-1" in subtracter 10 and then supplied to decoder 11 and register 9. Each time the subroutine process is completed, the register 9 sets the result of subtraction from the subtracter 10 to represent the remaining number of processes. The decoder 11 to which the subtraction result from the subtracter 10 is supplied detects that the subtraction result is "0" and sends a switching signal to the switching circuit 7. When the switching circuit 7 receives a switching signal from the decoder 11, it selects the output of the address register 3, and on the other hand, when the switching signal is not sent, it selects the output of the subtracter 6. Therefore, while the number of times the subroutine is processed does not reach the number specified by the microinstruction, the value obtained by subtracting "-1" from the contents of the address register 3 is saved in the address save register 8, and the number of times the subroutine is processed is specified. When the address register 3 reaches the specified number of times, the contents of the address register 3 are saved to the address save register 8.

Referring to FIG. 2, a microprogram flowchart for explaining the operation of the embodiment of FIG. 1 is shown. In this example, one subroutine from address n to address p is continuously repeated twice. Currently, a microinstruction instructing to branch to address n of the subroutine is partially stored at address m in the main routine. Further, the microinstruction at address m instructs register 9 to set the result of subtraction from subtracter 10. On the other hand, at address m-1, which precedes address m, a microinstruction is stored in register 9 that causes register 9 to set the number of consecutive processes of the subroutine (here, "2"). Also, the subroutine p
The microinstruction at address indicates a return to the main routine.

The operation of the control device according to the present invention will be schematically described with reference to FIG. Main routine processing is m-
When the process has proceeded from address 1 to address m, the branch instruction at address m causes a branch to the start address of the subroutine, that is, address n. When the subroutine is processed from address n to address p, the main routine m
Return to the address again. As a result, the subroutine is processed again from address n to address p, and when this is completed, the process returns to address m+1, and the main routine continues to be processed.

A more detailed explanation will be given below with reference to FIGS. 1 and 2. First, as the main routine progresses and the microinstruction at address m-1 is set in control register 2, m is set in address register 3. In this state,
“2” is written to register 9 by the microinstruction at address m-1 set in control register 2.
is set. Furthermore, since the microinstruction at address m-1 does not have a branch specification, the switching circuit 4 selects the contents of the address register 3 and supplies it to the control store 1 as a read address AD.
Therefore, the microinstruction at address m is read from control store 1 and set in control register 2, and the output of adder 5, that is, m
+1 is set in address register 3.

When the microinstruction at address m is set in the control register 2, the content of the register 9 is "2", so the decoder 11 cannot detect "0" and does not send out a switching signal. Therefore, the switching circuit 7 selects m, which is the value obtained by subtracting "1" from the output of the subtracter 6, that is, the content (m+1) of the address register 3, by the microinstruction at address m. This value m is saved in the address save register 8 via the switching circuit 7. On the other hand, "1", which is the result of subtraction from the subtracter 10, is stored in the register 9.
is set. Furthermore, since the microinstruction at address m specifies a branch to address n, switching circuit 4
selects the address part of control register 2, ie, n.

Therefore, the microinstruction at address n is read out and set in control register 2, and subroutine processing is started from address n. Adder 5 is provided via switching circuit 4. “1” for n
and sets n+1 in address register 3. When the subroutine processing progresses and the microinstruction at address p is set in control register 2, the contents of address save register 8 are output from switching circuit 4 since the microinstruction at address p has a return specification. . In this state, since m is saved in the address save register 8, the branch microinstruction at address m is again read out from the control store 1 and set in the control register 2. As a result, the process returns to the address m that was last executed in the main routine. In this state, the value m+1 obtained by adding "1" to the content m of the address save register 8 is sent to the address register 3 through the adder 5 and set therein.

When the microinstruction at address m is set in control register 2, the program branches again to the starting address n of the subroutine, as in the previous case. In this case, since the contents of the register 9 have already become "1", the deducer 11 detects "0" and sends out a switching signal. The switching circuit 7 selects the content m+1 of the address register 3 in accordance with this switching signal and sets it in the address save register 8. Therefore, the contents of the address save register 8 indicate, prior to the second subroutine processing, the address m+1 of the microinstruction to be executed after the subroutine processing.

When the subroutine processing is performed again and the microinstruction at address p is reached, the switching circuit 4 selects the content m+1 of the address save register 8. Therefore, the microinstruction at address m+1 of the main routine is read from control store 1 and set in control register 2. Thereafter, the main routine processing continues in sequence.

In the embodiment described above, a signal obtained by adding "-1" to the contents of the register 9 and decoding the result is used as a switching signal for the switching circuit 7, and the switching is designated by this switching signal. However, a part of the microinstruction may directly specify switching, or a part of the microinstruction may test the internal state of the device, and depending on the result, specify switching. Furthermore,
If the address after the subroutine processing is an address that has some relation to the address m of the branch instruction, it is the next address m+1 of the branch instruction.
It is clear that this does not have to be the case. For example, the address may be the address of the branch instruction plus a certain number.

As explained above, when saving the return address from a subroutine to the saving means, the present invention saves the address of the branch instruction itself to the subroutine, or saves the next address (address of the branch instruction itself + 1). By configuring the subroutine to be selectable, there is an effect of reducing wasted processing time when the subroutine is continuously and repeatedly used.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is an example of the flow of a microprogram for explaining the operation of the embodiment shown in FIG. 1... Control store, 2... Control register, 3... Address register, 4... Switching circuit, 5... Adder, 6... Subtractor, 7... Switching circuit, 8... Address save register, 9 ...Register, 10...Subtractor, 11...Decoder,
AD...Read address.

Claims (1)

[Claims] 1 Perform a series of processing through predetermined branching microinstructions, and after completing the series of processing,
In a microprogram control device that selects a microprogram address to be executed next, means for monitoring an internal state of the microprogram control device; means for selecting one of certain predetermined addresses; address saving means for saving the selected address while the series of processes is being performed; and address saving means for saving the selected address after the series of processes. and means for using the address saved in the means as the next microprogram address to be executed.