GB2081944A - Microinstruction sequence control - Google Patents

Abstract

A microinstruction sequence control provides control over the sequence of microinstruction operations performed by a digital computer processor. The microinstruction sequence control allows microinstructions to be fetched from a memory at the same time as microinstructions are executed by an arithmetic logic unit. By decoding and fetching an estimated microinstruction 310, the register 222 allows branching to occur in a microinstruction program, wherein the direction of branching is determined by the results of the immediately previous microinstruction. Through the use of a conditioning logic unit 328, subroutine calls involving a microinstruction stack are implemented, and a recovery microinstruction is provided, should the estimated microinstruction prove to be incorrect using control flip-flops 312,314,316 and a recovery translator ROM 336. The incorrectly estimated microinstruction is flushed out using a delayed pop from flip- flop 340. <IMAGE>

Description

SPECIFICATION Microinstruction sequence control This invention relates generally to digital computer processors and relates more particularly to structures for controlling the sequencing and execution of microinstructions by such a processor.

The structure and organization of prior art microprogrammed digital computers is described in Fink, Donald G. (Ed.), Electronics Engineers' Handbook (First Edition, Sections 23-15, 23-105, and 23-106), McGraw Hill: 1975. That handbook describes the use of a microinstruction counter in a digital computer to store the address of the next sequential microinstruction to be executed. The use of a field in a microinstruction to specify the next sequential microinstruction and to provide for branching is also disclosed.

The architecture and organization of prior art microprogrammable digital computer is described in the PDP 11 Processor Handbook, pages 262-275 (Digital Equipment Corpora tion:1979). That handbook discloses a microprogramming method in which each microinstruction specifies the address of the next sequential microinstruction. That handbook also discloses a method wherein each microinstruction can also be used to specify a branch condition to be tested before the next sequential microinstruction is fetched. The result of the branch condition test may be used to cause an alternate microinstruction to be fetched.

A high-speed bit slice microsequencing design in described in "Application Note 217" (National Semiconductor Corporation:May 1979) which was printed in IDM 2900 Family Microprocessor Data Book, pages 198-204 (National Semiconductor Corporation: 1980). That note describes a pipelining prediction mode of executing conditional branches. The conditional branch test is overlapped with the propagation of its statistically most likely outcome. Should the prediction prove to be true, the sequence continues; if false, a "pipeflushing" (NOP) one-cycle time delay is employed, during which the correct control word is allowed to propagate to the microcontrol output.

In the note mentioned above, the term "prediction" refers to selecting and propagating the statistically most likely outcome.

Should this prediction come true, the machins will continue at the unconditional microinstruction speed. If, however, the prediction turns out to be wrong, the predicted microcycle is converted to a NOP while waiting form propagation of the correct conditional outcome. Tiring this waiting period the system will ignore the false microcontrol output word.

In the circuit described, the prediction (and its correction, if necessary) is controlled by a flipflop.

It is therefore an object of this invention to provide a microprogrammable computer processor for operation at a high rate of speed.

Briefly, this invention is a pipelined microprogrammable digital processor utilizing micruinstructions which are encoded with an anticipation of the location of the next sequential microinstruction. This invention functions by executing a conditional branch microinstruction and, simultaneously, fetching and anticipated microinstruction specified by that same conditional branch microinstruction. The results of the execution of the conditional branch microinstruction are used to determine whether to execute the estimated microinstruction. The results are also used to decide whether to fetch a recovery microinstruction, whether to execute that microinstruction, and which of the microinstructions, anticipated or recovery, to use for sequence control. If the anticipated microinstruction is not to be executed, the recovery microinstruction must be fetched.Thus, this invention permits conditional branching wherein the direction of branching is based upon the execution of the immediately previous microinstruction. This invention also provides a delayed pop feature to control a microinstruction stack.

If the anticipated microinstruction is a microinstruction subroutine call, the conditional branch microinstruction is used by this invention to prepare the stack for a subroutine call.

The delayed pop feature allows this invention to undo the preparations made for a subroutine call if the execution results of the conditional branch microinstruction indicate that the anticipated microinstruction is not to be executed.

It is a feature of the present processor that branching occurs in a microinstruction sequence at a conditional branch microinstruction, wherein the direction of branching is determined by the results of the execution of the microinstruction immediately previous in the sequence.

Another feature of the present processor is that a fetch cycle occurs at the same time as an execute cycle.

Another feature of the present processor is that it can execute conditional branch microinstructions and has an anticipated address and a recovery address encoded therein, and that it can operate in a pipelined fashion, and can execute either microinstruction or both microinstructions associateo with and anticipated and recovery addresses, and can base sequence control on either the microinstruction association with the anticipated address or the mirminstruction associated with the recovery address.

A further feature of embodiments in accordance with this invention resides in the provision of a stack as in the prior ert for implementing microinstruction sub-routines, and for utilizing microinstructions in which sub-routine calls may be encoded, wherein a return address is pushed on the stack if either of two branches of a microinstruction is a sub-routine call, and wherein a delayed pop is performed on the stack if a microinstruction branch which is not a sub-routine call is selected.

The invention is described further hereinafter, by way of example, with reference to the accompanying drawings, wherein like reference characters refer to the same or similar parts throughout the several views, and wherein: Figure 1 is a block diagram showing the organization of a prior art microprogrammed digital computer; Figure 2 is a block diagram of the structure of a prior art microprogrammed computer processor; Figure 3 is a block diagram showing the structure of a portion of a sequence control for a prior art microprogrammed digital computer processor; Figure 4 is a block diagram showing the structure of a portion of a prior art microprogrammed digital computer processor; Figure 5 is a block diagram of a portion of the sequence control of a microprogrammed digital computer processor in accordance with this invention;; Figure 6 is a table disclosing the functions performed by the normal conditional sequence operations implemented by the sequence control of this invention; and Figure 7 is a block diagram disclosing the structure of a portion of the sequence control of this invention.

This invention concerns a structure and method of implementing a computer program by providing hardware and a method for operating the hardware so that a sequence of microinstructions is executed in the correct order. This invention is not concerned with the computer program itself, algorithms implemented by the program instructions, or mathematics of the individual instructions or sequence of instructions.

Fig. 1 shows a standard prior art computer organization which forms a basic skeleton for all microprogrammed computer systems, and provides a background for understanding the invention. In such systems, an arithmetic logic unit 10, sequence control 12, and control store 14 form the principal elements of a central processing unit 16, which is connected to a memory 18 and an input/output device 20. A computer program, incorporating a series of macroinstructions in machine language, is stored in the memory 18. These macroinstructions are accessed, one at a time, by the arithmetic logic unit 10 to provide the software including the macrosequence control, for the CPU 16.As each of the macroinstructions is accessed by the ALU 10, the sequence control 12, using a portion or field of the macroinstructions word to define an entry address, accesses a series of microinstructions starting at the entry address in the microprogram store 14. These microinstructions are used to implement the macroinstruction algorithmetically. The microinstructions are then implemented by the arithmetic logic unit 10 assisted by memory 18 and by input/output device 20.

In Fig. 2, a portion of the arithmetic logic unit 10 of the prior computers is shown, along with a more detailed representation of the sequence control 12, including its connections to the control store 14. An instruction register 102 within the arithmetic logic unit 10 stores macroinstructions, one at a time, as they are accessed from the memory 18 or l/O 20. All or a part of these macroinstructions are provided to a translator 202 within the sequence control 12 to provide an initial microinstruction address for the control store 14.

This address is fed to the control store 14 through an address multiplexer 204 which provides, at its output, an address for the control store 14 and for an incrementer 206.

The address, provided by the multiplexer 204, may be provided from any one of the plural sources, 6 being shown in Fig. 2. Therefore, when the translator 202 address is to be provided to the control store 14, the multiplexer is addressed by multiplexer addressing logic 208 to interconnect the translator 202 to the control store 14. The output of the multiplexer 204 is also connected to the incrementer 206 to provide an incrementally increasing sequence through the addresses of control store 14. Thus the incrementer 206 will add 1 to the current address and, if the output of the incrementer 206 is selected by the multiplexer 204, the next microinstruction chosen will be the microinstruction stored at the next sequential address within the control store.

Control mode logic 210 controls the loading of a stack 212 from the incrementer 206 and, in addition, controls the loading of a backup register 214 which may buffer a store 14 address for later use. The stack 212 allows sub-routines to be implemented within the microprogram (in control store 14) by "calling" a series of microinstructions and later returning to the original sequence. Thus, the stack 212 will typically be loaded with a return address to be used after the completion of the sub-routine series. The sub-routine series will typically be addressed by a jump address register 216 which provides an additional input to the multiplexer 204. When a series of sub-routines are to be undertaken in the control store 14, in a nested fashion, the return addresses from each nested sub-routine is provided by multiple levels within the stack 212. A stack pointer 220 is controlled by the control mode logic 210 and selects the location for the storage and retrieval of these return addresses. The stack 212 is connected as one of the inputs to the multiplexer 204 for use in determining the "return" address from a sub-routine for the control store 14. A vector logic 218 is connected to the arithmetic logic unit 10 and is used to modify the jump address 216 to provide multiple branch entry points into locations within the control store 14 as a modification to a specific jump address 216. The jump address 216 is also provided to the register 214 and is loaded in that register 214 under the control of the control mode logic 210. Thus, if the multiplexer address logic 208 selects the register 214 as the source of the address for the control store 14, the last address stored in the register 214 will be accessed.

The above description discloses some of the structural and functional attributes of commercially available microprogram controllers such as model numbers Am 2909 or Am 2910 manufactured by Advanced Micro Devices, 901 Thompson Place, Sunnyvale, California 94086, U.S.A. Such a device is included within the preferred embodiment of this invention.

The prior art devices, microinstructions from the control store 14 are accessed, one at a time, by the output of the multiplexer 204 and are placed in a control register 222 for decoding. A portion of the microinstruction contents of register 222 is used to control the multiplexer address logic unit 208, the control mode logic unit 210, and provides a series of ALU controls 104, the jump address register 216, and a myriad of other functions within the sequence control 12 and arithmetic logic unit 10 which do not form an essential part of this invention.

As will be seen from the description which follows, the register 214 and the stack 212 are used for a different function than was typical in prior computers, in the implementation of the present invention.

Additional elements shown in Fig. 2 are a fault detection logic circuit 106, which forms a part of the arithmetic logic unit 10. When the fault detection logic circuit provides an output signal, it forces the output of the multiplexer 204 to a zero value, so that the control store 14 is automatically addressed at its zero position. This is an overriding control for the multiplexer 204 and provides a zero output regardless of the input selection made by the multiplexer address 208 regardless of the inputs on the remaining lines to the multiplexer. In prior devices, it is used as a hard interrupt in the microprogram sequence for use in error detection.

Pipelining is a form of digital computer architecture allowing parallel processing to increase the operating speed of the processor. A pipelined processor such as that shown in the prior art allows one microinstruction to be executed at the same time as another microinstruction is fetched from a control store memory. Processors sequence microinstructions by performing cyclinal, repetitive groups of operations in a sequential manner. Sequence 1 lists a typical prior art microsequence operation which does not involve pipelining.

Sequence 1 Typical Microsequencing consists of the following: 1. Test the result of the previous microinstruction T-1.

2. Select a microinstruction address T based on the test result.

3. Fetch the T microinstruction.

4. Buffer the T microinstruction.

5. Execute the T microinstruction.

1. Test the results of the T microinstruction.

2. Select the next microinstruction address T + 1 using the test result of T.

3. Etc.

In this prior art sequence, Step 1 involves testing the output of any one of several functions within the arithmetic logic unit 10 in a test multiplexer 108. The output of the test multiplexer 108 is used to modify the output of the mux address 208, as controlled by the control register 22 in response to the operation of the arithmetic logic unit 10. Thus, Step 1, in effect, tests the results of a previous sequence step taken by the arithmetic logic unit 10. Step 2 is the operation of the multiplexer 204 in response to this address from the address logic 208 to provide an address to the control store 14.Step 3 involves reading the addressed microinstruction into the control register 222, step 4 is the actual storage of this microinstruction in the control register 222, and step 5 is the use of the buffered microinstruction to control the control mode logic 210, the ALU controls 104, etc. The process is then repeated, again using the output of the test multiplexer 108 which senses the status of the ALU operation which has resulted from a step (or a series of steps) in the ALU 10 under the control of the logic 104 which responds to the word in the control register 222. Thus, at Step 2, the next address is selected, etc.

Various techniques may be used with a non-pipelined prior art processor so that the output of the test multiplexer 108 affects the multiplex address logic 208. Fig. 3 shows one such prior technique. In this technique, the control register 222 contains the entire microinstruction. A portion or field of this microinstruction, shown as 302, provides a first multiplex address for the multiplexer 204. A second portion or field of the microinstruction includes a second multiplexer address 304. It is important to recognize, in this context, that the person who has written the microprogram, is providing two possible multiplex addresses which are to be selected in response to the output of the test multiplexer 108.The output of the test multiplexer 108 will then provide, in the illustration in Fig. 3, an input to a multiplexer 306 which selects one of the two multiplexer addresses 302 and 304 for controlling the multiplexer 204 of Fig. 2. In the non-pipelined version, if the control register 222 of Fig. 3 contains the microinstruction for the step occurring during a time period T, the two multiplexer addresses 302 and 304 will be addresses for the step occurring during a time period T + 1. Time period T - 1 immediately precedes time period T which immediately precedes time period T + 1. For convenience herein, operations occurring during a time period will be called a step and microinstructions which are executed during a time period will be referenced to the time period of execution.One of these two addresses will be selected by the output of the test multiplexer 108 at the completion of the execution of Step T and in response to that execution.

It should be understood that in the normal non-pipeline operation, a selection of a microinstruction address by the multiplexer 204 cannot occur until the previous microinstruction implementation is completed by the arithmetic logic unit 10 to provide the proper output from the test multiplexer 108. Thus, one period is required to fetch a microinstruction. Another whole period is required to execute that microinstruction, so that the next microinstruction address can be determined and the process continued.

Prior computers have attemped to shorted the timing process by permitting one microinstruction to be executed while the next microinstruction is being fetched (i.e., accessed).

Unfortunately, this process does not allow the results of one microinstruction implementation to affect the selection of the next sequential microinstruction; thus, although the execution time is shortened, the decision making time is not shortened. This process is shown by the following cyclinal sequence which lists a prior art pipelined operation.

Sequence 2: FETCH PHASE 1. Test the result of the previous microinstruction T - 1 2. Select the microinstruction address for T 1 3. Fetch the T + 1 microinstruction.

4. Buffer the T + 1 microinstruction.

EXECUTE PHASE 1. Execute the T microinstruction 2. Buffer the results of the T microinstruction.

It should be understood that the two phases (Fetch and Execute) are occurring simultane ously, each requiring one microcycle. The sub-sequence time for the four steps in the fetch phase and the two steps in the execute phase are not necessarily related to one another, except that the four steps in the fetch phase are accomplished within the same time frame as the two steps of the execute phase.

It can be seen that this sequence uses the results of the implementation or execution of microinstruction T - 1 to select microinstruction T + 1. Thus, referring to Fig. 2, the test multiplexer 108 is monitoring the condition of the arithmetic logic unit 10 at the end of the execution of microinstruction T~1 to provide an input to the multiplex address 208 for selection of the microinstruction T + 1. This process occurs during the execution of microinstruction T. Thus there is a leap-frogging effect where each microinstruction's execution can be used in the selection of not the next, but the second succeeding microinstruction.

If Fig. 3 is utilized in such a prior art pipelined computer, and if the microinstruction contained in the control register 222 is the microinstruction which is executed at time T, the multiplexer addresses 302 and 304 will be two possible multiplexer addresses for the microinstruction T + 1. The output of the test multiplexer 108, however, will be the results of the execution of Step T - 1.

Fig. 4 shows a second prior art technique for use in both the non-pipeline and pipeline version in which the microinstruction stored in the control register 222 does not contain two separate multiplexer addresses but rather a single multiplexer address field 308 which is used to supply the most significant bits of the multiplexer address to the multiplexer address logic 208. The least significant bit of this address is supplied by the test multiplexer 108. The output from the multiplexer address logic 208 is then supplied to the multiplexer 204. If the output is the test multiplexer 108 is a zero, this address is provided exclusively by the address field 308. If it is a one, it is the incremented address, that is, one address above the address 308.This technique, shown in Fig. 4, is usable for either nonpipelined or pipelined operation, in a manner similar to that described in reference to Fig. 3.

Fig. 5 is the first figure illustrating the present invention and comprises structures which take the place of the control register 222 and multiplexer addressing logic 208 of the prior art sequence control shown in Fig.

2. In this case, Fig. 5 shows the control register 222 and its control of the multiplexer address logic unit 208 which, in this invention, is a multiplexer itself. The microinstruction includes a normal multiplexer address code field 310 which will be used as the output of the multiplexer 208 unless certain control flip-flops 312, 314 and 316 are set.

In this case, the ilipflop 312 is a NO-OP flipflop, 314 is a stack backup flip-flop and 316 is a Register Backup flip-flop. Under normal mode circumstances, the field 310 within the microinstruction 222 will contain the normal next multiplexer 204 address, assuming that the flip-flops (312, 314 and 316) are all zero.

An OR gate 320 will provide a zero signal on multiplexer control line 322 which will permit the multiplexer address 310 to be output from the multiplexer 208 on line 324. It can thus be seen that the microinstruction program is written by a person who may select, in field 310, his best estimate of the next step in the sequence.

The field 310 also addresses a translator ROM 326 which provides enabling signals to conditioning logic unit 328 (which is also connected to the output of the test multiplexer 108); the conditioning logic unit 328 is used to set the flip-flops 312, 314, and 316 in response to the enabling signals from the ROM 326 and the test multiplexer 108 output. Control word field 310 is provided by the person who has written the program, as his best estimate of the next step. If this estimate is "incorrect", so that it is desired that theestimate microinstruction not be executed, the field 310 (as decoded by the translator ROM 326 and the conditioning logic 328) will provide an output to set the NO-OP flip-flop 312, based on the test multiplexer 108 being true or false, as selected by the programmer.

Similarly, the flip-flops 314 and 316 will be set by the conditioning logic 328 if, as a result of the output of the test multiplexer the sequence requires that the next address of the multiplexer 204 be supplied, not by the code 310, but by the stack 212 or register 214, respectively.

The structure shown in Fig. 5 corresponds to and performs functions analogous with the control register 222 and multiplexer address logic 208 of Fig. 2. In this regard, arithmetic logic unit 10 is a means for executing a selected microinstruction during an execution cycle time period to produce an execution result at the end of the execution time period.

An anticipated address is decoded from field 310 of control register 222 by the multiplexer 208. In the operation of this invention, address multiplexer 204 acts as a means for fetching a microinstruction from the anticipated location defined by the source field 310 which was decoded by multiplexer 208. The fetching occurs during a fetch cycle time period which begins during the execution cycle time period of arithmetic logic unit 10.

Test multiplexer 108 produces a test result which is used to determine whether the anticipated source is correct, that is, whether the anticipated source should be used to obtain the next microinstruction to be executed. The testing is performed by multiplexer 108 by evaluating the result of the execution of the conditional test microinstruction by arithmetic logic unit 10. If the anticipated source is correct, then the NO-OP control fil-flop 312 allows the anticipated microinstruction to be executed by the arithmetic logic unit 10.

Translating ROM 326 and conditioning logic 328 act as a recovery decoding means for decoding a recovery address from the selected microinstruction contents of control register 222. The recovery address is decoded from field 310. The address multiplexer 204 acts as a recovery fetching means for fetching the recovery microinstruction from the recovery location specified by the recovery address decoded by translating ROM 326 and conditioning logic 328. A recovery microinstruction is fetched if any of the control flip-flops 312, 314 or 316 is set by the operation of conditioning logic 328. Note that before such a recovery fetching operation is made, control register 222 will contain the anticipated microinstruction. Thus, the recovery fetch serves to place a recovery microinstruction into control register 222, replacing the anticipated microinstruction.Prior to the time that an anticipated microinstruction is placed in control register 222, control register 222 contains the selected microinstruction from which the sources for the anticipated microinstruction and the recovery microinstruction are decoded. As soon as a recovery microinstruction has been fetched to the control register 222, the recovery microinstruction will be executed.

If the contents of the selected microinstruction in the control register 222 indicates that a sub-routine is to be called by either the estimated microinstruction or the recovery microinstruction, translating ROM 326 acts as a push means for transferring a microprogram sub-routine address to the stack 212. Translating ROM 326 performs such a push function during the execution cycle when the selected microinstruction is being executed by the arithmetic logic unit 10. Flip-flop 340 acts as a delayed pop means to remove the return address from stack 212 which was placed on stack 212 by the translating ROM 326. Flipflop 340 performs this delayed pop function only if the test result provided by test multiplexer 108 indicates that the non-recovery sequence taken calls for a "pop" or that the "push" operation done during the previous cycle was not wanted.

Test mux 108 is monitoring a specifically selected result of the current operation in arithmetic logic unit 10. Conditioning logic 328 uses the output of test mux 108 in conjunction with enabling signals from translating ROM 326 to provide set signals to the recovery flip-flops 313, 314 and 316.

Each flipflop of 312, 314 and 316 may be enabled at each cycle to set on 108 being true, set on 108 being false, set unconditionally, or not set at all.

The enabling signals are ultimately provided from field 310 via translating ROM 326 or if in a recovery sequence, they are provided by recovery translator ROM 336 driven. by the flip-flops.

The operation of the circuit of Fig. 5 will be described in reference to the chart which is identified as Fig. 6. This chart provides, under the heading "Normal Conditional Sequence Operation", the choice of the person who writes the microinstruction program as to the sequence which he wishes to follow. Thus, for example, the third conditional sequence, shown on the chart, is entitled "Next If True/ Jump If False". In the chart of Fig. 6, each of the conditional sequences is described as an operation followed by a slash, with a different operation before the slash.The operation which is described before the slash is the operation which is designated by the field 310 and which is automatically loaded through the multiplexer 208 at the beginning of each microstep to provide, at the output of the multiplexer 208, the most likely next step, that is, the address for the multiplexer 204 which the person who writes the microinstruction program believes will be the proper address for Step T + 1. This address will be supplied to the multiplexer 204 and will actually provide the next address for the control store 14 from one of the inputs to the multiplexer 204. This new microinstruction from the control store 14 will replace the current microinstruction in the control register 222. In the meantime, during this fetching operation, a test is conducted on the current operation to provide an output from the test multiplexer 108.This is a test from the results of Step T.

Taking sequence operation no. 9 of Fig. 6 as an example; the person who writes the microinstruction program when he uses this sequence, will provide that the next microinstruction, in sequence, will be placed into the register 222 automatically. The person who writes the microinstruction program also indicates, through his selection or sequence 9, that this next microinstruction in the store 14 should be used if the output from the test multiplexer 108 is false. If, on the other hand, the output of the multiplexer 108 is true, operation no. 9 specifies that this next microinstruction, which was placed in the register 222, should not be executed (no op), but rather an instruction addressed by the B register 214 should be fetched for execution.This will be accomplished by setting the flip-flops 312 and 316 as shown in Fig. 6, and by using the state of these flip-flops, in combination, to address the multiplexer 204 through the multiplexer 208. Placing the proper address into the multiplexer 204 allows the multiplexer 204 to select the output of the register 214, so that the microinstruction in the control store 14 designated by the register 214 may be accessed and executed.

In this manner, it can be seen that each of the operations designated 1 through 26 in Fig. 6 provides, before the slash, the source of the microinstruction address which will be automatically used to access the next microinstruction from the control store 14. It also provides an indication, true or false, of the output of the test multiplexer 108 which must appear if the fetched microinstruction is to be executed. Thus, through his selection of one of the sequences 1 through 26, the person who writes the microinstruction program not only selects his estimate of the most probable source of the next microinstruction, but also determines the output of the test multiplexer 108, true or false, which will be used to determine if his estimate was correct.

Following the slash, the sequence provides the description of the source of address signals for the control store, which will be used if the output of the test multiplexer 108 does not match that designated. Thus, for example, returning to operation no. 9, if the output of the test multiplexer 108 is true, the microinstruction, which has been fetched, and placed in the control register 222, will not be executed. Rather, the value loaded into the flipflops 312, 314 and 316 (i.e., 101) will be used to designate the address of the multiplexer 204 as a recovery operation to select the alternative next sequence designated by the person who writes the microinstruction program. In operation no. 9, this is a register jump.Thus, for each of the operations 1 through 26, the person who writes the microinstruction program selects (by field 310) a sequence which will be followed if the output of the test multiplexer 108 is as he designates, and a recovery or backup sequence, (provided by flip-flops 312, 314, 316 and controlled by the test mux 108 and by ROM 326 in response to word 310) to be followed if the test output is not as he designates. It should be understood that the test which is used from the multiplexer 108 to determine whether or not the primary or secondary sequence designation should be used, is a test of the current execution. Thus, the execution of microinstruction is used to determine whether the test result from multiplexer 108 is true or false, and whether the estimate for microinstruction T + 1 was correct.

As shown in Fig. 5, the microinstruction word within the register 222 includes a jump field 327 and test field 329. The test field 329 determines what test the arithmetic logic unit 10 will perform, as selected by the test multiplexer 108. The jump field 327 is connected to the jump address register 216 of Fig. 2.

If the primary sequence is used, there is a very substantial time saving in decision making. If the secondary sequence is used, the primary fetched microinstruction is not excecuted and the fetching step must follow the previous execution step, so that the timing is approximately equivalent to that of Sequence 1 above (i.e., not pipelined). So long as the person who writes the microinstruction program can provide, for most microsteps, a correct anticipated output for the test multiplexer 108, very significant time savings can be accomplished in both execution and decision making.In fact, in some of the operations (and specifically operations 5, 6 and 7) there is no penalty under either circumstance, since the next microinstruction is executed, in all cases, and the only thing affected by the output of the test multiplexer 108 is the effect of the sequence control field 310 of that next microinstruction, allowing these operations to have the effect of overriding the sequence control field 310 of the next successive fetched microinstruction.

The chart of Fig. 6 shows, in six columns, a setting of the flip-flops 312, 314, and 316 in response to the output of the translator Read Only Memory 326 and the test multiplexer 108 for each control sequence word 310. As an example, in operation no. 3, if the output of the test multiplexer 108 is true, none of the flip-flops is set, the output of the OR gate 320 will be zero so that the next microinstruction placed in the register 222 will be interpreted in the normal mode, that is, the sequence control field 310 will be supplied at the output of the multiplexer 208. If, on the other hand, the output of the test multiplexer 108, in operation no. 3, is false, Fig. 6 shows that the no-op flip-flop 312 and the "Use Register Address" flip-flop 316 will both be set.Thus, the output of the OR gate 320 will be a one, so that the next microinstruction in the register 222 will not be executed because of the no-op flip-flop. Rather, that output will be provided directly by the flip-flops 312, 314, and 316. In this case, the operation is designated by the column in Fig. 6 designated "Recovery Address" showing that the B register, that is, register 214, is used as the source of the next address for the control store.

A column in Fig. 6 designated "Load Register 214" also bears a check for Step 3. This indicates that, at the time of setting up the flip-flops 312, 314 and 316, the register 214 will also be loaded from the jump address 216 to provide the proper jump location for the next recovery jump. In order for the no-op flip-flop 312 to control the operation and insure that a microinstruction, which has been accessed, is not executed, the no-op flip-flop 312 is connected to a no-op control 330 within the arithmetic logic unit 10 which prevents the status of the internal registers of the CPU 16 from being changed until another microinstruction is executed.

At the top of Fig. 6, the various sequence control functions designated by the field 310 of Fig. 5 are listed. It should be understood that these are the sequence controls selected at the mux 204, which are available if the output of the test multiplexer 108 is as designated in the primary condition of the operation. If the secondary condition is met, that is, the condition following the slash in the description, the only available addresses for the next microinstruction are from the B register 214, the stack 212 or the next or incrementor register 206.

Fig. 7 shows, in more detail, the stack 212 and stack counter or pointer 220 from Fig. 2.

As previously described, the pointer or counter 220 provides the addresses of the stack 212. The input, that is, the data to be written into the stack 212, is provided by the incrementor 206 while the output, that is, the data read from the stack 212, provides one of the multiple inputs to the multiplexer 204. As in the prior art, the stack 212 is a last in, first out memory stack which has been shown schematically in Fig. 7 to have stack locations a through g. The pointer 220 operates normally in a manner such that data from the incrementor is loaded first into position a, then, if the pointer 220 is pushed, that is, incremented, loaded into b, and so on. Push is a term of art which indicates that the pointer 220 is first incremented and then the stack 212 is written into at the incremented location, using data supplied by the incrementor 206.Pop, on the other hand, is a term of art which indicates that, in the reading mode, data is read from the location designated by the pointer 220, in this case, for supplying an input to the multiplexer 204, and the pointer 220 is then decremented.

As shown in Fig. 6, during primary sequence control, as described previously, the translator ROM 326, in response to the sequence control 310, will provide push and pop command signals. As shown in Fig. 5, at 332 and 334, respectively, these signals are used to control the stack counter 220 of Fig.

2. Similarly, during the recovery operation, a recovery translator ROM 336 of Fig. 5 is used to generate pop command signals 334 during certain specified recovery operations, as designated in Fig. 6. This recovery translator ROM 336 also provides a special conditional setting of the NO-OP flip-flop 312 in operation no. 7 of Fig. 6, as shown by recovery control flipflop 338 of Fig. 5.

A push operation is done during primary sequence control, that is, a signal is provided by the translator ROM 326 at 332, when a sub-routine is to be called, that is, at opera tions10, 11, 19, 20 and 22 of Fig. 6. A push control signal is also provided at operation steps 16 and 18 to provide the next address as a recovery address. Thus, when a sub-routine is to be called, the pointer 220 of Fig. 7 is incremented and the next address, taken from the incrementor 206, is loaded into the stack 212. This is done so that this next address can be phased for use at the end of the sub-routine to return to the main microsequence.In the case of operations 16 and 18, this address is saved as a recovery address on the stack in case the output of the test multiplexer determines that a recovery sequence is required, that is, the secondary rather than the primary sequence of operations is required by the output of the test multiplexer.

In a similar manner, at Step 25, a stack pop is designated. In this case, the program sequence is actually doing a sub-routine return, which is accomplished by the first reading out the address previously stored in the stack 212 and then decrementing the pointer 220 to place the stack 212 in the condition that it was in before the sub-routine was begun.

During the recovery operation, a stack pop is provided at Steps 12, 13, 16 to 19, and 22, in those cases where a push has not previously occurred in the primary sequence control at the stack 212 (i.e., at Steps 12, 13 and 18). The pop indicates that the secondary sequence control is a return. In other cases, if a push was undertaken as a part of the primary sequence control, a pop is used in the recovery phase in order to permit the next sequential microinstruction to be accessed in the recovery stage, returning the stack 212 to its initial condition.

It will also be noted in reference to Fig. 6, that operation sequence no. 10 includes a delayed pop if the output of the test multiplexer 108 is true, and operations no. 11 and no. 26 include a delayed stack pop if the result of the test multiplexer 108 is false.

Referring to Fig. 5, the delayed pop is accomplished by a flip-flop 340 which is set by the conditioning logic 328 in accordance with the table of Fig. 6. Once set, this flip-flop will decrement the stack pointer 220 during the next normal microsequence step. An unconditional push is done in the case of operation nos. 10 and 11 in order to save the current return address in case the sub-routine call is required in the recovery phase. The delayed pop is utilized then during normal sequencing to undo that push so that the stack will be in its original state.

The push is unconditional, since it must be down before the incrementor 206 is incremented, that is, at the beginning of the primary phase operation. Thus, if a "call" is needed for either the primary or secondary phase, it must be accomplished in the primary phase and then, in effect, undone, if not needed by a "delayed" pop.

Finally, in Step no. 26, the delayed pop is used to conditionally provide the full return facility required in the primary sequence. It should be noted that if the delayed pop facility is used, the "normal" sequence code following (in time) must not attempt to do a push or a pop operation on the stack.

This completes the detailed description. In summary, what has been accomplished, in effect, is shown in the following pipeline sequence: Fetch Phase 1. Select the microinstruction address for T + 1 using sequence control of T (or recovery sequence controls).

2. Fetch the T+ 1 microinstruction.

3. Buffer the T + 1 microinstruction.

Execute Phase 1. Execute the microinstruction T.

2. Test result of microinstruction F.

3. Buffer the T microinstruction results. Also buffer the test results into special sequence recovery control flip-flops under T microinstruction control.

This sequence shows that the address for T + 1 microinstruction is selected at the time of execution of microinstruction T. This microinstruction is buffered and the test result from microinstruction T is used to determine whether this microinstruction or a recovery microinstruction (to be fetched during a recovery operation) should be used for the succeeding step. Thus, the individual writing the microprogram, in writing each microprogram step, selects both the estimated source of the address for the next sequential microprogram step, and a secondary or recovery source for that microprogram step address. He also selects the criteria to be tested in the arithmetic logic unit to determine which of these two alternative sources will be used for the next microinstruction address source.Thus, the test which is conducted in the arithmetic logic unit during the execution of microinstruction T, is used to determine whether the primary or estimated next microinstruction's address source will be used, so that the sequence of microinstructions can proceed without delay, or whether a recovery operation must be conducted, delaying one microstep for the purpose of accessing a microinstruction using a backup, secondary, or recovery source for the microinstruction address. The person who writes the microinstruction program will thus attempt to anticipate or estimate the most likely results of the test conducted at each microsequence step and utilize this most likely result as a criteria for selecting the primary sequence control. Only in the less likely event that the test result is different from that anticipated, is a recovery operation undertaken. The time lost in the recovery operation is more than made up by the increased efficiency of the system due to the statistical advantage inherent in estimating the likely next sequence (i.e., bring the selection criteria and its result closer together in time).

There is a provision for permitting the unconditional execution of a next microinstruction while still permitting the modification of its microprogram sequence, since the execution is only stopped when a no-op flip-flop 212 is set. This permits the "no wasted cycle" advantage of conventional pipelining in those cases where decisions are more balanced, that is, where the person who writes the microinstruction program cannot anticipate the more likely of two results of the test, but can make the test one step earlier as required by conventional pipelining.

Claims (7)

1. A microprogrammable computer processor having a microinstruction stack, and an arithmetic logic unit for executing a selected microinstruction during an execution cycle time period to produce an execution result at the end of said execution cycle, the processor including a push means for transferring a microprogram subroutine return address to said stack during said execution cycle and a delayed pop means for removing said return address from said stack if said execution result indicates that a microprogram subroutine is not to be called.

2. A microprogrammable computer processor having an arithmetic logic unit with a test multiplexer, a control store, an address multiplexer, a control register, multiplexer address logic to provide an address to said address multiplexer, wherein said multiplexer address logic selects between an anticipated address from said control register and a recovery address, a plurality of control flip-flops to provides a recovery address to said multiplexer address logic, at least one of said control flip-flops being an ALU control flip-flop connected to selectively inhibit the operation of said arithmetic logic unit, an OR gate having inputs connected to the outputs of each of said control flip-flops, and having an output to gate said multiplexer address logic so as to select between said anticipated address and said recovery address and conditioning logic for decoding said recovery address from said control register, and having an input from said test multiplexer, and having an output to transfer said recovery address to said control flip-flops wherein said transfer is conditional on the state of said test multiplexer.

3. A processor as claimed in claim 2 further comprising a translating read only memory interposed between said control register and said conditioning logic for selectively incrementing and decrementing said stack.

4. A processor as claimed in claim 2 further including a recovery translator connected to the outputs of each of said control flip flops and connected to said stack for selectively decrementing said stack.

5. A processor as claimed in claim 4 further including a recovery control flip-flop having inputs connected to each of said test multiplexer and said recovery translator, and having an output connected to selectively inhibit the operation of said arithmetic logic unit.

6. A processor as claimed in claim 2 further including a delayed pop flip-flop having an input connected to said conditioning logic and having an output connected to said stack for selectively decrementing said stack.

7. A microprogrammable computer processor substantially as hereinbefore described with reference to and as illustrated in Figs. 5 to 7 of the accompanying drawings.