JP2005318544A - Cmos image sensor capable of high-speed processing of analog signal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a CMOS image sensor capable of layout of CDS circuit for every 2 pixel pitch while the totally high speed operation of the element is attained even if a relatively low speed system is used. <P>SOLUTION: In a pixel array unit, first, second and third pixels corresponding to a plurality of first, second and third colors respectively are arranged in matrix, and one CDS circuit for every two adjoining rows of the pixel array unit, and a first CDS unit for reciving an output signal of the first pixel corresponding to one of these two rows are provided. A first analog signal processing path on one side of the pixel array unit and one CDS circuit for every two adjoining rows of the pixel array unit are provided, and a second CDS unit for receiving an output signal of the second or third pixel corresponding to one row of these two rows. In addition, a second analog signal processing path at the other side of the pixel array unit is provided. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a CMOS (Complementary Metal Oxide Semiconductor) image sensor, and more particularly to a CMOS image sensor that can process an analog signal at high speed.

  As is well known, an image sensor is a semiconductor element that converts an optical image into an electric signal, and is generally divided into two types: a charge coupled device (hereinafter referred to as “CCD”) and a CMOS image sensor. It is done.

  Among them, the CCD is an element in which individual MOS capacitors are arranged at positions very close to each other, and charge carriers are stored in the capacitors and transferred. In contrast, a CMOS image sensor is an element that employs a method in which a pixel array is formed using a manufacturing technology of a CMOS integrated circuit, and an output is sequentially detected through a switching operation. Since the CMOS image sensor has a great advantage of low power consumption, it is widely used in personal portable systems such as mobile phones.

  FIG. 1 is a diagram showing a configuration for processing image data (analog signal) obtained from a pixel in a CMOS image sensor according to the prior art.

  As shown in FIG. 1, an image sensor according to the prior art has R (red), G (green), and B (blue) pixels in the row direction and N pixels in the column direction (N, M Are arranged in a matrix form to constitute a pixel array unit 11, and a plurality of CDS (Correlated Double Sampling) circuits provided for each column constitute a CDS unit 12, and the pixel array unit 11 is arranged on the lower side. On the right side of the pixel array unit 11, an ASP unit (Analog Signal Processor) 13 for processing an analog signal output from the CDS unit 12 is arranged.

  The CDS circuit samples the reset signal and the data signal from each pixel and outputs them to the analog data bus 15, and the ASP unit 13 performs amplification after obtaining the difference between the reset signal and the data signal. Thereby, pure pixel data that is a substantial image of the subject is obtained.

  When the pixel data is read, the data of all the pixels in a certain row of the pixel array unit 11 are simultaneously transmitted to the corresponding CDS circuits of the CDS unit 12 simultaneously (with the same clock). Are controlled by the column driving unit 14 and sequentially transmitted to the ASP unit 13 via the analog data bus 15 for processing.

  As described above, in a conventional CMOS image sensor, when a certain row is selected, each pixel signal (reset signal and data signal) of that row is stored in the corresponding CDS circuit at the same time, and then the column drive A method is adopted in which the signal of each CDS circuit is transmitted to the ASP unit in order by the unit 14.

  By the way, in the above-described conventional driving method and configuration, when millions of pixels are arrayed, the number of pixels in the row direction increases, and it is necessary to increase the number of CDS circuits by the increased number. Since the number of CDS circuits increased by that amount is commonly connected to one analog data bus 15, the load capacitance of the analog data bus 15 also increases.

  For this reason, it is difficult for a system using a conventional CMOS image sensor to perform high-speed operation. For high-speed operation, it is necessary to improve functional blocks (particularly ASP) so as to have a desired signal processing performance. In addition, when a system that operates at high speed is designed, the time margin for stabilizing the signal value within a predetermined time is reduced, thereby adversely affecting the reliability and mass productivity of the element.

  Further, as shown in FIG. 1, the conventional CMOS image sensor has one CDS circuit for each column, so that the transistors constituting the CDS circuit have a pixel pitch corresponding to the width of one pixel. Need to be laid out inside. However, in the case of an image sensor of several million pixel class, since the pixel size is very small, there arises a problem that it is difficult to lay out the corresponding CDS circuit within the pixel pitch.

  The present invention has been made to solve the above-described problems of the prior art, and is capable of high-speed operation of the entire device even when a relatively low-speed system is used. An object of the present invention is to provide a CMOS image sensor capable of solving the above problem and laying out one CDS circuit per 2 pixel pitch.

  To achieve the above object, a CMOS image sensor according to the present invention includes a plurality of first pixels corresponding to a first color, a plurality of second pixels corresponding to a second color, and a plurality of second pixels corresponding to a third color. A pixel array unit in which three pixels are arranged in a matrix in the row and column directions, and one side of the pixel array unit, which processes an analog signal output from the first pixel in the pixel array unit A first analog signal processing path, and a second analog signal processing disposed on the other side of the pixel array unit for processing an analog signal output from the second pixel or the third pixel in the pixel array unit And the first analog signal processing path has one CDS circuit for every two adjacent columns of the pixel array unit, and among the two columns, A first CDS unit that receives an output signal of the first pixel corresponding to one of the columns; and the second analog signal processing path includes one CDS circuit for every two adjacent columns of the pixel array unit. And a second CDS unit that receives an output signal of the second pixel or the third pixel corresponding to one of the two columns.

  In the present invention, the first analog signal processing path exists in the same row, and one of the two pixels corresponding to two adjacent columns is transmitted to the CDS circuit of the first CDS. The second analog signal processing path further includes second selection means for transmitting the signal of the other pixel of the two pixels to the CDS circuit of the second CDS unit.

  Further, the first analog signal processing path further includes at least one first analog data bus that transmits an output of each CDS circuit of the first CDS unit, and a first ASP connected to the first analog data bus. And the second analog signal processing path includes at least one second analog data bus for transmitting an output of each CDS circuit of the second CDS unit, and a second ASP connected to the second analog data bus. .

  A first column driving unit configured to generate a selection signal for transmitting an output of each CDS circuit of the first CDS unit to the first analog data bus in response to a column address; And a second column driver for generating a selection signal for transmitting an output of each CDS circuit of the second CDS unit to the second analog data bus in response to a column address. Is further provided.

  Preferably, the first, second, and third pixels are a G pixel, an R pixel, and a B pixel, respectively.

  In the present invention, since an analog signal is processed through multiple paths, the signal processing speed can be improved even through a stable signal processing system. In addition, while processing signals through multiple paths, signals of the same type of pixels in the pixel array are processed through the same path, so that the offset between the same types of pixels is minimized. Therefore, the effect that the image quality can be improved is obtained.

  In addition, since one CDS circuit is laid out per two pixel pitches, the effect of solving the CDS circuit layout problem that occurs as the pixel pitch decreases can be obtained.

  Furthermore, since one CDS circuit is laid out per two pixel pitches, the mismatch between the transistors generated due to the small pixel pitch is minimized. Thereby, column FPN (Fixed Pattern Noise) can be suppressed to the maximum. Furthermore, since fewer CDS circuits are used, power consumption can be reduced.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1) First Embodiment FIG. 2 is a diagram showing a configuration of a CMOS image sensor according to a first embodiment of the present invention.

  As shown in FIG. 2, in the image sensor according to the first embodiment of the present invention, in the CDS circuit portion, the path for sampling the signal from the pixel is divided into two as a whole, In this pass, one CDS circuit is laid out per two pixel pitches so that two pixels share one CDS circuit.

  More specifically, the image sensor according to the first embodiment of the present invention has N (R, red), G (green), and B (blue) pixels in the row direction and M (N, M) pixels in the column direction. Are arranged in a matrix form to constitute a pixel array unit 21, and CDS units 22 and 26 each having one CDS circuit for every two adjacent columns are arranged on the lower and upper stages of the pixel array unit 21. It is arranged on each side. A first ASP unit 23 for processing an analog signal output from the lower CDS unit 22 is disposed on the lower right side of the pixel array unit 21, and an upper CDS on the upper right side of the pixel array unit 21. A second ASP unit 27 for processing the analog signal output from the unit 26 is arranged.

  The pixel array unit 21 includes a plurality of odd rows (Odd row) in which G pixels are arranged in the first column, R pixels and G pixels are alternately arranged in the subsequent columns, and B pixels are arranged in the first column. And a plurality of even rows in which G pixels and B pixels are alternately arranged in the subsequent columns.

  Each CDS circuit arranged on each of the upper and lower sides exists in the same row and shares two pixels corresponding to two adjacent columns, but either one of the two adjacent pixels. Is transmitted to the lower CDS circuit, the signal of the other pixel must be output to the upper CDS circuit. Therefore, the output signal of the pixel array unit 21 is selected by the selection units 20A and 20B. To the CDS section.

  In the first embodiment, the selection units 20A and 20B are configured by switches that are driven according to a row selection signal Row_Sel. When an even row (Even row) is selected, the row selection signal Row_Sel is When the level corresponds to the logical value “0” and an odd row is selected, the row selection signal Row_Sel becomes a level corresponding to the logical value “1”. As a result, all G pixel signals in the pixel array section are transmitted to the lower CDS circuit, and B or R pixel signals are transmitted to the upper CDS circuit.

  The selection units 20A and 20B may have any circuit configuration as long as the above-described functions are provided. For example, a plurality of control signals can be used, and a multiplexer or the like can be used instead of the switch.

  A signal output from the lower CDS unit 22 is transmitted to the first ASP unit 23 via the first analog data bus 25, and a signal output from the upper CDS unit 26 passes through the second analog data bus 29. Via the second ASP unit 27.

  Then, the output of each CDS circuit of the lower CDS unit 22 is transmitted to the first analog data bus 25 according to the selection signal CS generated by the first column driving unit 24, and the output of the upper CDS unit 26. The output of each CDS circuit is transmitted to the second analog data bus 29 in accordance with the selection signal CS generated by the second column driver 28.

  Next, an overall operation for reading out pixel data will be described.

  When any row of the pixel array unit 21 is selected, the output signal of the G pixel of the selected row is transmitted to the respective CDS circuits of the CDS unit 22 on the lower side at a time, and B or R of the selected row is selected. The pixel output signal is transmitted to each CDS circuit of the upper CDS unit 26 at a time.

  Next, the first column driving unit 24 sequentially drives each CDS circuit of the lower CDS unit 22 and places the output signal on the first analog data bus 25. These output signals are processed by the first ASP unit 23. The second column drive unit 28 sequentially drives the CDS circuits of the upper CDS unit 26 and places the output signal on the second analog data bus 29. These output signals are processed by the second ASP unit 27.

  As described above, in the first embodiment of the present invention, since the signal of the R pixel or the B pixel and the signal of the G pixel are processed through different paths, two signals are simultaneously transmitted with one clock. Thus, an analog system having twice the bandwidth can be implemented.

  Further, since the ASP is divided into two and the role is halved, each ASP can use a relatively low speed system with a sufficient time margin for stabilizing the data signal at a predetermined time.

  Also, while processing signals through multiple paths, each color signal (ie, R, G, or B signal) is processed in the same ASP path, minimizing the offset problem and 2 pixel pitch One CDS circuit can be laid out per hit. Thereby, there is an advantage that the number of CDS circuits is reduced, the layout margin of the CDS circuit is improved, and the power consumption is reduced.

2) Second Embodiment As described above, in the first embodiment of the present invention, the analog signal processing path is divided into two, and one analog data bus is provided for each analog signal processing path. A CMOS image sensor has been described. On the other hand, the second embodiment relates to a CMOS image sensor when a plurality of analog data buses are provided in each analog signal processing path.

  FIG. 3 is a diagram showing a configuration of a CMOS image sensor according to the second embodiment of the present invention.

  As shown in FIG. 3, the CMOS image sensor according to the second embodiment includes eight analog data buses (BR′_D, BR_D, BR′_C, BR_C, BR′_B, BR_B) on the upper path. , BR′_A, BR_A), and eight analog data buses (G′_A, G_A, G′_B, G_B, G′_C, G_C, G′_D, G_D) are also provided in the lower path. The configurations of the pixel array unit 21 and the selection units 20A and 20B are the same as those in the first embodiment.

  As described above, in the CMOS image sensor according to the second embodiment, by providing a plurality of analog data paths in one analog signal processing path, the load capacitance of the analog data line in each path is greatly reduced. The ASP design burden can be reduced and the signal processing speed can be further improved.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical idea of the present invention, and these also belong to the technical scope of the present invention.

It is a figure which shows the structure of the analog signal processing path of the CMOS image sensor which concerns on a prior art. It is a figure which shows the structure of the analog signal processing path of the CMOS image sensor which concerns on the 1st Embodiment of this invention. It is a figure which shows the structure of the analog signal processing path of the CMOS image sensor which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

11, 21 Pixel array unit 12, 22, 26 CDS unit 13 ASP unit 14 Column driving unit 15 Analog data buses 20A, 20B Selection unit 23 First ASP unit 24 First column driving unit 25 First analog data bus 27 Second ASP unit 28 Second column drive unit 29 Second analog data bus

Claims (9)

A pixel array in which a plurality of first pixels corresponding to the first color, a plurality of second pixels corresponding to the second color, and a plurality of third pixels corresponding to the third color are arranged in a matrix in the row and column directions And
A first analog signal processing path disposed on one side of the pixel array unit to process an analog signal output from the first pixel in the pixel array unit;
A second analog signal processing path disposed on the other side of the pixel array unit and processing an analog signal output from the second pixel or the third pixel in the pixel array unit,
The first analog signal processing path includes one CDS circuit for every two adjacent columns of the pixel array unit, and outputs an output signal of the first pixel corresponding to one of the two columns. A first CDS unit for receiving,
The second analog signal processing path includes one CDS circuit for every two adjacent columns of the pixel array unit, and the second pixel corresponding to any one of the two columns, or the first A CMOS image sensor comprising a second CDS unit that receives an output signal of 3 pixels. The first analog signal processing path exists in the same row, and a first pixel signal is transmitted to the CDS circuit of the first CDS unit from two pixels corresponding to two adjacent columns. Further comprising a selection means,
The second analog signal processing path further comprises second selection means for transmitting a signal of the other pixel of the two pixels to a CDS circuit of the second CDS unit. CMOS image sensor. The first analog signal processing path comprises:
At least one first analog data bus for transmitting an output of each CDS circuit of the first CDS unit;
The CMOS image sensor according to claim 1, further comprising a first ASP connected to the first analog data bus. The second analog signal processing path comprises:
At least one second analog data bus for transmitting the output of each CDS circuit of the second CDS unit;
4. The CMOS image sensor according to claim 1, further comprising a second ASP connected to the second analog data bus. 5. The first analog signal processing path comprises:
4. The apparatus of claim 3, further comprising a first column driver that generates a selection signal for transmitting an output of each CDS circuit of the first CDS unit to the first analog data bus in response to a column address. The described CMOS image sensor. The second analog signal processing path comprises:
5. The apparatus of claim 4, further comprising a second column driver that generates a selection signal for transmitting an output of each CDS circuit of the second CDS unit to the second analog data bus in response to a column address. The described CMOS image sensor. The pixel array portion is
A plurality of even rows in which the third pixel is arranged in a first column and the first pixel and the third pixel are alternately arranged in a subsequent column;
3. The CMOS image of claim 2, comprising a first pixel in a first column and a plurality of odd rows in which the second pixel and the first pixel are alternately arranged in a subsequent column. Sensor.   8. The CMOS image sensor according to claim 7, wherein each of the first selection unit and the second selection unit includes a switching element controlled by a row selection signal having information related to an odd row or an even row.   The CMOS according to any one of claims 1 to 8, wherein the first pixel is a G pixel, the second pixel is an R pixel, and the third pixel is a B pixel. Image sensor.

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