CN1691758B - CMOS image sensor for processing analog signal at high speed - Google Patents

CMOS image sensor for processing analog signal at high speed Download PDF

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CN1691758B
CN1691758B CN2005100598711A CN200510059871A CN1691758B CN 1691758 B CN1691758 B CN 1691758B CN 2005100598711 A CN2005100598711 A CN 2005100598711A CN 200510059871 A CN200510059871 A CN 200510059871A CN 1691758 B CN1691758 B CN 1691758B
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analog signal
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correlated double
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CN1691758A (en
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裵昌民
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MagnaChip Semiconductor Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
    • H04N25/671—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction
    • H04N25/677—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction for reducing the column or line fixed pattern noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

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  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

A CMOS image sensor includes: a pixel array having a plurality of first pixels, a plurality of second pixels and a plurality of third pixels that are arranged in matrix form and respectively correspond to a first color, a second color and a third color. A first analog signal processing path is arranged in one side of the pixel array to process analog signals outputted from the first pixels, and a second analog signal processing path is arranged in the other side of the pixel array to process analog signals outputted from the second pixels or the third pixels. The first analog signal processing path includes a lower CDS part where one CDS circuit per two adjacent columns of the pixel array is provided. The second analog signal processing path includes an upper CDS part where one CDS circuit per two adjacent columns of the pixel array is provided.

Description

The cmos image sensor of processing analog signal at high speed
Technical field
The present invention relates to a kind of cmos image sensor; And, more particularly, relate to a kind of cmos image sensor of Analog signals and signal processing method wherein of being used at full speed.
Background technology
Imageing sensor is in order to optical imagery is changed into the equipment of the signal of telecommunication.This imageing sensor mainly is classified as complementary metal oxide semiconductors (CMOS) (CMOS) imageing sensor and charge-coupled device (CCD).
In the situation of CCD, each mos capacitance device is stored in the capacitor very close to ground setting and electric charge carrier each other and is passed to this capacitor.Simultaneously, in the situation of cmos image sensor, use the CMOS integrated circuit technique to construct pel array and by switching manipulation tested in sequence dateout.Because this cmos image sensor has advantage of low power consumption, it extensively is used in PCS Personal Communications System, in cell-phone.
Fig. 1 is the schematic diagram of conventional cmos image sensor.In Fig. 1, to being illustrated from processing as the view data (analog signal) that is.
With reference to figure 1, this conventional cmos image sensor comprises pel array 11, and wherein red (R), green (G) and blue (B) pixel are set up with M * N matrix form.Correlated-double-sampling (correlateddouble sampling, CDS) part 12 is provided at the downside of pel array 11, and described part comprises the CDS circuit.This CDS circuit is provided at each row.Analogue signal processor (ASP) 13 is provided at the right side of pel array 11 and handles from the analog signal of CDS part 12 outputs.
The CDS circuit is to being applied on the analog data bus from the data-signal of each pixel and reset signal sampling and with the signal of being sampled.Then, ASP 13 calculate between reset signals and the data-signal difference and with its amplification.Therefore, the pure pixel data of practical object can be obtained.
In the process of reads pixel data, the pixel that is provided with along the delegation of pel array 11 is sent to the corresponding CDS circuit of CDS part 12 at once with (at identical clock) simultaneously.Under the control of row driver 14, the output of this CDS circuit sequentially is sent to ASP 13, and is processed therein then.
As mentioned above, according to this conventional cmos image sensor, when delegation was selected, the picture element signal of selected row (reset signal and data-signal) was stored in the corresponding CDS circuit.Then, the signal of corresponding CDS circuit sequentially is sent to ASP by this row driver.
Simultaneously, if millions of pixels is set up, the number of the pixel that then is provided with on line direction increases and therefore the number of CDS circuit must the increase of as much ground.And analog data bus is connected to the CDS circuit of big figure jointly.Like this, the load capacitance of this analog data bus also increases.
Because these reasons, conventional system can not be realized high speed operation.For high speed operation, functional block (particularly ASP) needs to be improved to obtain required signal processing performance.And if High Speed System is designed, the sequential nargin that is used for stabilization signal value in settling time (settling time) is little.Therefore, the reliability of device and productivity ratio are demoted.
In addition, as shown in fig. 1, conventional cmos image sensor comprises a CDS circuit at each row.The transistor that is used for this CDS circuit must be disposed in the pel spacing, and this pel spacing is corresponding to the zone of a pixel.Yet in the situation of the imageing sensor with millions of pixels, Pixel Dimensions is very little.Therefore, the layout of CDS circuit is difficult in the pel spacing.
Summary of the invention
Therefore the purpose of this invention is to provide a kind of cmos image sensor, signal is handled by multipath therein, but chrominance signal (being R, G and B signal) is handled by the path of identical ASP.By this way, offset issue can be minimized and per two pel spacings can be arranged a CDS circuit.Therefore, the layout nargin of CDS circuit can increase and the number of this CDS circuit can reduce.
In one aspect of the invention, provide a kind of cmos image sensor, having comprised: pel array, it has a plurality of first pixels, a plurality of second pixels and a plurality of the 3rd pixel, they are set up and correspond respectively to first look with matrix form, second look and the 3rd look; First analog signal processing path, its side that is set at described pel array is to handle from the analog signal of first pixel output of this pel array; And second analog signal processing path, its opposite side that is set at pel array is to handle from second pixel of this pel array or the analog signal of the 3rd pixel output; Selected cell, be used for analog signal selection be sent to first analog signal processing path and second analog signal processing path; Wherein first analog signal processing path comprises CDS part down, here per two adjacent column of described pel array are provided a CDS circuit, this time CDS partly is configured to receive the output signal corresponding to first pixel of one of described two row, and second analog signal processing path comprises the CDS part, here per two adjacent column of described pel array are provided a CDS circuit, and CDS partly is configured to receive corresponding to second pixel of one of described two row or the output signal of the 3rd pixel on this.
First analog signal processing path further comprises first choice device, its signal that is used for exporting from a pixel of two pixels is sent to described CDS partial C DS circuit down, described two pixels are present on the identical row and corresponding to two adjacent column, and second analog signal processing path further comprises second choice device, and it is used for the signal from one other pixel output is sent to the described CDS partial C DS circuit of going up.
First analog signal processing path further comprises: at least one is analog data bus down, and the described output signal of CDS partial C DS circuit down is loaded thereon; And following ASP, it is connected to this time analog data bus.Second analog signal processing path further comprises: analog data bus at least one, and the described output signal that goes up CDS partial C DS circuit is loaded thereon; And go up ASP, it is connected to analog data bus on this.
First analog signal processing path further comprises first row driver, and it is configured to produce selects signal, is used in response to column address the described output signal of CDS partial C DS circuit down being sent to down analog data bus.Second analog signal processing path further comprises the secondary series driver, and it is configured to produce selects signal, is used in response to column address the described output signal that goes up CDS partial C DS circuit being sent to down analog data bus.
Description of drawings
According to the following description of carrying out in conjunction with the accompanying drawings to preferred embodiment, above and other purpose of the present invention and characteristics will be conspicuous, in the accompanying drawings:
Fig. 1 is the schematic diagram of conventional cmos image sensor, and it shows analog signal processing path;
Fig. 2 is that it shows analog signal processing path according to the schematic diagram of the cmos image sensor of first embodiment of the invention; And
Fig. 3 is that it shows analog signal processing path according to the schematic diagram of the cmos image sensor of second embodiment of the invention.
Embodiment
Below, describe the present invention with reference to the accompanying drawings.
First embodiment
Fig. 2 is the schematic diagram according to the cmos image sensor of first embodiment of the invention.In the CDS circuit, be used for the path from the signal sampling of pixel is divided into two.In each path, two shared CDS circuit of pixel and per two pel spacings are arranged a CDS circuit.
With reference to figure 2, this cmos image sensor comprises pel array 21, and wherein red (R), green (G) and blue (B) pixel are set up with M * N matrix form.Comprise that the CDS part 22 and 26 of CDS circuit is provided at the downside and the upside of pel array 21 respectively.In each of CDS part 22 and 26, per two pixels of two adjacent column are provided a CDS circuit.The one ASP 23 is provided at the right side of pel array 21 with the analog signal of processing from following CDS part 22 outputs, and the 2nd ASP 27 is provided at the right side of pel array 21 to handle from the analog signal of last CDS part 26 outputs.
Pel array 21 comprises a plurality of even number lines and a plurality of odd-numbered line.In odd-numbered line, the G pixel is set in first row, and G pixel and R pixel are arranged alternately.In even number line, the B pixel is set in first row, and B pixel and G pixel are arranged alternately.
Be set at that described upside and the CDS circuit in the downside are shared to be present in the identical row and corresponding to two pixels of two adjacent column.If the picture element signal from a pixel in two neighbors is sent to down the CDS circuit, then the picture element signal from one other pixel must be output to the CDS circuit.For this reason, the output signal of pel array is sent to the CDS part by selecting part 20a and 20b.
In the present embodiment, select part 20a and 20b to be configured with switch, this switching response is driven in row selection signal row_sel.When even number line was selected, row selection signal row_sel was a logical zero.On the contrary, if row selection signal row_sel is that odd-numbered line is selected so for logical one.Therefore, the signal of the G pixel in the pel array all is sent to down the CDS circuit, and the signal of B or R pixel all is sent to the CDS circuit.
Select part 20a and 20b to dispose in every way.For example, but a plurality of control signal can be used and multiplexer place of switches and being used.
The output signal of following CDS part 22 is sent to an ASP23 by first analog data bus 25, and upward the output signal of CDS part 26 is sent to the 2nd ASP 27 by second analog data bus 29.
In response to the selection signal CS that produces from first row driver 24, the output of the CDS circuit of following CDS part 22 is applied on first analog data bus 25, and upward the output of the CDS circuit of CDS part 26 is applied in from the selection signal CS of secondary series driver 28 generations.
The complete operation of reads pixel data will be described below.If the delegation of pel array 21 is selected, then the output signal of the G pixel of selected row is sent to down the CDS circuit of CDS part 22 at once, and the output signal of the B of selected row or R pixel is sent to the CDS circuit of CDS part 26.
Then, first row driver 24 drives the CDS circuit of CDS part 22 down in turn, thereby output signal is loaded on first analog data bus 25.These signals are handled by an ASP 23.In addition, secondary series driver 28 drives the CDS circuit of CDS part 26 in turn, thereby output signal is loaded on this second analog data bus 29.These signals are handled by the 2nd ASP27.
In the present embodiment, because R and the signal of B pixel and the signal of G pixel is handled by different paths, two signals can be processed at a clock in the identical time.Therefore, can implement to have the analogue system of twice bandwidth.
In addition, because two ASP are provided, their task is reduced half.Therefore, the enough idling slow speed systems of this ASP up time nargin.
In addition, though signal is to handle by multipath, chrominance signal (being R, G and B signal) is to handle by the path of identical ASP.By this way, offset issue can be minimized and per two pel spacings can be arranged a CDS circuit.Therefore, the layout nargin of CDS circuit can increase and the number of CDS circuit can reduce, thereby has reduced power consumption.
Second embodiment
Fig. 3 is the schematic diagram according to the cmos image sensor of second embodiment of the invention.In this embodiment, eight analog data bus are applied to upper and lower path respectively.Pel array 21 and the structure of selecting part 20a and 20b are identical with among first embodiment those.
The load capacitance of the analog data line in each path is lowered manyly, reduces the design burden of this ASP thus and improves conversion speed.
According to the present invention, analog passband signal is crossed multipath and is handled, thereby has improved conversion speed by stable signal processing system.In addition, though signal is to handle by multipath, the signal of the same pixel of pel array is to handle by same paths.By this way, the deviation between the same pixel can be minimized and can improve image quality thus.In addition, because per two pel spacings are arranged a CDS circuit, because the Layout Problem of the CDS circuit that the small pixel spacing causes can be solved.
In addition, the mismatch between the transistor also can be minimized.Therefore, fixed pattern noise (FPN) can be suppressed at utmost.Because the CDS circuit of smallest number is used, power consumption is reduced.
The application comprise about korean patent application No.2004-28746 that submits in Korean Patent office on April 26th, 2004 and on December 30th, 2004 respectively and No.2004-116853 theme, the full content of described patent application is hereby incorporated by.
Though the present invention is described with reference to certain embodiments, to one skilled in the art, it is evident that and to carry out variations and modifications as in the spirit and scope of the present invention that following claim limited.

Claims (9)

1.一种CMOS图像传感器，包括：1. A CMOS image sensor, comprising: 像素阵列，其具有多个第一像素，多个第二像素和多个第三像素，它们以矩阵形式被设置并分别对应于第一色，第二色和第三色；A pixel array, which has a plurality of first pixels, a plurality of second pixels and a plurality of third pixels, which are arranged in a matrix and correspond to the first color, the second color and the third color respectively; 第一模拟信号处理路径，其被设置在所述像素阵列的一侧以处理从该像素阵列的第一像素输出的模拟信号；a first analog signal processing path disposed at one side of the pixel array to process an analog signal output from a first pixel of the pixel array; 第二模拟信号处理路径，其被设置在所述像素阵列的另一侧以处理从该像素阵列的第二像素或第三像素输出的模拟信号；a second analog signal processing path disposed on the other side of the pixel array to process an analog signal output from a second pixel or a third pixel of the pixel array; 该第一模拟信号处理路径包括第一选择装置，用于把模拟信号选择性地传送到第一模拟信号处理路径；The first analog signal processing path includes first selection means for selectively passing an analog signal to the first analog signal processing path; 该第二模拟信号处理路径包括第二选择装置，用于把模拟信号选择性地传送到第二模拟信号处理路径；The second analog signal processing path includes second selection means for selectively passing the analog signal to the second analog signal processing path; 其中第一模拟信号处理路径包括下相关双采样部分，在这里所述像素阵列的每两个相邻列被提供一个相关双采样电路，该下相关双采样部分被配置成接收对应于所述两列之一的第一像素的输出信号，并且第二模拟信号处理路径包括上相关双采样部分，在这里所述像素阵列的每两个相邻列被提供一个相关双采样电路，该上相关双采样部分被配置成接收对应于所述两列之一的第二像素或第三像素的输出信号。Wherein the first analog signal processing path includes a down-correlated double sampling part, where every two adjacent columns of the pixel array are provided with a correlated double-sampling circuit, and the down-correlated double sampling part is configured to receive signals corresponding to the two The output signal of the first pixel of one of the columns, and the second analog signal processing path includes an upper correlated double sampling part, where every two adjacent columns of the pixel array are provided with a correlated double sampling circuit, the upper correlated double sampling circuit The sampling part is configured to receive an output signal of a second pixel or a third pixel corresponding to one of the two columns. 2.如权利要求1所述的CMOS图像传感器，其中，2. The CMOS image sensor as claimed in claim 1, wherein, 所述第一选择装置用于将从两个像素中的一个像素输出的信号传送到下相关双采样部分的相关双采样电路，该两个像素存在于相同的行上并且对应于两个相邻列；所述第二选择装置用于将从另一个像素输出的信号传送到上相关双采样部分的相关双采样电路。The first selection means is for transferring a signal output from one of two pixels, which exist on the same row and correspond to two adjacent column; the second selection means is used to transmit the signal output from another pixel to the correlated double sampling circuit of the upper correlated double sampling part. 3.如权利要求2所述的CMOS图像传感器，其中第一模拟信号处理路径进一步包括：3. The CMOS image sensor as claimed in claim 2, wherein the first analog signal processing path further comprises: 至少一个下模拟数据总线，所述下相关双采样部分的相关双采样电路的输出信号被加载在其上；以及at least one lower analog data bus on which the output signal of the correlated double sampling circuit of the lower correlated double sampling section is loaded; and 下模拟信号处理器，其被连接到该下模拟数据总线。A lower analog signal processor is connected to the lower analog data bus. 4.如权利要求3所述的CMOS图像传感器，其中第二模拟信号处理路径进一步包括：4. The CMOS image sensor as claimed in claim 3, wherein the second analog signal processing path further comprises: 至少一个上模拟数据总线，所述上相关双采样部分的相关双采样电路的输出信号被加载在其上，以及at least one upper analog data bus on which the output signal of the correlated double sampling circuit of the upper correlated double sampling section is loaded, and 上模拟信号处理器，其被连接到该上模拟数据总线。An upper analog signal processor is connected to the upper analog data bus. 5.如权利要求3所述的CMOS图像传感器，其中第一模拟信号处理路径进一步包括第一列驱动器，其被配置成产生选择信号，用于响应于列地址而将下相关双采样部分的相关双采样电路的输出信号传送到下模拟数据总线。5. The CMOS image sensor as claimed in claim 3 , wherein the first analog signal processing path further comprises a first column driver configured to generate a select signal for correlating the correlating portion of the down-correlated double-sampled portion in response to a column address. The output signal of the double sampling circuit is sent to the lower analog data bus. 6.如权利要求4所述的CMOS图像传感器，其中第二模拟信号处理路径进一步包括第二列驱动器，其被配置成产生选择信号，用于响应于列地址而将上相关双采样部分的相关双采样电路的输出信号传送到下模拟数据总线。6. The CMOS image sensor as claimed in claim 4 , wherein the second analog signal processing path further comprises a second column driver configured to generate a selection signal for correlating the correlated double-sampled portion of the up-correlated double-sampled portion in response to the column address The output signal of the double sampling circuit is sent to the lower analog data bus. 7.如权利要求2所述的CMOS图像传感器，其中所述像素阵列包括：7. The CMOS image sensor as claimed in claim 2, wherein said pixel array comprises: 多个偶数行，在这里第三像素被设置在第一列，并且第三像素和第一像素被交替设置；以及a plurality of even rows, where the third pixel is arranged in the first column, and the third pixel and the first pixel are alternately arranged; and 多个奇数行，在这里第一像素被设置在第一列，并且第一像素和第二像素被交替设置。A plurality of odd-numbered rows, where the first pixel is arranged in the first column, and the first pixel and the second pixel are alternately arranged. 8.如权利要求7所述的CMOS图像传感器，其中第一选择装置和第二选择装置被配置成具有开关元件，其由行选择信号控制，该行选择信号具有有关奇数或偶数行的信息。8. The CMOS image sensor according to claim 7, wherein the first selection means and the second selection means are configured with switching elements controlled by a row selection signal having information on odd or even rows. 9.如权利要求8所述的CMOS图像传感器，其中第一像素，第二像素和第三像素分别是G像素，R像素和B像素。9. The CMOS image sensor according to claim 8, wherein the first pixel, the second pixel and the third pixel are G pixels, R pixels and B pixels, respectively.
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