KR102408730B1 - Pixel partitioning method for reducing the number of ADCs in CIS system - Google Patents

Abstract

A pixel partitioning method for reducing the number of ADCs in a CIS system is provided. An image sensor system according to an embodiment of the present invention reads a signal generated from a pixel array in which pixels that convert an incident light amount into an analog electrical signal and pixels arranged in a grid in the pixel array are arranged and converts it into a digital signal, a readout circuit for processing, the readout circuit reads some of the pixel columns constituting the pixel array with a single ADC and converts them into digital signals, and reads the rest of the pixel columns constituting the pixel array with multiple ADCs and converts it to a digital signal. Accordingly, by dividing pixels for some of the columns of the pixel array so that a plurality of ADCs process them together, even when the ADC speed improvement does not reach an integer multiple of the existing speed, the number of ADCs can be reduced by the speed improvement amount do.

Description

Pixel partitioning method for reducing the number of ADCs in CIS system

The present invention relates to a technology related to a CMOS image sensor (CIS) system, and more particularly, to a method of high-speed readout of a pixel array in a high-resolution CIS system.

1 is a structural diagram of a CIS system. As shown, the CIS system includes a pixel array 10 , a column-parallel readout circuit 20 , an amplifier 30 , and an interface (MIPI) 40 . is composed by

Pixels arranged in a grid in the pixel array 10 convert the incident light amount into an analog electric signal. The readout circuit 20 includes ADCs that read analog electrical signals generated from pixels and convert them into digital signals, a Digital Signal Processor (DSP) that performs necessary digital signal processing, and a decoder that performs decoding.

The signal read and processed by the readout circuit 20 is amplified by the amplifier 30 and then outputted to the outside through the interface 40 .

As shown in FIG. 2 , in analog-to-digital converters (ADCs) that convert analog signals generated from pixels in the readout circuit 20 into digital signals, pixels are allocated in units of columns. 2 is a simplified diagram of ADCs included in the pixel array and the readout circuit.

ADC is a device that has a large effect on the area of the CIS system due to its large volume. Therefore, an approach for reducing the area of the CIS system by reducing the number of ADCs is required. Furthermore, this approach should be coupled with recent ADC speed improvements.

The present invention has been devised to solve the above problems, and an object of the present invention is to reduce the number of ADCs in connection with improving the ADC speed, ultimately reducing the area of the CIS system and lowering the manufacturing cost. It is to provide a CIS system that can be processed by sharing the column to be processed.

According to an embodiment of the present invention for achieving the above object, an image sensor system includes: a pixel array in which pixels for converting an incident light amount into an analog electrical signal are arranged; a readout circuit that reads signals generated from pixels arranged in a lattice in a pixel array, converts them into digital signals, and processes them; the readout circuit includes, wherein some of pixel columns constituting the pixel array are converted to a single ADC It is read and converted into a digital signal, and the rest of the pixel columns constituting the pixel array is read by multiple ADCs and converted into a digital signal.

The readout circuit includes: a first ADC for reading m pixel columns and a portion of pixels in a specific pixel column and converting them into a digital signal; and a second ADC that reads the remaining pixels of a specific pixel column and m other pixel columns and converts them into a digital signal, and m may be an integer of 1 or more.

The first ADC and the second ADC may process (m + 0.5)*N or more pixel columns per second, and N may be FPS (Frame Per Second).

Also, in the readout circuit, the first ADC and the second ADC may be sequentially arranged.

The first ADC and the second ADC may be asynchronous Successive Approximation Resister (SAR) ADCs.

The readout circuit includes: a first MUX connecting one of the m pixel columns and the specific pixel column to the first ADC; and a second MUX connecting one of the m different pixel columns and the specific pixel column to the second ADC.

The first MUX performs a switching operation such that one of the m pixel columns is connected to the first ADC when a specific pixel column is connected to the second ADC, and the second MUX is configured such that the specific pixel column is connected to the first ADC. In this case, a switching operation may be performed such that one of m different pixel columns is connected to the second ADC.

The first ADC may be allocated half of the pixels of the specific pixel column, and the second ADC may be allocated the other half of the pixels of the specific pixel column.

The half pixels allocated to the first ADC may be pixels disposed above a specific pixel column, and the other half pixels allocated to the second ADC may be pixels disposed below the specific pixel column.

Meanwhile, according to another embodiment of the present invention, an image sensor readout method includes: reading some of pixel columns constituting a pixel array with a single ADC and converting it into a digital signal; and reading the rest of the pixel columns constituting the pixel array by a multi-ADC and converting it into a digital signal.

Meanwhile, according to another embodiment of the present invention, an image sensor readout circuit includes: ADCs for reading signals generated from pixels arranged in a lattice in a pixel array and converting them into digital signals; a processor for processing digital signals converted by ADCs; A decoder for decoding the signal processed by the processor; including, ADCs, some of the pixel columns constituting the pixel array are read by a single ADC and converted into a digital signal, and the rest of the pixel columns constituting the pixel array are It is read by multiple ADCs and converted into digital signals.

Meanwhile, according to another embodiment of the present invention, an image sensor readout method includes: reading some of pixel columns constituting a pixel array with a single ADC and converting it into a digital signal; reading the rest of the pixel columns constituting the pixel array by a multi-ADC and converting it into a digital signal; Signal processing the digital signal converted by ADCs; and decoding the processed signal.

As described above, according to embodiments of the present invention, by dividing pixels for some of the columns of the pixel array so that a plurality of ADCs process them together, even when the ADC speed improvement does not reach an integer multiple of the existing speed, the speed As the number of ADCs can be reduced by the amount of improvement, the area of the CIS system can be reduced and the manufacturing cost can be lowered.

1 is a structural diagram of a CIS system;
2 is a pixel array readout method;
3 and 4 are diagrams illustrating a column-shared readout scheme;
5 is a view provided for explaining a method of dividing pixels of one column and processing two column-shared ADCs together according to an embodiment of the present invention;
6 is a structural diagram of a synchronous SAR ADC;
7 is a structural diagram of an asynchronous SAR ADC;
8 is a timing diagram of a synchronous SAR ADC, and
9 is a timing diagram of an asynchronous SAR ADC.

Hereinafter, the present invention will be described in more detail with reference to the drawings.

3 illustrates a structure in which ADCs that convert analog signals of pixels into digital signals in a readout circuit are configured in a column-shared manner. In the structure shown in FIG. 3, two pixel columns are allocated to one column-shared ADC.

Since one column-shared ADC has to process two pixel columns, the conversion speed of the column-shared ADC shown in FIG. 3 should be twice that of the ADC shown in FIG. 2 .

4 shows another structure in which ADCs are configured in a column-shared manner in a readout circuit. In the structure shown in Fig. 4, four pixel columns are allocated to one column-shared ADC.

Therefore, since one column-shared ADC has to process four pixel columns, the column-shared ADC shown in FIG. 4 should have twice the conversion speed than the column-shared ADC shown in FIG. The conversion speed should be 4 times faster than the ADC shown.

In this way, when the conversion speed of the ADC is 2 times faster than the conventional conversion speed, the column-shared method is applied as shown in FIG. 3, and when the conversion speed of the ADC is 4 times faster than the conventional conversion speed, as shown in FIG. 4 You can apply the column-shared method as well.

Therefore, if the conversion speed of ADC is 2 times faster than the conventional conversion speed, the area occupied by the ADC in the readout circuit is halved. The area is 1/4.

If the conversion speed of ADC is 3 times faster than the existing conversion speed, configure one column-shared ADC to process 3 pixel columns in the readout circuit, reducing the area occupied by the ADC in the readout circuit by 1/3 can

The problem is that the conversion speed of the ADC does not increase by an integer multiple of the existing conversion speed. In this case, the increase in the conversion speed cannot be reflected in the area reduction.

For example, when the conversion speed of the ADC is 1.5 times faster than the conventional conversion speed, the configuration shown in FIG. 3 cannot be applied, and the configuration shown in FIG. 2 must be applied. Accordingly, the ADC occupies the readout circuit The area is not reduced to 1/1.5 (=2/3).

Similarly, when the conversion speed of the ADC is 2.5 times faster than the conventional conversion speed, the configuration shown in FIG. 4 cannot be applied, and the configuration shown in FIG. 3 must be applied, so the reduction in the area occupied by the ADC in the readout circuit is It will be 1/2, not 1/2.5 (=2/5).

In the embodiment of the present invention, even when the conversion speed of the ADC is improved to the extent that it does not reach an integer multiple of the existing conversion speed, a method for reducing the area of the readout circuit by reducing the number of ADCs in the CIS system is proposed.

Specifically, in the embodiment of the present invention, the column-shared ADCs share the pixel column to be processed, that is, for some columns of the pixel array, pixels constituting the column are divided so that the two column-shared ADCs process it together. .

5 is a diagram provided to explain a method of dividing pixels of one column and processing two column-shared ADCs together according to an embodiment of the present invention.

In the readout circuit according to the embodiment of the present invention, as shown in FIG. 5 , some of the columns 11, 13, 14, and 16 constituting the pixel array are single ADCs 21, 22, 23, 24 is read and converted to a digital signal, but the remaining shared columns 12 and 15 are read by multiple ADCs 21&22,23&24 and converted into a digital signal.

Specifically, the signals of the pixels constituting the column-1 (11) are converted into column-shared ADC-1 (21), and the signals of the pixels constituting the column-3 (13) are converted to the column-shared ADC-2 (22). ), and the signals of pixels constituting column-4 (14) are converted into column-shared ADC-3 (23), and signals of pixels constituting column-6 (16) are converted into column-shared ADC-4 (24).

On the other hand, the signals of the pixels constituting the shared column-2 (12) are divided and converted by the column-shared ADC-1 (21) and the column-shared ADC-2 (22), and constitute the shared column-5 (15). The signal of the pixels to be converted is divided by the column-shared ADC-3 (23) and the column-shared ADC-4 (24).

Meanwhile, the column-shared ADCs 21 , 22 , 23 , and 24 are selectively connected to the columns 11 , 12 , 13 , 14 , 15 and 16 through the MUXs 51 , 52 , 53 , 54 .

Specifically, MUX-1 (51) selectively connects column-shared ADC-1 (21) to column-1 (11) or shared column-2 (12), and MUX-2 (52) is column-shared ADC-2 (22) is selectively connected to shared column-2 (12) or column-3 (13), and MUX-3 (53) connects column-shared ADC-3 (23) to column-4 (14) Or selectively connected to shared column-5 (15), MUX-4 (54) selectively connected column-shared ADC-4 (24) to shared column-5 (15) or column-6 (16) .

The MUXs 51, 52, 53, and 54 are controlled by a controller (not shown), so that two column-shared ADCs are not connected to one column at the same time.

Specifically, when the column-shared ADC-2 (22) is connected to the shared column-2 (12) by the MUX-2 (52), the MUX-1 (51) sets the column-shared ADC-1 (21) to the column. When connected to -1 (11) and column-shared ADC-1 (21) is connected to shared column-2 (12) by MUX-1 (51), MUX-2 (52) is column-shared ADC- Connect 2 (22) to column-3 (13).

In addition, when the column-shared ADC-4 (24) is connected to the shared column-5 (15) by the MUX-4 (54), the MUX-3 (53) converts the column-shared ADC-3 (23) to the column- When connected to 4(14) and column-shared ADC-3(23) is connected to shared column-5(15) by MUX-3(53), MUX-4(54) is column-shared ADC-4 (24) is connected to column-6 (16).

On the other hand, column-shared ADC-1,3 (21,23) processes the upper pixels of the shared column (12,15), column-shared ADC-2,4 (22,24) is the shared column (12,15) ) of the sub-pixels. Specifically, the column-shared ADC-1 (21) processes the upper two pixels of the shared column-2 (12), and the column-shared ADC-2 (22) processes the lower two pixels of the shared column-2 (12). processing pixels, column-shared ADC-3 (23) processes the upper two pixels of shared column-5 (15), column-shared ADC-4 (24) processes the lower part of shared column-5 (15) Two pixels are processed.

Accordingly, the pixel processing order in each column-shared ADC (21, 22, 23, 24) is as follows.

column-shared ADC-1(21): 4 pixels of column-1(11) → top 2 pixels of shared column-2(12)

column-shared ADC-2(22): lower 2 pixels of shared column-2(12) → 4 pixels of column-3(13)

column-shared ADC-3(23): 4 pixels of column-4(14) → top 2 pixels of shared column-5(15)

column-shared ADC-4(24): lower 2 pixels of shared column-5(15) → 4 pixels of column-6(16)

So far, the conversion speed of column-shared ADC is 1.5 times faster than the conventional conversion speed, so when column-shared ADCs can process 1.5*N [N is FPS (Frame Per Second)] columns per second, pixels A preferred embodiment of the partitioning method has been described in detail.

According to the above structure, the number of ADCs and the area occupied by the ADCs in the readout circuit can be reduced to 1/1.5 (=2/3).

On the other hand, it is only an exemplary situation that the conversion speed of the ADC is improved so that it can process 1.5*N columns per second, and the technical idea of the present invention is that ADCs can process (m + 0.5)*N columns per second. It can be applied to all cases where it has been improved. Here, m is an integer of 1 or more.

In this case, each ADC will process m columns and half of the shared columns. For example, if the ADC can process 2.5 columns per second, one ADC is designed to process two columns and half the pixels of one shared column. As another example, if the ADC can process 3.5 columns per second, then one ADC is designed to process three columns and half the pixels of one shared column.

At this time, in the readout circuit, the ADC that processes the general column (non-shared column) first and the ADC that processes the shared column first should be sequentially arranged in the pixel array.

Hereinafter, a method for improving the conversion speed of the ADC will be described.

In order to improve the resolution (pixel resolution) and speed (FPS) of the CIS system, various ADC structures have been proposed.

6 is a structure of a synchronous SAR ADC. The clock signal Φ _latch output from the clock generation is used by the comparator and the synchronous SAR logic. According to the Φ _latch , the comparator decides the value and the synchronous SAR logic generates the output code.

Synchronous SAR has a disadvantage in that the number of column-shared ADCs required for the CIS system is large because the worst case must be assumed in all bit decisions.

In general operation of SAR ADC, the comparator compares the sampled pixel voltage for each bit conversion and the voltage of the switching CDAC (Capacitive Digital-to-Analog Converter) and makes a bit decision.

At this time, the smaller the difference between the sample voltage and the CDAC voltage, the longer it takes for the comparator to output the result (quantization time). However, since the pixel voltage cannot be predicted, it is not known at which bit conversion the worst case quantization time will occur. Therefore, the conversion time allocated to all bit conversions is the same.

As a result, the number of column-shared ADCs required is determined assuming the worst case quantization time for all bit conversions. As a result, more column-shared ADC is used than necessary, and the die chip area of the CIS system increases, resulting in an increase in unit cost.

7 is a diagram illustrating the structure of an asynchronous SAR ADC. There is no clock generation, and when the comparator starts latching and the output value is widened beyond a certain level, a flag signal is generated through the XOR gate. In accordance with this signal, asynchronous SAR Logic generates an output code.

8 is a timing diagram of a synchronous SAR ADC, and FIG. 9 is a timing diagram of an asynchronous SAR ADC. When the comparator output (V _COMP+,- ) latches above a certain value, the comparator completes the decision (quantization phase).

The problem is that the required quantization time is different according to the difference between the comparator inputs (V _SH and V _DAC ). The synchronous SAR ADC assumes this quantization time as the worst case for all bits and configures the hardware. Accordingly, the number of column-shared ADCs required in the CIS system increases.

Therefore, in the embodiment of the present invention, by adopting the asynchronous SAR ADC, the quantization phase is terminated immediately after the comparator decision is finished. Accordingly, since there is no need to assume the comparator decision time as the worst, it can be applied to the readout circuit of the CIS system according to the embodiment of the present invention as an ADC having improved speed.

Until now, by dividing pixels for some of the columns of the pixel array so that a plurality of ADCs process them together, even if the ADC speed improvement does not reach an integer multiple of the existing speed, it is possible to reduce the number of ADCs by the speed improvement. method was presented.

In addition, although preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and the technical field to which the present invention belongs without departing from the gist of the present invention as claimed in the claims In addition, various modifications are possible by those of ordinary skill in the art, and these modifications should not be individually understood from the technical spirit or perspective of the present invention.

10: Pixel array
11,13,14,16: non-shared pixel columns
12,15: shared column
20: readout circuit (Readout circuit)
21,22,23,24 : column-shared ADC
30: amplifier
40: interface
51,52,53,54 : MUX

Claims (12)

a pixel array in which pixels that convert an incident light amount into an analog electrical signal are arranged;
A readout circuit that reads a signal generated from pixels arranged in a grid in a pixel array, converts it into a digital signal, and processes it;
The readout circuit is
Some of the pixel columns constituting the pixel array are read by a single ADC and converted into a digital signal,
The rest of the pixel columns constituting the pixel array are read by multiple ADCs and converted into digital signals.
a first ADC that reads m pixel columns and a portion of pixels in a specific pixel column and converts them into digital signals;
A second ADC that reads the remaining pixels of a specific pixel column and m other pixel columns and converts them into digital signals;
m is an integer greater than or equal to 1, wherein the image sensor system.
delete The method according to claim 1,
The first ADC and the second ADC are
It can process more than (m + 0.5)*N pixel columns per second,
N is an image sensor system, characterized in that FPS (Frame Per Second).
The method according to claim 1,
In the readout circuit,
The image sensor system of claim 1, wherein the first ADC and the second ADC are sequentially arranged.
The method according to claim 1,
The first ADC and the second ADC are
An image sensor system, characterized in that it is an asynchronous SAR (Successive Approximation Resister) ADC.
The method according to claim 1,
The readout circuit is
a first MUX connecting one of the m pixel columns and the specific pixel column to the first ADC;
and a second MUX connecting one of the m different pixel columns and the specific pixel column to the second ADC.
7. The method of claim 6,
The first MUX,
When a specific pixel column is connected to the second ADC, a switching operation is performed such that one of the m pixel columns is connected to the first ADC,
The second MUX,
When a specific pixel column is connected to the first ADC, a switching operation is performed such that one of m other pixel columns is connected to the second ADC.
The method according to claim 1,
In the first ADC,
half of the pixels in a particular pixel column are allocated,
In the second ADC,
An image sensor system, characterized in that the other half of the pixels of a specific pixel column are allocated.
9. The method of claim 8,
Half of the pixels allocated to the first ADC,
These are pixels disposed on top of a specific pixel column,
The other half of the pixels allocated to the second ADC,
An image sensor system, characterized in that the pixels are disposed below a specific pixel column.
reading, by the readout circuit, some of the pixel columns constituting the pixel array with a single ADC and converting them into a digital signal;
The readout circuit reads the remainder of the pixel columns constituting the pixel array with a multi-ADC and converts it into a digital signal;
The readout circuit is
a first ADC that reads m pixel columns and a portion of pixels in a specific pixel column and converts them into digital signals;
A second ADC that reads the remaining pixels of a specific pixel column and m other pixel columns and converts them into digital signals;
m is an integer greater than or equal to 1, characterized in that the image sensor readout method.
ADCs that read signals generated from pixels arranged in a grid in a pixel array and convert them into digital signals;
a processor for processing digital signals converted by ADCs;
a decoder for decoding the signal processed by the processor; and
ADCs are
Some of the pixel columns constituting the pixel array are read by a single ADC and converted into a digital signal,
The rest of the pixel columns constituting the pixel array are read by multiple ADCs and converted into digital signals.
a first ADC that reads m pixel columns and a portion of pixels in a specific pixel column and converts them into digital signals;
A second ADC that reads the remaining pixels of a specific pixel column and m other pixel columns and converts them into digital signals;
A readout circuit, characterized in that m is an integer greater than or equal to 1.
reading, by the readout circuit, some of the pixel columns constituting the pixel array with a single ADC and converting them into a digital signal;
reading, by the read-out circuit, the remainder of the pixel columns constituting the pixel array by a multi-ADC and converting it into a digital signal;
The readout circuit processing the digital signal converted by the ADCs;
a readout circuit decoding the processed signal;
The readout circuit is
a first ADC that reads m pixel columns and a portion of pixels in a specific pixel column and converts them into digital signals;
A second ADC that reads the remaining pixels of a specific pixel column and m other pixel columns and converts them into digital signals;
An image sensor readout method where m is an integer greater than or equal to 1;

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