CN1691758A - CMOS image sensor for processing analog signal at high speed - Google Patents
CMOS image sensor for processing analog signal at high speed Download PDFInfo
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- CN1691758A CN1691758A CNA2005100598711A CN200510059871A CN1691758A CN 1691758 A CN1691758 A CN 1691758A CN A2005100598711 A CNA2005100598711 A CN A2005100598711A CN 200510059871 A CN200510059871 A CN 200510059871A CN 1691758 A CN1691758 A CN 1691758A
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- cds
- image sensor
- analog signal
- cmos image
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
- H04N25/671—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction
- H04N25/677—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction for reducing the column or line fixed pattern noise
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
Abstract
A CMOS image sensor includes: a pixel array having a plurality of first pixels, a plurality of second pixels and a plurality of third pixels that are arranged in matrix form and respectively correspond to a first color, a second color and a third color. A first analog signal processing path is arranged in one side of the pixel array to process analog signals outputted from the first pixels, and a second analog signal processing path is arranged in the other side of the pixel array to process analog signals outputted from the second pixels or the third pixels. The first analog signal processing path includes a lower CDS part where one CDS circuit per two adjacent columns of the pixel array is provided. The second analog signal processing path includes an upper CDS part where one CDS circuit per two adjacent columns of the pixel array is provided.
Description
Technical field
The present invention relates to a kind of cmos image sensor; And, more particularly, relate to a kind of cmos image sensor of Analog signals and signal processing method wherein of being used at full speed.
Background technology
Imageing sensor is in order to optical imagery is changed into the equipment of the signal of telecommunication.This imageing sensor mainly is classified as complementary metal oxide semiconductors (CMOS) (CMOS) imageing sensor and charge-coupled device (CCD).
In the situation of CCD, each mos capacitance device is stored in the capacitor very close to ground setting and electric charge carrier each other and is passed to this capacitor.Simultaneously, in the situation of cmos image sensor, use the CMOS integrated circuit technique to construct pel array and by switching manipulation tested in sequence dateout.Because this cmos image sensor has advantage of low power consumption, it extensively is used in PCS Personal Communications System, in cell-phone.
Fig. 1 is the schematic diagram of conventional cmos image sensor.In Fig. 1, the processing from the view data (analog signal) of pixel is illustrated.
With reference to figure 1, this conventional cmos image sensor comprises pel array 11, and wherein red (R), green (G) and blue (B) pixel are set up with M * N matrix form.Correlated-double-sampling (correlateddouble sampling, CDS) part 12 is provided at the downside of pel array 11, and described part comprises the CDS circuit.This CDS circuit is provided at each row.Analogue signal processor (ASP) 13 is provided at the right side of pel array 11 and handles from the analog signal of CDS part 12 outputs.
The CDS circuit is to being applied on the analog data bus from the data-signal of each pixel and reset signal sampling and with the signal of being sampled.Then, ASP 13 calculate between reset signals and the data-signal difference and with its amplification.Therefore, the pure pixel data of practical object can be obtained.
In the process of reads pixel data, the pixel that is provided with along the delegation of pel array 11 is sent to the corresponding CDS circuit of CDS part 12 at once with (at identical clock) simultaneously.Under the control of row driver 14, the output of this CDS circuit sequentially is sent to ASP 13, and is processed therein then.
As mentioned above, according to this conventional cmos image sensor, when delegation was selected, the picture element signal of selected row (reset signal and data-signal) was stored in the corresponding CDS circuit.Then, the signal of corresponding CDS circuit sequentially is sent to ASP by this row driver.
Simultaneously, if millions of pixels is set up, the number of the pixel that then is provided with on line direction increases and therefore the number of CDS circuit must the increase of as much ground.And analog data bus is connected to the CDS circuit of big figure jointly.Like this, the load capacitance of this analog data bus also increases.
Because these reasons, conventional system can not be realized high speed operation.For high speed operation, functional block (particularly ASP) needs to be improved to obtain required signal processing performance.And if High Speed System is designed, the sequential nargin that is used for stabilization signal value in settling time (settling time) is little.Therefore, the reliability of device and productivity ratio are demoted.
In addition, as shown in fig. 1, conventional cmos image sensor comprises a CDS circuit at each row.The transistor that is used for this CDS circuit must be disposed in the pel spacing, and this pel spacing is corresponding to the zone of a pixel.Yet in the situation of the imageing sensor with millions of pixels, Pixel Dimensions is very little.Therefore, the layout of CDS circuit is difficult in the pel spacing.
Summary of the invention
Therefore the purpose of this invention is to provide a kind of cmos image sensor, signal is handled by multipath therein, but chrominance signal (being R, G and B signal) is handled by the path of identical ASP.By this way, offset issue can be minimized and per two pel spacings can be arranged a CDS circuit.Therefore, the layout nargin of CDS circuit can increase and the number of this CDS circuit can reduce.
In one aspect of the invention, provide a kind of cmos image sensor, having comprised: pel array, it has a plurality of first pixels, a plurality of second pixels and a plurality of the 3rd pixel, they are set up and correspond respectively to first look with matrix form, second look and the 3rd look; First analog signal processing path, its side that is set at described pel array is to handle from the analog signal of first pixel output of this pel array; And second analog signal processing path, its opposite side that is set at pel array is to handle from second pixel of this pel array or the analog signal of the 3rd pixel output, wherein first analog signal processing path comprises CDS part down, here per two adjacent column of described pel array are provided a CDS circuit, this time CDS partly is configured to receive the output signal corresponding to first pixel of one of described two row, and second analog signal processing path comprises the CDS part, here per two adjacent column of described pel array are provided a CDS circuit, and CDS partly is configured to receive corresponding to second pixel of one of described two row or the output signal of the 3rd pixel on this.
First analog signal processing path further comprises first choice device, its signal that is used for exporting from a pixel of two pixels is sent to described CDS partial C DS circuit down, described two pixels are present on the identical row and corresponding to two adjacent column, and second analog signal processing path further comprises second choice device, and it is used for the signal from one other pixel output is sent to the described CDS partial C DS circuit of going up.
First analog signal processing path further comprises: at least one is analog data bus down, and the described output signal of CDS partial C DS circuit down is loaded thereon; And following ASP, it is connected to this time analog data bus.Second analog signal processing path further comprises: analog data bus at least one, and the described output signal that goes up CDS partial C DS circuit is loaded thereon; And go up ASP, it is connected to analog data bus on this.
First analog signal processing path further comprises first row driver, and it is configured to produce selects signal, is used in response to column address the described output signal of CDS partial C DS circuit down being sent to down analog data bus.Second analog signal processing path further comprises the secondary series driver, and it is configured to produce selects signal, is used in response to column address the described output signal that goes up CDS partial C DS circuit being sent to down analog data bus.
Description of drawings
According to the following description of carrying out in conjunction with the accompanying drawings to preferred embodiment, above and other purpose of the present invention and characteristics will be conspicuous, in the accompanying drawings:
Fig. 1 is the schematic diagram of conventional cmos image sensor, and it shows analog signal processing path;
Fig. 2 is that it shows analog signal processing path according to the schematic diagram of the cmos image sensor of first embodiment of the invention; And
Fig. 3 is that it shows analog signal processing path according to the schematic diagram of the cmos image sensor of second embodiment of the invention.
Embodiment
Below, describe the present invention with reference to the accompanying drawings.
First embodiment
Fig. 2 is the schematic diagram according to the cmos image sensor of first embodiment of the invention.In the CDS circuit, be used for the path from the signal sampling of pixel is divided into two.In each path, two shared CDS circuit of pixel and per two pel spacings are arranged a CDS circuit.
With reference to figure 2, this cmos image sensor comprises pel array 21, and wherein red (R), green (G) and blue (B) pixel are set up with M * N matrix form.Comprise that the CDS part 22 and 26 of CDS circuit is provided at the downside and the upside of pel array 21 respectively.In each of CDS part 22 and 26, per two pixels of two adjacent column are provided a CDS circuit.The one ASP 23 is provided at the right side of pel array 21 with the analog signal of processing from following CDS part 22 outputs, and the 2nd ASP 27 is provided at the right side of pel array 21 to handle from the analog signal of last CDS part 26 outputs.
Be set at that described upside and the CDS circuit in the downside are shared to be present in the identical row and corresponding to two pixels of two adjacent column.If the picture element signal from a pixel in two neighbors is sent to down the CDS circuit, then the picture element signal from one other pixel must be output to the CDS circuit.For this reason, the output signal of pel array is sent to the CDS part by selecting part 20a and 20b.
In the present embodiment, select part 20a and 20b to be configured with switch, this switching response is driven in row selection signal row_sel.When even number line was selected, row selection signal row_sel was a logical zero.On the contrary, if row selection signal row_sel is that odd-numbered line is selected so for logical one.Therefore, the signal of the G pixel in the pel array all is sent to down the CDS circuit, and the signal of B or R pixel all is sent to the CDS circuit.
Select part 20a and 20b to dispose in every way.For example, but a plurality of control signal can be used and multiplexer place of switches and being used.
The output signal of following CDS part 22 is sent to an ASP23 by first analog data bus 25, and upward the output signal of CDS part 26 is sent to the 2nd ASP 27 by second analog data bus 29.
In response to the selection signal CS that produces from first row driver 24, the output of the CDS circuit of following CDS part 22 is applied on first analog data bus 25, and upward the output of the CDS circuit of CDS part 26 is applied in from the selection signal CS of secondary series driver 28 generations.
The complete operation of reads pixel data will be described below.If the delegation of pel array 21 is selected, then the output signal of the G pixel of selected row is sent to down the CDS circuit of CDS part 22 at once, and the output signal of the B of selected row or R pixel is sent to the CDS circuit of CDS part 26.
Then, first row driver 24 drives the CDS circuit of CDS part 22 down in turn, thereby output signal is loaded on first analog data bus 25.These signals are handled by an ASP 23.In addition, secondary series driver 28 drives the CDS circuit of CDS part 26 in turn, thereby output signal is loaded on this second analog data bus 29.These signals are handled by the 2nd ASP27.
In the present embodiment, because R and the signal of B pixel and the signal of G pixel is handled by different paths, two signals can be processed at a clock in the identical time.Therefore, can implement to have the analogue system of twice bandwidth.
In addition, because two ASP are provided, their task is reduced half.Therefore, the enough idling slow speed systems of this ASP up time nargin.
In addition, though signal is to handle by multipath, chrominance signal (being R, G and B signal) is to handle by the path of identical ASP.By this way, offset issue can be minimized and per two pel spacings can be arranged a CDS circuit.Therefore, the layout nargin of CDS circuit can increase and the number of CDS circuit can reduce, thereby has reduced power consumption.
Second embodiment
Fig. 3 is the schematic diagram according to the cmos image sensor of second embodiment of the invention.In this embodiment, eight analog data bus are applied to upper and lower path respectively.Pel array 21 and the structure of selecting part 20a and 20b are identical with among first embodiment those.
The load capacitance of the analog data line in each path is lowered manyly, reduces the design burden of this ASP thus and improves conversion speed.
According to the present invention, analog passband signal is crossed multipath and is handled, thereby has improved conversion speed by stable signal processing system.In addition, though signal is to handle by multipath, the signal of the same pixel of pel array is to handle by same paths.By this way, the deviation between the same pixel can be minimized and can improve image quality thus.In addition, because per two pel spacings are arranged a CDS circuit, because the Layout Problem of the CDS circuit that the small pixel spacing causes can be solved.
In addition, the mismatch between the transistor also can be minimized.Therefore, fixed pattern noise (FPN) can be suppressed at utmost.Because the CDS circuit of smallest number is used, power consumption is reduced.
The application comprise about korean patent application No.2004-28746 that submits in Korean Patent office on April 26th, 2004 and on December 30th, 2004 respectively and No.2004-116853 theme, the full content of described patent application is hereby incorporated by.
Though the present invention is described with reference to certain embodiments, to one skilled in the art, it is evident that and to carry out variations and modifications as in the spirit and scope of the present invention that following claim limited.
Claims (9)
1. cmos image sensor comprises:
Pel array, it has a plurality of first pixels, a plurality of second pixels and a plurality of the 3rd pixel, they are set up and correspond respectively to first look with matrix form, second look and the 3rd look;
First analog signal processing path, its side that is set at described pel array is to handle from the analog signal of first pixel output of this pel array; And
Second analog signal processing path, the analog signal that its opposite side that is set at described pel array is exported from second pixel or the 3rd pixel of this pel array with processing,
Wherein first analog signal processing path comprises CDS part down, here per two adjacent column of described pel array are provided a CDS circuit, this time CDS partly is configured to receive the output signal corresponding to first pixel of one of described two row, and second analog signal processing path comprises the CDS part, here per two adjacent column of described pel array are provided a CDS circuit, and CDS partly is configured to receive corresponding to second pixel of one of described two row or the output signal of the 3rd pixel on this.
2. cmos image sensor as claimed in claim 1, wherein first analog signal processing path further comprises first choice device, be used for and be sent to down CDS partial C DS circuit from the signal that a pixel of two pixels is exported, these two pixels are present on the identical row and corresponding to two adjacent column, and second analog signal processing path further comprises second choice device, is used for the signal from one other pixel output is sent to CDS partial C DS circuit.
3. cmos image sensor as claimed in claim 2, wherein first analog signal processing path further comprises:
At least one is analog data bus down, and the described output signal of CDS partial C DS circuit down is loaded thereon; And
Following ASP, it is connected to this time analog data bus.
4. cmos image sensor as claimed in claim 3, wherein second analog signal processing path further comprises:
Analog data bus at least one, the described output signal that goes up CDS partial C DS circuit is loaded thereon, and
Last ASP, it is connected to analog data bus on this.
5. cmos image sensor as claimed in claim 3, wherein first analog signal processing path further comprises first row driver, it is configured to produce selects signal, is used for will descending the output signal of CDS partial C DS circuit to be sent to down analog data bus in response to column address.
6. cmos image sensor as claimed in claim 4, wherein second analog signal processing path further comprises the secondary series driver, it is configured to produce to select signal, and the output signal that is used for will going up in response to column address CDS partial C DS circuit is sent to down analog data bus.
7. cmos image sensor as claimed in claim 2, wherein said pel array comprises:
A plurality of even number lines, here first pixel is set at first row, and first pixel and second pixel are arranged alternately; And
A plurality of odd-numbered lines, here the 3rd pixel is set at first row, and the 3rd pixel and first pixel are arranged alternately.
8. cmos image sensor as claimed in claim 7, wherein first switching device and second choice device are configured to have switch element, and it is controlled by row selection signal, and this row selection signal has the information of closing odd number or even number line.
9. cmos image sensor as claimed in claim 8, first pixel wherein, second pixel and the 3rd pixel are respectively the G pixels, R pixel and B pixel.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2004-0028746 | 2004-04-26 | ||
| KR20040028746 | 2004-04-26 | ||
| KR1020040028746 | 2004-04-26 | ||
| KR10-2004-0116853 | 2004-12-30 | ||
| KR1020040116853A KR100588731B1 (en) | 2004-04-26 | 2004-12-30 | CMOS Image Sensor for High Speed analog signal processing |
| KR1020040116853 | 2004-12-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1691758A true CN1691758A (en) | 2005-11-02 |
| CN1691758B CN1691758B (en) | 2010-10-13 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2005100598711A Expired - Fee Related CN1691758B (en) | 2004-04-26 | 2005-03-31 | CMOS image sensor for processing analog signal at high speed |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR100588731B1 (en) |
| CN (1) | CN1691758B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101510964B (en) * | 2008-02-14 | 2011-01-05 | 佳能株式会社 | Image sensing apparatus, image sensing apparatus control method, and imaging system |
| CN102595068A (en) * | 2012-03-15 | 2012-07-18 | 天津大学 | Digital-domain accumulation complementary metal oxide semiconductor-time delay integration (CMOS-TDI) image sensor |
| CN101783891B (en) * | 2009-01-20 | 2013-03-13 | 索尼公司 | Imaging device, control method therefor, and camera |
| CN110084144A (en) * | 2019-04-08 | 2019-08-02 | 杭州士兰微电子股份有限公司 | Sensor module and its pixel circuit and signal processing method |
| CN110147718A (en) * | 2019-04-08 | 2019-08-20 | 杭州士兰微电子股份有限公司 | Sensor module and its pixel circuit and signal processing method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022145509A1 (en) * | 2020-12-29 | 2022-07-07 | 한국전자기술연구원 | Pixel partitioning method for reducing number of analog/digital converters of cmos image sensor system |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0928103A3 (en) * | 1997-12-31 | 2000-08-02 | Texas Instruments Incorporated | CMOS imaging sensors |
| US6753912B1 (en) * | 1999-08-31 | 2004-06-22 | Taiwan Advanced Sensors Corporation | Self compensating correlated double sampling circuit |
| KR100397663B1 (en) * | 2000-06-23 | 2003-09-13 | (주) 픽셀플러스 | Cmos image sensor in which dataline is maintained as data of reset mode |
| EP1176807A1 (en) * | 2000-07-24 | 2002-01-30 | Agilent Technologies, Inc. (a Delaware corporation) | Skewed pixel pattern sub-sampling for image sensor |
| JP2002320235A (en) * | 2001-04-19 | 2002-10-31 | Fujitsu Ltd | Cmos image sensor for generating reduced image signal by suppressing decrease in space resolution |
-
2004
- 2004-12-30 KR KR1020040116853A patent/KR100588731B1/en not_active IP Right Cessation
-
2005
- 2005-03-31 CN CN2005100598711A patent/CN1691758B/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101510964B (en) * | 2008-02-14 | 2011-01-05 | 佳能株式会社 | Image sensing apparatus, image sensing apparatus control method, and imaging system |
| CN101783891B (en) * | 2009-01-20 | 2013-03-13 | 索尼公司 | Imaging device, control method therefor, and camera |
| CN102595068A (en) * | 2012-03-15 | 2012-07-18 | 天津大学 | Digital-domain accumulation complementary metal oxide semiconductor-time delay integration (CMOS-TDI) image sensor |
| CN102595068B (en) * | 2012-03-15 | 2013-05-22 | 天津大学 | Digital-domain accumulation complementary metal oxide semiconductor-time delay integration (CMOS-TDI) image sensor |
| CN110084144A (en) * | 2019-04-08 | 2019-08-02 | 杭州士兰微电子股份有限公司 | Sensor module and its pixel circuit and signal processing method |
| CN110147718A (en) * | 2019-04-08 | 2019-08-20 | 杭州士兰微电子股份有限公司 | Sensor module and its pixel circuit and signal processing method |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20050103447A (en) | 2005-10-31 |
| CN1691758B (en) | 2010-10-13 |
| KR100588731B1 (en) | 2006-06-12 |
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