JP3751931B2 - Area image sensor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a CMOS (Complementary Metal Oxide Semiconductor) type area image sensor incorporated in, for example, a digital camera.
[0002]
[Prior art]
Conventional CMOS area image sensors generally have one signal line parallel to each column of the image sensor and one address line parallel to each row. Each signal line is commonly connected to the image sensor in the corresponding column, and each address line is commonly connected to the image sensor in the corresponding row. An analog / digital converter is connected to the output end of each signal line, and a shift register is connected to the output end of the analog / digital converter (see, for example, Patent Document 1).
[0003]
In such an area image sensor, when a full sampling scan for scanning all address lines is performed, the address lines are selectively scanned one by one in order, and the signal voltage from the image sensor is analog / digital for each row accordingly. Input to the converter. The analog / digital converter sequentially compares a signal voltage input within one address line scanning time with a reference voltage that changes according to the operation clock within the same time, and counts when both voltages match. Is output to the shift register as a digital signal. The shift register sequentially outputs a digital signal from each analog / digital converter in synchronization with the shift pulse. Thereby, continuous pixel data for each row is obtained as a digital signal.
[0004]
By the way, in the full sampling scan, it takes a certain amount of time to obtain image data for one frame that covers the total number of rows, and it is difficult to increase the frame rate. Therefore, for example, when displaying a moving image for preview on a liquid crystal monitor of a digital camera, for example, by extracting only a signal for one pixel from four pixels (four image sensors) in two rows and two columns, A sub-sampling scan is performed so that the data amount for one frame is 1/4 of the full sampling scan.
[0005]
According to this sub-sampling scan, address lines are selectively scanned every other row (one line), and unnecessary address lines are thinned out at a rate of one out of every two lines. Then, unnecessary signals are discarded every other column, so that only signals from 4 pixels to 1 pixel are extracted. In such a sub-sampling scan, if the frame rate is the same as that of the full sampling scan, the address line scanning time per line can be extended to about twice. As a result, the operation clock (clock frequency) of the analog / digital converter can be lowered to about ½. Note that, as described above, the sub-sampling scan that selectively scans the address lines at a ratio of one to two is called a ½ sub-sampling scan.
[0006]
[Patent Document 1]
JP 2001-036816 A
[0007]
[Problems to be solved by the invention]
However, in the conventional area image sensor, for example, when a 1/2 sub-sampling scan is performed, the operation clock of the analog / digital converter is reduced to half by comparison with the rate of reducing the data amount (1/4). The operating clock cannot be reduced dramatically. That is, even from the proportional relationship between the operation clock and power consumption, the power consumption cannot be significantly reduced during the sub-sampling scan.
[0008]
DISCLOSURE OF THE INVENTION
The present invention has been conceived under such circumstances, and it is an object of the present invention to provide an area image sensor that can greatly reduce the operation clock and power consumption during sub-sampling scanning. Yes.
[0009]
In order to solve the above problems, the present invention takes the following technical means.
[0010]
That is, according to the present invention, an area image sensor in which a large number of image sensors are arranged in multiple rows and multiple columns, a plurality of signal lines assigned to each column or two columns of the image sensor, and each signal Each line of the image sensor, and a small group is formed for each image sensor continuously arranged in the same number as the number of signal lines allocated per column. In addition, in the small group, each image sensor is connected to a different signal line, and in each row of the image sensor, a large group is formed for each small group continuously arranged over two or more. In this large group, there are two or more types of connection patterns for signal lines in small group units. It is subjected.
[0011]
As a preferred embodiment, when a predetermined number of signal lines are assigned to each column of the image pickup device, each column of the image pickup device has the same group configuration and a configuration that forms a connection pattern for the signal line. can do.
[0012]
In another preferred embodiment, when a plurality of predetermined signal lines are assigned to each two-column unit of the image sensor, all the columns of the image sensor have the same group configuration, while The connection pattern can be configured to be the same pattern every other column.
[0013]
In each row of the imaging elements, a large group can be formed for each small group that is a power of 2.
[0014]
Each column of the image sensor can be configured to include two or more types of large groups having different numbers of small groups.
[0015]
Within the large group, the same number of image pickup devices as the number of signal lines per column, and image pickup devices positioned in a predetermined regular order may be connected to different signal lines. it can.
[0016]
In addition, an address line that is assigned to each row of the image pickup device and is connected to all the image pickup devices in the row for each line, and the address line are selected while being divided into large groups, a signal per column. An address line selection circuit that simultaneously selects an address line corresponding to a row of imaging elements located in a predetermined regular order, the number of which is equal to the number of lines allocated, and each time the address line selection circuit selects an address line The digital signal output from each of the analog / digital converters is taken in, and the digital signal is output by switching the shift register that outputs these digital signals on a plurality of transfer lines and the transfer line of the shift register. A configuration having a duplexer circuit or a multiplexer circuit may be employed.
[0017]
Each time the address line selection circuit selects an address line, the analog / digital converter sequentially compares a signal voltage input from the signal line with a reference voltage that changes within the selection time of the address line, and the two voltages are The voltage value itself or the count value when they coincide can be output to the shift register as a digital signal.
[0018]
According to the present invention, for example, when two signal lines are allocated to each column of the image sensor, a small group is formed for each image sensor as many as the number of signal lines allocated (two). A large group is formed by the multiplied number, that is, every two small groups. Within each small group, the two image sensors are connected to different signal lines, and within each large group, the connection pattern for the signal line is different for each small group. Further, in the large group, two image sensors located every other row are connected to different signal lines. Such a group configuration and connection pattern are the same over all rows of the image sensor.
[0019]
When performing full sampling scan, two address lines (two rows) can be selected and scanned simultaneously in small group units, and the signal voltage for two consecutive rows is sent to the analog / digital converter accordingly. Can be entered. That is, every time an address line is selectively scanned, the analog / digital converter outputs a digital signal for two consecutive rows, and the shift register outputs a digital signal (pixel data) for two consecutive rows through a duplexer circuit. Is done. According to such a full sampling scan, pixel data for two rows can be obtained almost simultaneously, so that the operation clock of the analog / digital converter is compared with the case where the address lines are selectively scanned one row at a time as in the prior art. (Clock frequency) can be reduced to about ½.
[0020]
On the other hand, when 1/2 sub-sampling scan is performed, two address lines located every other row can be simultaneously selected and scanned while four address lines (for four rows) are grouped into large groups. . In response to this, a signal voltage is transmitted from the image sensor for two rows located every other row to each analog / digital converter through a signal line. The analog / digital converter as a whole outputs two rows of digital signals each time two address lines are selected and scanned simultaneously, and the shift register outputs a total of 2 thinned out at a rate of one row per two rows. Rows of pixel data are output through a duplexer circuit. At this time, by discarding unnecessary pixel data every other column, only pixel data for one element is extracted from four elements in two rows and two columns. According to such a 1/2 sub-sampling scan, the data amount for one frame is set to 1/4 of the full sampling scan. Further, the operation clock of the analog / digital converter is lowered to about ¼ compared with the conventional one.
[0021]
In addition, in each column of the image sensor, a large group composed of two small groups and another large group composed of small groups such as 4, 8, 16 and the like can simultaneously exist. In such a case, 1/4, 1/8, and 1/16 sub-sampling scans can be handled.
[0022]
In addition, for example, even when four signal lines are assigned to each two-row unit of the image sensor, the number of signal lines assigned to one row is the same two as described above. It can be a group structure. At this time, the connection pattern for the signal line can be the same every other column.
[0023]
Therefore, according to the present invention, the operation clock of the analog / digital converter can be reduced at the time of the full sampling scan, so that the operation clock can be further reduced during the sub-sampling scan. Power consumption can be significantly reduced from the proportional relationship with power.
[0024]
Other features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings.
[0026]
FIG. 1 is a configuration diagram of an area image sensor according to a first embodiment of the present invention. The area image sensor 1 is a CMOS image sensor for a digital camera, for example, and includes a horizontally-long rectangular imaging unit 1A. The imaging unit 1A and its peripheral circuits include a large number of photodiodes 10, a large number of switching elements 20, a large number of analog / digital converters (hereinafter referred to as “AD converters”) 30, a shift register 40, and an address line selection circuit. 50, a duplexer circuit 60, signal lines L extending in the vertical direction, address lines A extending in the horizontal direction, and the like.
[0027]
The photodiode 10 and the switching element 20 are connected to each other to form a pair and function as an imaging element. A unit section that divides the image sensors one by one corresponds to one pixel (pixel), and the imaging unit 1A has a pixel array structure in which a large number of image sensors are arranged in multiple rows and multiple columns. As an example, two signal lines L are drawn for each column of the imaging elements. The output ends 20A of the switching elements 20 are connected to these signal lines L in accordance with a predetermined regular pattern. This regular pattern will be described later. The AD converters 30 are connected to the output ends of the signal lines L, the output ends of the AD converters 30 are connected to the shift register 40, and the output ends of the shift register 40 are connected to the duplexer circuit 60. . One address line A is drawn for each row of the image sensor. The input / output gates 20B of the switching elements 20 in all rows are connected to the address lines A in each row. All of these address lines A are connected to an address line selection circuit 50.
[0028]
As for the arrangement of the image sensors and the like, a group of image sensors (pixels) arranged in the horizontal direction is called a “row”, and a group of image sensors arranged in the vertical direction perpendicular to the “row” is expressed as “ This is called a “column”. For example, “first row, second row,...” In order from the top, and “first column, second column,. The signal lines L... Are labeled so as to be “La1, La2” sequentially from the left in the first column, “Lb1, Lb2”, etc. sequentially from the left in the second column. The address lines A are numbered so that the first row, the second row,... Become “A1, A2,.
[0029]
The area image sensor 1 according to this embodiment is based on a monochrome input method. Therefore, for each pixel, a digital pixel signal expressing black and white shading with a digital amount is obtained, and image data for one frame consisting of a monochrome image is obtained for all pixels.
[0030]
FIG. 2 is a circuit diagram of one image sensor. The switching element 20 is formed by combining a reset transistor TR1, a switching transistor TR2, and a source follower amplifier transistor TR3. The reset transistor TR1 and the switching transistor TR2 are realized by a CMOS structure. Although omitted in FIG. 1, a reset line R (reference number R1 for the first row) is drawn for each row, and a common line C (reference number C1 for the first column) is drawn for each column. . The source, gate, and drain of the reset transistor TR1 are connected to the output terminal of the photodiode 10, the reset line R1, and the common line C1, respectively. The source, gate, and drain of the switching transistor TR2 are the common line C1 and address line A1. The source follower amplifier transistor TR3 is connected to the source of the source follower amplifier transistor TR3. The gate of the source follower amplifier transistor TR3 is connected to the output terminal of the photodiode 10, and the drain is connected to the signal line L11. Of these, the contact between the drain of the source follower amplifier transistor TR3 and the signal line L11 corresponds to the output terminal 20A of the switching element 20, and the contact between the gate of the switching transistor TR2 and the address line A1 is the input of the switching element 20. This corresponds to the output gate 20B. In brief, in each pixel, when the input / output gate 20B is turned on and the switching elements 20 are turned on, the signal charges photoelectrically converted from the photodiodes 10 flow into the signal lines L, and these signal lines. A signal voltage is input to the AD converters 30 through L.
[0031]
Next, focusing on the image sensor in the first column and the signal lines L1 and L2 as an example, these regular patterns will be described in detail. Note that the same regular pattern as in the first column is applied to each column other than the first column.
[0032]
FIG. 3 is an explanatory diagram for explaining a regular pattern in the first column. As shown in this figure, the image pickup devices P1, P2,... Arranged in the first column form one small group g1, g2, g3,. , G3,..., Two adjacent image sensors (P1 and P2), (P3 and P4),... Are connected to different signal lines L1, L2. Further, the small groups g1, g2, g3,... Are configured so as to form one large group G1, G2,.
[0033]
Here, for example, when one large group G1 is viewed, the connection pattern of the small group g1 to the signal lines L1 and L2 and the connection pattern of the small group g2 to the signal lines L1 and L2 are different. The other large groups G2, G3,... And about two image pick-up elements (P1 and P3), (P5, P7), ... which are located in 2n + 1 (n = 0, 1) order regular order in each large group G1, G2, ... They are connected to different signal lines L1 and L2.
[0034]
In addition, the small groups g1, g2, g3,..., 2 squared 4, 2 cubed 8, 2 squared 16, and so on, are G # 1, G% 1, G & 1, respectively. Configured to form a large group. For example, in each of the large groups G # 1, G # 2,... Configured for four consecutive small groups (g1 to g4), (g5 to g8),..., The small groups (g1 to g4), ( g5 to g8),... unit connection patterns are divided into two different types, and they do not all become the same pattern. In the large groups G # 1, G # 2,..., Two image pickup devices (P1 and P5), (P9, P13), (Pn and P5) positioned in the 4n + 1 (n = 0, 1) th regular order. Are connected to different signal lines L1 and L2.
[0035]
This is a large group G% 1, G% 2,... Composed of 8 small groups (g1 to g8), (g9 to g16),..., And 16 small groups (g1 to g16),. The same applies to the large group G & 1,. That is, two image pickup devices (P1 and P9), (P17, P25) positioned in the 8n + 1 (n = 0, 1) th regular order in each large group G% 1, G% 2,. Are connected to different signal lines L1 and L2. Further, two image pickup devices (P1 and P17),... Positioned in the 16n + 1 (n = 0, 1) th regular order in each large group G & 1,... Are respectively connected to different signal lines L1, L2. It is connected.
[0036]
Such a connection pattern is repeated for the largest large group G & 1,..., And is repeated for every 32 imaging elements P1, P2,. The regular pattern is determined so as to form the group configuration and connection pattern as described above.
[0037]
According to such a regular pattern, when a full sampling scan for extracting signals from all pixels (imaging elements) is performed, the imaging elements (P1 and P2) in units of small groups g1, g2, g3,. (P3 and P4),... Can be turned on simultaneously, and signal voltages for two consecutive rows can be simultaneously input to the AD converters 30 through the signal lines L. On the other hand, when performing a 1/2 sub-sampling scan in which the address lines A,... Are selectively scanned at a ratio of one to two, the image pickup elements (P1-P4), (P5- .., While separating P8),..., Simultaneously turn on the first and third imaging elements (P1 and P3), (P5 and P7),... Within each large group G1, G2,. it can. That is, the signal voltages for two rows can be input to the AD converters 30 through the signal lines L,.
[0038]
Further, in the case of performing the 1/4 sub-sampling scan, the large groups G # 1, G # 2,..., The image sensors (P1 to P8), (P9 to P16),. The first and fifth imaging elements (P1 and P5), (P9 and P13),... In the groups G # 1, G # 2,.
[0039]
When the 1/8 sub-sampling scan is performed, the large groups G% 1, G% 2,..., While separating the image pickup devices (P1 to P16), (P17 to P32),. The image sensors (P1 and P9), (P17 and P25),... Positioned in the first and ninth positions in% 1, G% 2,.
[0040]
When a 1/16 sub-sampling scan is performed, the image pickup devices (P1 to P32),... Are separated into large groups G & 1,. The imaging devices (P1 and P17) to be turned on can be turned on simultaneously. That is, signal voltages for two rows can be input to the AD converters 30 through the signal lines L,... Even in the 1/2, 1/4, 1/8, and 1/16 subsampling scans.
[0041]
Next, FIG. 4 is a block diagram of one AD converter 30, and FIG. 5 is an explanatory diagram for explaining the operation of the AD converter 30. As shown in FIG. 4, the AD converter 30 includes a comparator 31 and a counter 32. As shown in FIG. 5, a signal voltage sampled and held as an analog signal (shown by a plot in the figure) is input to the comparator 31 through the signal line L and changes in a slope shape in synchronization with the operation clock. The reference voltage to be input is input. This reference voltage is input every address line scanning time (referred to as “line scanning period”) of the address line selection circuit 50. The comparator 31 sequentially compares the signal voltage input for each line scanning period and the reference voltage within the same time, and outputs a latch signal to the counter 32 when the two voltages match. The counter 32 counts the number of clocks for each line scanning cycle. When the counter 32 receives a latch signal from the comparator 31, the counter 32 outputs the clock count number at that time to the shift register 40 as a digital pixel signal. That is, two AD converters 30 are provided corresponding to two signal lines L in each column, and one AD converter 30 outputs an analog signal voltage for one pixel for each line scanning period. Convert to digital pixel signal and output.
[0042]
As shown in FIG. 1, the shift register 40 includes registers 41,... Individually configured by flip-flop circuits or the like. Each register 41 is connected to the output terminal of the AD converter 30. The registers 41 are provided in two stages corresponding to two AD converters 30 in each column, and a group corresponding to the signal line L1 is connected to the first transfer line 42A and the signal line L2. A corresponding group is connected to the second transfer line 42B. In such a shift register 40, the digital pixel signal from each AD converter 30 is temporarily taken into each register 41, and then one digital pixel signal is passed through the two transfer lines 42A and 42B in synchronization with the shift pulse. Forward. At this time, the duplexer circuit 60 switches the transfer lines 42A and 42B at an appropriate timing in conjunction with the operation of the shift register 40. For example, the duplexer circuit 60 sequentially outputs the digital pixel signals on the first transfer line 42A while being connected to the first transfer line 42A, and switches the connection to the second transfer line 42B after the output is completed. The digital pixel signals on the second transfer line 42B are sequentially output. As a result, two rows of digital pixel signals serialized for each row by the shift register 40 are output.
[0043]
In the case of full sampling scan, the address line selection circuit 50 selects two address lines (A1 and A2), (A3 and A4),... Consecutive in small groups g1, g2,. To do. On the other hand, in the case of ½ sub-sampling scan, the address line selection circuit 50 is divided into the 2n + 1 (n = 0, 1) th of the large groups G1, G2,. Two corresponding address lines (A1 and A3),... Are simultaneously selected to be energized. In the case of 1/4 sub-sampling scan, the address line selection circuit 50 is divided into large groups G # 1, G # 2,. Two address lines (reference numerals omitted) corresponding to the 4n + 1 (n = 0, 1) th are simultaneously selected to be in an energized state. Further, in the case of 1/8 and 1/16 sub-sampling scans, the address line selection circuit 50 has a large group of codes G% 1, G% 2,. , Two address lines corresponding to the 8n + 1 (n = 0, 1) th and 16n + 1 (n = 0, 1) th in each large group, while being divided into large groups of symbols G & 2,. At the same time, the energized state is selected. Such an operation of the address line selection circuit 50 is called a selection scan, and is selected once in any of a full sampling scan or a 1/2, 1/4, 1/8, or 1/16 subsampling scan. Two address lines A,... Can be turned on simultaneously for each scan. Further, the time required for one selective scanning is set as a line scanning cycle, and AD conversion processing of the AD converter 30 is performed within that time.
[0044]
Next, the operation of the area image sensor 1 will be described. In order to make the operation principle easy to understand, the imaging unit 1A is composed of only 16 pixels in total of 4 rows and 4 columns, and peripheral circuits such as the AD converter 30... And the shift register 40 are configured accordingly.
[0045]
6 to 8 are explanatory diagrams for explaining a signal processing procedure. 6 is a full sampling scan in which the address lines A1 to A4 are selectively scanned one by one as an operation mode, FIG. 7 is a full sampling scan in which two of the address lines A1 to A4 are selectively scanned simultaneously, and FIG. 8 is one in two. It is a figure corresponding to the 1/2 subsampling scan which carries out selective scanning of 2 pieces simultaneously at a rate. The upper part of each figure shows a timing chart, and the lower part schematically shows the operation of the shift register 40. Note that FIG. 6 is merely for reference and there is actually no operation mode in which the address lines A,... Are selectively scanned one by one.
[0046]
If a full sampling scan is performed in which the address lines A1 to A4 are selectively scanned one by one in sequence, the address line selection circuit 50 performs an address every time the frame signals F1, F2,. The lines A1 to A4 are selectively scanned one by one. Here, the frame signals F1, F2,... Are for giving a timing for periodically capturing one frame of image data. That is, the frequency of the frame signals F1, F2,... Matches the frame rate.
[0047]
When one address line A1 is selectively scanned, the switching elements 20 in the first row connected to the address line A1 are turned on. At the same time, from the photodiodes 10,... Paired with the switching elements 20,... That are turned on, a signal voltage by photoelectric conversion is supplied to the AD converters 30,.
[0048]
As shown in FIG. 5, the AD converters 30 sequentially compare the slope-shaped reference voltage with the analog input signal voltage for each selected scan. Then, the AD converters 30 ... output the clock count number when the two voltages coincide with each other to the shift register 40 as a digital image signal. The shift register 40 outputs a digital image signal until one selection scan is completed. Thereafter, the address lines A2, A3, and A4 are selected and scanned in order in the same manner, and the digital image signal of each row is output from the shift register 40 for each selected scan. That is, one cycle of the address line selection signal and output data shown in FIG. 6 corresponds to a line scanning cycle, and processing of one frame is completed in four line scanning cycles. In short, according to the full sampling scan in which the address lines A1 to A4 are selectively scanned one by one in sequence, the AD converter 30 must perform AD conversion processing four times per frame, and the operation clock (clock frequency) is also increased. Accordingly, the frequency is set to be somewhat high. The clock frequency at this time is “f”.
[0049]
Next, consider an actual full sampling scan in which the address rates A1 to A4 are selectively scanned two by two while the frame rate is the same as described above. In this case, as shown in FIG. 7, the address line selection circuit 50 has two address lines (A1 and A2), (A3) corresponding to the small groups g1, g2, each time the frame signals F1, F2,. And A4) are simultaneously selected and scanned.
[0050]
First, when the two address lines A1, A2 are selected and scanned simultaneously, the switching elements 20,... Connected to the address lines A1, A2 are turned on. At the same time, the signal voltage by photoelectric conversion is supplied to the AD converters 30 through the signal lines L1 and L2 from the photodiodes 10 through the pairs of the switching elements 20 that are turned on.
[0051]
The AD converters 30,... Sequentially compare the reference voltage and the signal voltage for each selected scan, and output the clock count number when the two voltages match to the shift register 40 as a digital image signal. The shift register 40 outputs the digital image signals for two rows before completing one selection scan. Thereafter, the address lines A3 and A4 are simultaneously selected and scanned in the same manner, and the digital image signals for two rows are output from the shift register 40. In this case, one cycle of the address line selection signal and output data shown in FIG. 7 corresponds to a line scanning cycle, and processing of one frame is completed in two line scanning cycles.
[0052]
Here, a difference from the above-described full sampling scan is that a digital image signal for two rows can be obtained by one selection scan. In addition, as shown in FIG. 7, since the transfer lines 42 </ b> A and 42 </ b> B are switched by the duplexer circuit 60 within the line scanning period, the shift register 40 serially outputs digital pixel signals for two rows through the duplexer circuit 60. The point is also different. At this time, the duplexer circuit 60 switches the transfer lines 42A and 42B so as to output the digital pixel signals from the shift register 40 in the row order.
[0053]
That is, according to the actual full sampling scan, the AD conversion process by the AD converter 30 is performed twice per frame. As a result, it is possible to set the line scanning period to be long and set the clock frequency to about f / 2 lower than the previous full sampling scan.
[0054]
Further, a half-full sampling scan is considered with the frame rate set to the same condition as above. In this case, the address line selection circuit 50, as shown in FIG. 8, whenever the frame signals F1, F2,... Are asserted, the address line A1 corresponding to the 2n + 1 (n = 0, 1) th in the large group G1. , A3 are simultaneously selected and scanned.
[0055]
When the two address lines A1 and A3 are selected and scanned simultaneously, the switching elements 20 in the first and third rows connected to the address lines A1 and A3 are turned on. At the same time, the signal voltage by photoelectric conversion is supplied to the AD converters 30 through the signal lines L1 and L2 from the photodiodes 10 through the pairs of the switching elements 20 that are turned on.
[0056]
The AD converters 30,... Sequentially compare the reference voltage and the signal voltage for each selected scan, and output the clock count number when the two voltages match to the shift register 40 as a digital image signal. The shift register 40 outputs the digital image signals for two rows before completing one selection scan. In this case, since one cycle of the address line selection signal and output data shown in FIG. 8 corresponds to the line scanning cycle, the processing of one frame is completed in one line scanning cycle.
[0057]
In such a 1/2 sub-sampling scan, digital image signals for two rows can be obtained by one selection scan, but digital image signals separated every other row can be obtained. That is, as shown in FIG. 8, in the shift register 40, the transfer lines 42A and 42B are switched by the duplexer circuit 60 within the line scanning period, so that every other row of digital pixel signals is serially output through the duplexer circuit 60. . At this time, among the digital pixel signals in every other row, as shown by hatching in FIG. 8, the digital pixel signals in the second and fourth columns are discarded as unnecessary. Therefore, finally, digital pixel signals for 4 pixels are extracted from 16 pixels in 4 rows and 4 columns, and the data amount for one frame is set to 1/4 of the full sampling scan.
[0058]
Therefore, according to the 1/2 sub-sampling scan, the AD conversion process by the AD converter 30 may be performed once per frame, and the clock frequency can be set to about f / 4 by setting the line scanning cycle longer. . Such a reduction rate of the clock frequency is constant as long as the number of pixels is increased as long as the level of the sub-sampling scan is not changed, and is always about f / 4 in the 1/2 sub-sampling scan. Further, if the 1/4, 1/8, and 1/16 sub-sampling scans are performed based on the same operation principle, the clock frequencies can be set to about f / 8, f / 16, and f / 32, respectively.
[0059]
That is, referring again to FIG. 3, at the time of a full sampling scan, as shown by the shaded portion in the figure, two rows of P1, P2 constituting the small groups g1, g2,. Since pixel data is obtained for each row,..., The clock frequency can be set to about f / 2.
[0060]
Further, at the time of 1/2 sub-sampling scan, two rows of P1 and P3 regularly connected to different signal lines L1 and L2 and divided into large groups G1, G2,. Since pixel data is obtained every two rows,..., The clock frequency can be set to about f / 4.
[0061]
Furthermore, at the time of 1/4 sub-sampling scan, two rows of P1 and P5 regularly connected to different signal lines L1 and L2 while being divided into large groups G # 1, G # 2,. Since pixel data is obtained for each of the two rows P9, P13,..., The clock frequency can be reduced to about f / 8.
[0062]
Further, at the time of 1/8 sub-sampling scan, two rows of P1 and P9 regularly connected to different signal lines L1 and L2 are separated while being divided into large groups G% 1, G% 2,. , P17, P25, and so on, pixel data can be obtained for each row, so that the clock frequency can be set to about f / 16.
[0063]
During the 1/16 sub-sampling scan with the smallest sampling rate, P1 is regularly connected to different signal lines L1 and L2 while being divided into large groups G & 1, G & 2 (G & 2 and subsequent figures are not shown),. , P17, P33, P49 (not shown after P33),..., And pixel data can be obtained, so that the clock frequency can be set to about f / 32.
[0064]
Therefore, according to this embodiment, for example, in the 1/2 sub-sampling scan, the operation clock is compared with the operation clock (clock frequency) f of the AD converter 30 when the address lines A,... Are selectively scanned one by one. The power consumption can be reduced to f / 4, and the power consumption can be significantly reduced from the proportional relationship between the operation clock and the power consumption.
[0065]
In the case of 1/4 sub-sampling scan, the operation clock can be reduced to f / 8, and the power consumption can be further greatly reduced. However, if 1/8 and 1/16 subsampling scans are used, a greater effect can be obtained in terms of power consumption.
[0066]
Further, if the operation clock of the AD converter 30 during the sub-sampling scan or the line scanning cycle of the address line selection circuit 50 is adjusted in a well-balanced manner, both high frame rate and low power consumption can be achieved.
[0067]
Next, a second embodiment will be described. Note that the description of the same points as in the first embodiment described above will be omitted.
[0068]
FIG. 9 is a configuration diagram of an area image sensor according to the second embodiment. In the second embodiment, four signal lines L,... Are drawn for each column of the image sensors P,. These signal lines L,... Are connected to image sensors P,... According to a regular pattern described below.
[0069]
FIG. 10 is an explanatory diagram for explaining a regular pattern in the first column in the second embodiment. As shown in this figure, the image pickup devices P1, P2,... Arranged in the first column form one small group g1, g2, g3,. , G3,..., Four image sensors (P1 to P4), (P5 to P8),... Are connected to different signal lines L1 to L4, respectively. Further, the small groups g1, g2, g3,... Are configured so as to form one large group G1, G2,.
[0070]
For example, when one large group G1 is viewed, the connection patterns for the signal lines L1 to L4 of the small group g1 included therein are different from the connection patterns for the signal lines L1 to L4 of the small group g2. The other large groups G2, G3,... In the large groups G1, G2,..., Four image sensors (P1, P3, P5, P7), (P9) positioned in the 2n + 1 (n = 0, 1, 2, 3) th regular order. , P11, P13, P15),... Are connected to different signal lines L1 to L4, respectively.
[0071]
Further, the small groups g1, g2, g3,... Are configured so as to form large groups indicated by symbols G # 1, G% 1, etc., even when every 4 is a square of 2 and every 8 is a cube of 2. The For example, in each of the large groups G # 1, G # 2,... Configured for four consecutive small groups (g1 to g4), (g5 to g8),..., The small groups (g1 to g4), ( g5 to g8),... unit connection patterns are different from each other, and they are not all the same pattern. .., And four imaging elements (P1, P5, P9, P13) positioned in the 4n + 1 (n = 0, 1, 2, 3) th regular order in each large group G # 1, G # 2,. ), (P17, P21, P25, P29),... Are connected to different signal lines L1 to L4, respectively.
[0072]
Further, the same applies to the large groups G% 1,... Configured for each of the eight small groups (g1 to g8), (g9 to g16),. The four image pickup devices (P1, P9, P17, P25),... positioned in the n = 0, 1, 2, 3) regular order are connected to different signal lines L1 to L4, respectively.
[0073]
Such a connection pattern is repeated for each unit of the largest large group G% 1,..., And is repeated for every 32 imaging elements P1, P2,. The regular pattern of the second embodiment is determined to have the group configuration and the connection pattern as described above.
[0074]
According to such a regular pattern, when a full sampling scan for extracting signals from all pixels (imaging devices) is performed, the imaging devices (P1 to P4) in units of small groups g1, g2, g3,. (P5 to P8),... Are simultaneously turned on, and signal voltages for four consecutive rows can be input to the AD converters 30 through the signal lines L,. On the other hand, when 1/2 sub-sampling scanning is performed such that the address lines A,... Are selectively scanned at a ratio of one to two, the image pickup elements (P1-P8), (P9- P16),..., But the image sensors (P1, P3, P5, P7), (P9, P7) located in the first, third, fifth, and seventh positions within each large group G1, G2,. P11, P13, P15),... Can be turned on simultaneously. That is, the signal voltages for four rows can be input to the AD converters 30 through the signal lines L,.
[0075]
In addition, when performing the 1/4 sub-sampling scan, the large groups G # 1, G # 2,..., While separating the image pickup devices (P1 to P16), (P17 to P32),. Image sensors (P1, P5, P9, P13), (P17, P21, P25, P29),... Located in the first, fifth, ninth, and thirteenth positions in the groups G # 1, G # 2,. Can be turned on simultaneously.
[0076]
When the 1/8 sub-sampling scan is performed, the image pickup elements (P1 to P32),... Are divided into large groups G% 1,. 9, the 17th and 25th imaging elements (P1, P9, P17, P25),... Can be simultaneously turned on. That is, the signal voltages for four rows can be simultaneously input to the AD converters 30 through the signal lines L through the 1/2, 1/4, and 1/8 subsampling scans.
[0077]
As shown in FIG. 9, the group of registers 41 corresponding to the signal line L1 is connected to the first transfer line 42A, and the group corresponding to the signal line L2 is connected to the second transfer line 42B. A group corresponding to the line L3 is connected to the third transfer line 42C, and a group corresponding to the signal line L4 is connected to the fourth transfer line 42D. That is, the shift register 40 transfers the digital pixel signals one by one through the four transfer lines 42A, 42B, 42C, and 42D in synchronization with the shift pulse. At this time, the multiplexer circuit 61 switches the four transfer lines 42A, 42B, 42C, and 42D at an appropriate timing in conjunction with the operation of the shift register 40. For example, the multiplexer circuit 61 sequentially outputs the digital pixel signals on the first transfer line 42A one by one, then switches the connection to the second transfer line 42B, outputs the digital pixel signal, and further performs the third transfer. The connection is switched to the line 42C and finally the fourth transfer line 42D to output a digital pixel signal. As a result, four rows of digital pixel signals serialized for each row by the shift register 40 are output.
[0078]
In the case of full sampling scan, the address line selection circuit 50 selects and scans four address lines (A1 to A4), (A5 to A8),... Continuous in small groups g1, g2,. And On the other hand, in the case of ½ sub-sampling scan, the address line selection circuit 50 is divided into the second group n + 1 (n = 0, 1, 2,...) In the large group G1, G2,. 3) The four corresponding address lines (A1, A3, A5, A7),... In the case of 1/4 sub-sampling scan, the address line selection circuit 50 is divided into large groups G # 1, G # 2,. The four address lines (reference numerals omitted) corresponding to the 4n + 1 (n = 0, 1, 2, 3) th are simultaneously selected and scanned to be energized. Further, in the case of 1/8 sub-sampling scan, the address line selection circuit 50 is divided into large groups G% 1,..., But is divided into 8n + 1 (n = 0, 1, The four address lines (reference numerals omitted) corresponding to the (2) and (3) th are simultaneously selected and scanned to be energized. That is, in any of the full sampling scan and the 1/2, 1/4, and 1/8 sub-sampling scans, four address lines A,... Can be turned on simultaneously for each selected scan.
[0079]
Next, the operation of the second embodiment will be described. In order to make the operation principle easy to understand, the image pickup device P,... Consists of only 48 pixels in total of 8 rows and 6 columns as shown in FIG. 9, and peripheral circuits such as the AD converter 30. It is set up according to it.
[0080]
11 and 12 are explanatory diagrams for explaining a signal processing procedure. In particular, FIG. 11A shows a full sampling scan that selectively scans the address lines A1 to A8 one by one as an operation mode, FIG. 11B shows a full sampling scan that selectively scans four address lines at a time, and FIG. These are timing charts corresponding to ½ sub-sampling scans in which four lines are selectively scanned at a rate of one in two. Note that FIG. 11A is merely for comparison and there is actually no operation mode in which the address lines A,... Are selectively scanned one by one.
[0081]
If a full sampling scan is performed such that the address lines A1 to A8 are selectively scanned one by one in sequence, the address line selection circuit 50 asserts frame signals F1, F2,... As shown in FIG. Each time, the address lines A1 to A8 are selectively scanned one by one. At this time, the frequency of the frame signals F1, F2,... Matches the frame rate.
[0082]
When one address line A1 is selectively scanned, the image sensors P,... In the first row connected to the address line A1 are turned on. At the same time, signal voltages are supplied to the AD converters 30 through the signal lines La1, Lb1,.
[0083]
The AD converters 30,... Sequentially compare the reference voltage and the signal voltage for each selected scan, and output the clock count number when the two voltages match to the shift register 40 as a digital image signal. The shift register 40 outputs a digital image signal until one selection scan is completed. Thereafter, the address lines A2, A3,... Are sequentially selected and scanned in the same manner, and a digital image signal for each row is output from the shift register 40 for each selected scan. That is, one cycle of the address line selection signal and output data shown in (a) of FIG. 11 corresponds to a line scanning cycle, and processing of one frame is completed in eight line scanning cycles. In short, according to the full sampling scan in which the address lines A1 to A8 are selectively scanned one by one in sequence, the AD converter 30 must perform AD conversion processing eight times per frame, and the operation clock (clock frequency) is also increased. Accordingly, the frequency is set to be somewhat high. The clock frequency at this time is “f”.
[0084]
Next, an actual full sampling scan in which four address lines A1 to A8 are selected and scanned while the frame rate is the same as described above will be considered. In this case, as shown in FIG. 11B, the address line selection circuit 50 has four address lines (A1 to A4) corresponding to the small groups g1, g2 each time the frame signals F1, F2,. ), (A5 to A8) are simultaneously selected and scanned.
[0085]
First, when the four address lines A1 to A4 are selected and scanned simultaneously, the image sensors P,... Connected to the address lines A1 to A4 are turned on. At the same time, signal voltages are supplied to the AD converters 30 through the signal lines L1 to L4 from the image pickup devices P through the turned on.
[0086]
The AD converters 30,... Sequentially compare the reference voltage and the signal voltage for each selected scan, and output the clock count number when the two voltages match to the shift register 40 as a digital image signal. The shift register 40 outputs digital image signals for four rows before completing one selection scan. Thereafter, the address lines A5 to A8 are simultaneously selected and scanned in the same manner, and the digital image signals for four rows are output from the shift register 40. In this case, one cycle of the address line selection signal and output data shown in FIG. 11B corresponds to a line scanning cycle, and processing of one frame is completed in two line scanning cycles.
[0087]
Here, a difference from the above-described full sampling scan is that a digital image signal for four rows can be obtained by one selection scan. Also, the shift register 40 is different in that the transfer lines 42A, 42B, 42C, and 42D are switched by the multiplexer circuit 61 within the line scanning cycle, so that digital pixel signals for four rows are serially output through the multiplexer circuit 61. . The multiplexer circuit 61 switches the transfer lines 42A, 42B, 42C, and 42D so as to output the digital pixel signals from the shift register 40 in the row order. For example, in the step of outputting the first four rows (selection scanning step of the address lines A1 to A4), the transfer lines are switched in the order of reference numerals 42A, 42B, 42C, and 42D, and the next four rows are output ( In the selection scanning stage of the address lines A5 to A8), switching is performed in the order of reference numerals 42B, 42C, 42D, and 42A.
[0088]
That is, according to the actual full sampling scan, the AD conversion process by the AD converter 30 is performed twice per frame. As a result, it is possible to set the line scanning period to be long and set the clock frequency to about f / 4 lower than the previous full sampling scan.
[0089]
Further, a half-full sampling scan is considered with the frame rate set to the same condition as above. In this case, as shown in FIG. 12, the address line selection circuit 50 corresponds to the 2n + 1 (n = 0, 1, 2, 3) th in the large group G1 every time the frame signals F1, F2,. The selected address lines A1, A3, A5 and A7 are selected and scanned simultaneously.
[0090]
When four address lines A1, A3, A5, A7 are selected and scanned simultaneously, the image sensors P in the first, third, fifth, and seventh rows connected to these address lines A1, A3, A5, and A7. , ... are turned on. At the same time, signal voltages are supplied to the AD converters 30 through the signal lines L1 to L4 from the image pickup devices P through the turned on.
[0091]
The AD converters 30,... Sequentially compare the reference voltage and the signal voltage for each selected scan, and output the clock count number when the two voltages match to the shift register 40 as a digital image signal. The shift register 40 outputs digital image signals for four rows before completing one selection scan. In this case, since one cycle of the address line selection signal and output data shown in FIG. 12 corresponds to the line scanning cycle, the processing of one frame is completed in one line scanning cycle.
[0092]
In such a 1/2 sub-sampling scan, digital image signals for four rows can be obtained by one selection scan, but digital image signals separated every other row can be obtained. That is, in the shift register 40, the transfer lines are switched in the order of reference numerals 42A, 42C, 42B, and 42D by the multiplexer circuit 61 within the line scanning cycle, so that every other row of digital pixel signals is serially output through the multiplexer circuit 61. . At this time, among the digital pixel signals in every other row, the digital pixel signals in the second, fourth, and sixth columns are discarded as unnecessary. Therefore, finally, digital pixel signals for 12 pixels are extracted from 48 pixels in 8 rows and 6 columns, and the data amount for one frame is set to 1/4 of the full sampling scan.
[0093]
Therefore, according to the 1/2 sub-sampling scan of the second embodiment, the AD conversion processing by the AD converter 30 is only once per frame, the line scanning cycle is set longer and the clock frequency is about f / 8. Can be. Such a reduction rate of the clock frequency is constant as long as the number of pixels is increased as long as the level of the sub-sampling scan is not changed, and is always about f / 8 in the 1/2 sub-sampling scan. In addition, based on the same operation principle, the clock frequency can be set to about f / 16 and f / 32, respectively, if 1/4 and 1/8 sub-sampling scans are performed.
[0094]
That is, referring again to FIG. 10, at the time of the full sampling scan, as shown by the shaded portion in the figure, four rows of P1 to P4 and 4 of P5 to P8 constituting the small groups g1, g2,. Since pixel data is obtained for each row,..., The clock frequency can be set to about f / 4.
[0095]
Further, at the time of 1/2 sub-sampling scanning, four rows of P1, P3, P5, and P7 regularly connected to different signal lines L1 to L4 while being divided into large groups G1, G2,. Since pixel data is obtained for each of the four rows P9, P11, P13, P15,..., The clock frequency can be reduced to about f / 8.
[0096]
Further, at the time of 1/4 sub-sampling scan, P1, P5, P9, and P13 regularly connected to different signal lines L1 to L4 while being divided into large groups G # 1, G # 2,. Since the pixel data is obtained for each of the four rows, P17, P21, P25, P29,..., The clock frequency can be reduced to about f / 16.
[0097]
At the time of 1/8 sub-sampling scan with the smallest sampling rate, the large groups G% 1, G% 2 (G & 2 and subsequent figures are not shown),... Are divided and regularly connected to different signal lines L1 to L4. Pixel data is obtained for each of four rows P1, P9, P17, and P25, four rows P33, P41, P49, and P57 (not shown after P33),..., So that the clock frequency is about f / 32. can do.
[0098]
Therefore, according to the second embodiment, for example, in the 1/2 sub-sampling scan, the operation clock is compared with the operation clock (clock frequency) f of the AD converter 30 when the address lines A,. Can be reduced to f / 8, and the power consumption can be greatly reduced from the proportional relationship between the operation clock and the power consumption.
[0099]
In the case of 1/4 sub-sampling scan, the operation clock can be reduced to f / 16, and the power consumption can be further greatly reduced. Further, if the 1/8 sub-sampling scan is used, a greater effect can be obtained in terms of power consumption.
[0100]
Also in the second embodiment, if the operation clock of the AD converter 30 at the time of sub-sampling scanning or the line scanning cycle of the address line selection circuit 50 is adjusted in a well-balanced manner, both high frame rate and low power consumption can be achieved. be able to.
[0101]
Next, a third embodiment will be described. Note that the description of the same points as in the first or second embodiment described above will be omitted.
[0102]
FIG. 13 is a configuration diagram of an area image sensor according to the third embodiment. The area image sensor according to the third embodiment is suitable for a color input method. Each of the image pickup devices P,... Is filtered by any one of the three primary colors RGB. More specifically, the image sensor P of 2 rows and 2 columns indicated by virtual lines is one pixel, and the color filter is, for example, G at the upper left, R at the upper right, B at the lower left, and lower right for each pixel. Are arranged to be G. In such a pixel structure, one image sensor P corresponds to one subpixel. Therefore, the color pixel signal of 1 pixel is composed of digital pixel signals for 4 sub-pixels (imaging devices) having 2 rows and 2 columns.
[0103]
In the third embodiment, the number of signal lines L,... Per row (four) is the same as in the second embodiment, while the signal lines L,. The regular pattern is slightly different from the second embodiment.
[0104]
FIG. 14 is an explanatory diagram for explaining a regular pattern in the first column in the third embodiment. The third embodiment is the same as the second embodiment in that the group configuration and the connection patterns of the small groups g1, g2,... Are different in each large group G1, G2,. On the other hand, looking at the entire column, there are only two types of connection patterns for the signal lines L1 to L4 of the small groups g1, g2,. Therefore, in each large group G1, G2,..., Four imaging elements (P1, P2, P5, P6), (P9, Pn, 4n + 1 and 4n + 2 (n = 0, 1)) are arranged in a regular order. P10, P13, P14),... Are connected to different signal lines L1 to L4, respectively.
[0105]
Also, as the large group indicated by the symbols G # 1, G # 2,..., The 8n + 1 and 8n + 2 (n = 0, 1) th regular groups in the individual large groups G # 1, G # 2,. The four image pickup elements (P1, P2, P9, P10), (P17, P18, P25, P26),... Positioned in this order are connected to different signal lines L1 to L4, respectively.
[0106]
Further, as the large group indicated by the symbol G% 1,..., Four image pickup elements positioned in the 16n + 1 and 16n + 2 (n = 0, 1) th regular order within each large group G% 1,. (P1, P2, P17, P18),... Are connected to different signal lines L1 to L4, respectively.
[0107]
Such a connection pattern is repeated for each unit of the largest large group G% 1,..., And is repeated for every 32 imaging elements P1, P2,. The regular pattern of the third embodiment is determined so as to form the group configuration and the connection pattern as described above.
[0108]
According to such a regular pattern, the operation in the case of performing a full sampling scan for extracting signals from all pixels (imaging devices) is the same as that of the second embodiment as small groups g1, g2, g3,. It is the same. On the other hand, when 1/2 sub-sampling scanning is performed such that the address lines A,... Are selectively scanned at a ratio of one to two, the image pickup elements (P1-P8), (P9- P16),..., But the image sensors (P1, P2, P5, P6), (P9, P6) located in the first, second, fifth, and sixth positions within each large group G1, G2,. P10, P13, P14),... Can be turned on simultaneously. That is, the signal voltages for four rows can be input to the AD converters 30 through the signal lines L,.
[0109]
In addition, when performing the 1/4 sub-sampling scan, the large groups G # 1, G # 2,..., While separating the image pickup devices (P1 to P16), (P17 to P32),. Imaging elements (P1, P2, P9, P10), (P17, P18, P25, P26),... Located in the first, second, ninth, and tenth positions in the groups G # 1, G # 2,. Can be turned on simultaneously.
[0110]
When the 1/8 sub-sampling scan is performed, the image pickup elements (P1 to P32),... Are divided into large groups G% 1,. The image sensors (P1, P2, P17, P18) located at the 2nd, 17th, and 18th positions can be simultaneously turned on. That is, the signal voltages for four rows can be simultaneously input to the AD converters 30 through the signal lines L through the 1/2, 1/4, and 1/8 subsampling scans.
[0111]
In the case of full sampling scan, the address line selection circuit 50 selects and scans four address lines (A1 to A4), (A5 to A8),... Continuous in small groups g1, g2,. And On the other hand, in the case of ½ sub-sampling scan, the address line selection circuit 50 is divided into the large groups G1, G2,..., But is divided into the 4n + 1 and 4n + 2 (n = 0, 1) in the large groups G1, G2,. The four corresponding address lines (A1, A2, A5, A6),... In the case of 1/4 sub-sampling scan, the address line selection circuit 50 is divided into large groups G # 1, G # 2,. The four address lines (symbol omitted) corresponding to the 8n + 1 and 8n + 2 (n = 0, 1) th are simultaneously selected and scanned to be energized. Further, in the case of 1/8 subsampling scan, the address line selection circuit 50 divides the large group G% 1,... Into units, but the 16n + 1 and 16n + 2 (n = 0) within the large group G% 1,. , 1) The four corresponding address lines (reference numeral omitted) are simultaneously selected and scanned to be energized. That is, in any of the full sampling scan and the 1/2, 1/4, and 1/8 sub-sampling scans, four address lines A,... Can be turned on simultaneously for each selected scan.
[0112]
Next, the operation of the third embodiment will be described. The operation timing is the same as that shown in FIGS. 11 and 12 corresponding to the second embodiment, and is not shown.
[0113]
As an operation mode of the third embodiment, consider a 1/2 sub-full sampling scan in which the frame rate is the same as that of the full sampling scan. In this case, each time the frame signal is asserted, the address line selection circuit 50 simultaneously selects the 4n + 1 and 4n + 2 (n = 0, 1) th address lines A1, A2, A5, and A6 in the large group G1. Scan.
[0114]
When four address lines A1, A2, A5, A6 are simultaneously selected and scanned, the image sensors P in the first, second, fifth, and sixth rows connected to these address lines A1, A2, A5, and A6. , ... are turned on. At the same time, signal voltages are supplied to the AD converters 30 through the signal lines L1 to L4 from the image pickup devices P through the turned on.
[0115]
The AD converters 30,... Sequentially compare the reference voltage and the signal voltage for each selected scan, and output the clock count number when the two voltages match to the shift register 40 as a digital image signal. The shift register 40 outputs digital image signals for four rows before completing one selection scan. Thereafter, the same operation is repeated for each large group G2,. Therefore, even with such a 1/2 sub-sampling scan, processing for one frame is completed in one line scanning cycle, as in the second embodiment. Also, the data amount for one frame is 1/4 of the full sampling scan. The operation clock (clock frequency) of the AD converter 30 can be set to about f / 8.
[0116]
Further, based on the same operating principle as in the second embodiment, the clock frequency can be set to about f / 16 and f / 32, respectively, if the 1/4 and 1/8 subsampling scans are performed.
[0117]
That is, referring to FIG. 14 again, at the time of the full sampling scan, as shown by the shaded portion in the figure, four rows of P1 to P4 constituting the small groups g1, g2,. Since pixel data is obtained for each row,..., The clock frequency can be set to about f / 4.
[0118]
Further, at the time of 1/2 sub-sampling scanning, four rows of P1, P2, P5, P6 regularly connected to different signal lines L1 to L4 while being divided into large groups G1, G2,. Since pixel data is obtained for each of the four rows P9, P10, P13, P14,..., The clock frequency can be reduced to about f / 8.
[0119]
Further, at the time of 1/4 sub-sampling scan, P1, P2, P9, and P10 regularly connected to different signal lines L1 to L4 while being divided into large groups G # 1, G # 2,. Since the pixel data is obtained for each of the four rows, P17, P18, P25, P26,..., The clock frequency can be reduced to about f / 16.
[0120]
At the time of 1/8 sub-sampling scan with the smallest sampling rate, the large groups G% 1, G% 2 (G & 2 and subsequent figures are not shown),... Are divided and regularly connected to different signal lines L1 to L4. Pixel data is obtained for each of the four rows P1, P2, P17, and P18, the four rows P33, P34, P49, and P50 (not shown after P33),..., So that the clock frequency is about f / 32. can do.
[0121]
Therefore, according to the third embodiment, since a regular pattern is set such that one pixel is not decomposed into sub-pixel units during the sub-sampling scan, the same effect as that of the second embodiment can be obtained as a color input method. be able to.
[0122]
Furthermore, a fourth embodiment will be described. The description of the same points as in the first to third embodiments described above will be omitted.
[0123]
FIG. 15 is a configuration diagram of an area image sensor according to the fourth embodiment. The area image sensor according to the fourth embodiment is also suitable for the color input method, as in the third embodiment. The RGB three primary color filters are arranged to form a pattern similar to that shown in FIG. 13, and the image sensor (subpixel) P,...
[0124]
In the fourth embodiment, eight signal lines L1 to L8 are assigned to two columns. That is, the eight signal lines L1 to L8 are connected so as to be shared by the two rows of image pickup devices P,. Therefore, the number of signal lines L,... Per column is four, which is the same as in the third embodiment.
[0125]
FIG. 16 is an explanatory diagram for explaining a regular pattern in the first column in the fourth embodiment. The fourth embodiment is the same as the third embodiment in terms of group configuration. On the other hand, when the entire column is limited to the first column, there are four types of connection patterns for the signal lines L1 to L8 of the small groups g1, g2,..., But only two of them are the signal lines L1 to L4. The other two types are for only the signal lines L5 to L8. Therefore, in each large group G1, G2,..., Four imaging elements (P1, P2, P5, P6), (P9, Pn, 4n + 1 and 4n + 2 (n = 0, 1)) are arranged in a regular order. P10, P13, P14),... Are connected to different signal lines (L1 to L4) and (L5 to L8) while corresponding to any group of the signal lines L1 to L4 or the signal lines L5 to L8. Yes.
[0126]
Further, regarding the large groups indicated by the symbols G # 1, G # 2,..., The 8n + 1 and 8n + 2 (n = 0, 1) th rules in the individual large groups G # 1, G # 2,. The four image pickup devices (P1, P2, P9, P10), (P17, P18, P25, P26),... Positioned in a specific order are connected to different signal lines L1 to L8, respectively.
[0127]
Further, as the large group indicated by the symbol G% 1,..., Four image pickup elements positioned in the 16n + 1 and 16n + 2 (n = 0, 1) th regular order within each large group G% 1,. (P1, P2, P17, P18),... Are connected to different signal lines L1 to L4, respectively.
[0128]
Further, as shown in FIG. 15, the connection pattern of the entire column is the same pattern in the first column and the third column of the odd columns, and the second column and the fourth column of the even columns are the same. Consists of patterns. And the connection pattern is formed in the 1st row | line | column and 2nd row | line | column which adjoin, and the 3rd row | line and the 4th row | line. As is clear from this, the same wiring pattern is formed every other column. Such a connection pattern is repeated for each unit of the largest large group G% 1,..., And is repeated for every 32 imaging elements P1, P2,. The regular pattern of the fourth embodiment is determined so as to form the group configuration and the connection pattern as described above.
[0129]
Even with such a regular pattern, the same operation as in the third embodiment can be realized. Therefore, when 1/2, 1/4, and 1/8 sub-sampling scans are performed, four rows of signal voltages corresponding to each sub-sampling scan are applied to four of the eight signal lines L1 to L8. Through the AD converters 30 and so on.
[0130]
That is, referring again to FIG. 16, at the time of the full sampling scan, as shown by the shaded portion in the figure, four rows of P1 to P4 constituting the small groups g1, g2,. Since pixel data is obtained for each row,..., The clock frequency can be set to about f / 4.
[0131]
Further, at the time of 1/2 sub-sampling scanning, four rows of P1, P2, P5, and P6 regularly connected to different signal lines L1 to L8 while being divided into large groups G1, G2,. Since pixel data is obtained for each of the four rows P9, P10, P13, P14,..., The clock frequency can be reduced to about f / 8.
[0132]
Further, at the time of 1/4 sub-sampling scan, P1, P2, P9, and P10 are regularly located by being connected to different signal lines L1 to L8 while being divided into large groups G # 1, G # 2,. Since the pixel data is obtained for each of the four rows, P17, P18, P25, P26,..., The clock frequency can be reduced to about f / 16.
[0133]
At the time of 1/8 sub-sampling scan with the smallest sampling rate, the large groups G% 1, G% 2 (G & 2 and subsequent figures are not shown),... Are divided and regularly connected to different signal lines L1 to L4. Pixel data is obtained for each of the four rows P1, P2, P17, and P18, the four rows P33, P34, P49, and P50 (not shown after P33),..., So that the clock frequency is about f / 32. can do.
[0134]
Therefore, according to the fourth embodiment, the same effects as those of the third embodiment can be obtained in accordance with the color input method.
[0135]
As a modification of the fourth embodiment, a configuration as shown in FIGS. 17 and 18 may be used.
[0136]
Even in such a modification, eight signal lines L1 to L8 are assigned to two columns, and the number of signal lines L,... Per column is four. The difference from the previous fourth embodiment is that two opposing image pickup devices P, P are always connected to adjacent signal lines L, L. Therefore, in each large group G1, G2,..., Four imaging elements (P1, P2, P5, P6), (P9, Pn, 4n + 1 and 4n + 2 (n = 0, 1)) are arranged in a regular order. .., P10, P13, P14),... Correspond to one group of signal lines L1, L3, L5, L7 corresponding to odd columns or signal lines L2, L4, L6, L8 corresponding to even columns, respectively. It is connected to the lines (L1, L3, L5, L7), (L2, L4, L6, L8).
[0137]
Further, regarding the large groups indicated by the symbols G # 1, G # 2,..., The 8n + 1 and 8n + 2 (n = 0, 1) th rules in the individual large groups G # 1, G # 2,. The four image pickup devices (P1, P2, P9, P10), (P17, P18, P25, P26),... Positioned in a specific order are connected to different signal lines L1 to L8, respectively.
[0138]
Further, as the large group indicated by the symbol G% 1,..., Four image pickup elements positioned in the 16n + 1 and 16n + 2 (n = 0, 1) th regular order within each large group G% 1,. (P1, P2, P17, P18),... Are connected to different signal lines L1, L3, L5, and L7, respectively.
[0139]
Even with such a connection pattern, the same operation as in the fourth embodiment can be realized. As is clear from FIG. 18, the clock frequency can be set to about f / 4 during the full sampling scan. Further, the clock frequency can be set to about f / 8 at the time of 1/2 sub-sampling scan. Further, the clock frequency can be set to about f / 16 at the 1/4 sub-sampling scan. In the 1/8 sub-sampling scan with the smallest sampling rate, the clock frequency can be set to about f / 32.
[0140]
Therefore, also by the modification of the fourth embodiment, it is possible to obtain the same effect as that of the third embodiment, which is suitable for the color input method.
[0141]
The effects of the above embodiments are particularly effective when, for example, a moving image is displayed on a liquid crystal monitor, or when moving image data is taken into a recording memory or the like.
[0142]
The present invention is not limited to the above embodiments.
[0143]
The area image sensor 1 can be applied not only to a digital camera but also to, for example, a digital video camera, a portable telephone with a photographing function, and further widely applicable to an industrial inspection apparatus.
[0144]
The imaging unit 1A may not have a structure in which imaging elements are strictly arranged in multiple rows and multiple columns, and may have a honeycomb structure, for example.
[0145]
Although FIG. 2 shows an example of an image pickup device including one photodiode and three transistors, for example, the switching device 20 may have a four-transistor structure.
[0146]
The number of signal lines L assigned to each column is preferably about 4 to 8, but may be at least 2 or more.
[0147]
The AD converter 30 is not limited to the method using the slope-shaped reference voltage. For example, a reference voltage as a digital quantity may be generated based on an operation clock, and the reference voltage and signal voltage may be sequentially compared to output the voltage value itself when the two voltages match as a digital pixel signal.
[0148]
In the case of the color input method, the color filter applied to each image sensor may be a complementary color filter that separates colors into YMC and G.
[0149]
In addition, when one image sensor has a characteristic capable of color separation into RGB three primary colors according to input sensitivity, the first and second embodiments can be applied as a color input method.
[0150]
In each of the above embodiments, in order to support a plurality of types of sub-sampling scans, the same connection pattern is not repeated for each of the largest groups G1, G2,. If only the / 2 sub-sampling scan is performed, the same connection pattern may be repeated for each large group G1, G2,.
[0151]
Other changes can be made within the scope of the present invention. For example, when the number of signal lines per column is six, six image sensors form one small group, and six addresses are arranged in an appropriate order during 1/2 sub-sampling scanning. The lines may be turned on simultaneously in one selection scan.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an area image sensor according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram of one image sensor.
FIG. 3 is an explanatory diagram for explaining a regular pattern in a first column.
FIG. 4 is a block diagram of one AD converter.
FIG. 5 is an explanatory diagram for explaining the operation of an AD converter;
FIG. 6 is an explanatory diagram for explaining a signal processing procedure;
FIG. 7 is an explanatory diagram for explaining a signal processing procedure;
FIG. 8 is an explanatory diagram for explaining a signal processing procedure;
FIG. 9 is a configuration diagram of an area image sensor according to a second embodiment.
FIG. 10 is an explanatory diagram for explaining a regular pattern in the first column in the second embodiment.
FIG. 11 is an explanatory diagram for explaining a signal processing procedure;
FIG. 12 is an explanatory diagram for explaining a signal processing procedure;
FIG. 13 is a configuration diagram of an area image sensor according to a third embodiment.
FIG. 14 is an explanatory diagram for explaining a regular pattern in the first column in the third embodiment.
FIG. 15 is a configuration diagram of an area image sensor according to a fourth embodiment.
FIG. 16 is an explanatory diagram for explaining a regular pattern in the first column in the fourth embodiment.
FIG. 17 is a configuration diagram showing a modification of the fourth embodiment.
FIG. 18 is an explanatory diagram for explaining a regular pattern in the first column in a modified example;
[Explanation of symbols]
1 Area image sensor
1A Imaging unit
10 Photodiode
20 Switching element
30 AD converter
40 shift register
41 registers
42 Transfer line
50 Address line selection circuit
60 duplexer circuit
61 Multiplexer circuit
A Address line
L signal line
P Image sensor
g Small group
G large group

Claims (8)

An area image sensor in which a large number of image sensors are arranged in multiple rows and multiple columns,
A plurality of signal lines assigned to each column or two columns of the image sensor;
An analog / digital converter connected to the output end of each signal line,
In each column of the image pickup elements, a small group is formed for each image pickup element continuously arranged for the same number as the number of signal lines assigned to one column, and each image pickup element has a different signal line in the small group. Connected to
Furthermore, in each row of image sensors, a large group is formed for each small group that is continuously arranged over two or more, and within this large group, there are two or more types of connection patterns for signal lines in small group units. An area image sensor. 2. The area image according to claim 1, wherein when a plurality of predetermined signal lines are assigned to each column of the image pickup device, each column of the image pickup device forms a connection pattern for the same group configuration and signal line. Sensor. When a predetermined number of signal lines are assigned to each two-row unit of the image pickup device, all the rows of the image pickup device have the same group configuration, while the connection pattern for the signal line is the same pattern every other row. The area image sensor according to claim 1, wherein: The area image sensor according to any one of claims 1 to 3, wherein a large group is formed for each small group of powers of 2 in each row of the image pickup devices. The area image sensor according to claim 4, wherein each row of the image pickup device includes two or more types of large groups having different numbers of small groups. In the large group, the same number of image pickup devices as the number of signal lines assigned to one column, and image pickup devices located in a predetermined regular order are connected to different signal lines, respectively. The area image sensor according to claim 5. One address line assigned to each row of the image sensor, and an address line to which all the image sensors in the row are connected,
When selecting the address lines while separating them into large groups, simultaneously select the address lines corresponding to the rows of the imaging elements that are the same number as the number of signal lines allocated per column and are located in a predetermined regular order. An address line selection circuit to perform,
Each time the address line selection circuit selects an address line, a shift register that takes in digital signals output from each of the analog / digital converters and outputs these digital signals on a plurality of transfer lines;
The area image sensor according to claim 6, further comprising a duplexer circuit or a multiplexer circuit that switches a transfer line of the shift register and outputs a digital signal. Each time the address line selection circuit selects an address line, the analog / digital converter sequentially compares a signal voltage input from the signal line with a reference voltage that changes within the selection time of the address line, and the two voltages are The area image sensor according to claim 7, wherein the voltage value itself or the count value when they coincide with each other is output as a digital signal to the shift register.

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