CN100407773C - Area image sensor - Google Patents
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- CN100407773C CN100407773C CN2003801011874A CN200380101187A CN100407773C CN 100407773 C CN100407773 C CN 100407773C CN 2003801011874 A CN2003801011874 A CN 2003801011874A CN 200380101187 A CN200380101187 A CN 200380101187A CN 100407773 C CN100407773 C CN 100407773C
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Abstract
An area image sensor ( 1 ) includes a plurality of image pick-up elements ( 10, 20 ) arranged in a matrix including a plurality of element rows and a plurality of element columns. A plurality of signal lines (L 11 -L 14 ) are allocated to a respective one of the element columns. Each of the signal lines includes an output terminal to which an A/D converter ( 30 ) is connected. Each of the image pick-up elements belonging to the one element column is connected to only one of the signal lines, and each of the signal lines is connected to at least one of the image pick-up elements belonging to the one element column.
Description
Technical field
The present invention's for example CMOS profile type imageing sensor (areaimage sensor) (two-dimensional image sensor) of digital camera that relates to pack into.
Background technology
One example of existing C MOS profile type imageing sensor, the existing record in Japanese Patent Application Publication communique P2001-36816A.Shown in Figure 1 as this communique, existing area image sensor comprises a plurality of imaging apparatuss (each imaging apparatus is made up of photodiode and switching transistor) of rectangular configuration.The vertical arrangement of imaging apparatus is called row, and the arrangement of the horizontal stroke of imaging apparatus is called row.Be arranged with a signal line in parallel with each row of imaging apparatus, be arranged with an address wire in parallel with each row.Be connected with the imaging apparatus (more clearly saying it is the output of switching transistor) of corresponding row on each holding wire.And, be connected with the imaging apparatus (more clearly saying it is the grid of switching transistor) of corresponding delegation on each address wire.The output of each holding wire is connected with analogue-to-digital converters, and the output of each A/D converter is connected with shift register.
In above-mentioned area image sensor, address wire is selected one at a time in turn.Thus from the imaging apparatus of the corresponding row of selecting of address wire to the A/D converter output signal voltage.A/D converter outputs to shift register with the picture signal of numeral after the signal voltage and reference voltage of relatively input.Shift register is output into shift pulse (data of this output are called " view data ") synchronously with the picture signal of numeral.
The view data of one frame (picture) is by scanning whole address wires fully, obtaining with the corresponding digital pixel signal of each imaging apparatus from shift register output.Therefore, be F for example at frame frequency
R(fps: frame/second), all the bar number of address wire is N
ASituation under, A/D converter needs substantially at 1/ (F
R* N
A) second about time (" cycle ") in the simulation signal voltage be transformed to digital pixel signal.
Usually, the cycle is short more, and the operating stably of A/D converter just has the tendency that is under some influence more.As mentioned above, the existing cycle is 1/ (F
R* N
A).So, F
RDuring increase (at N
ANecessarily), can not the bring into normal play problem of function of A/D converter might appear.
Summary of the invention
The present invention proposes in view of the above problems, and its purpose is to provide the operating stably that does not influence A/D converter, and can improve the area image sensor of frame frequency.
Area image sensor (matrix type imageing sensor) by a first aspect of the present invention provided has: be configured to rectangular a plurality of imaging apparatuss with forming a plurality of element rows and a plurality of element lines; Many signal line for each element line distribution in described a plurality of element lines; And a plurality of A/D converters that are connected with a corresponding signal line respectively; And the shift register that is connected with described a plurality of A/D converters.Each of imaging apparatus that belongs to described each element line, respectively only with described many signal line in arbitrary be connected, and described many signal line are connected with in the above-mentioned imaging apparatus that belongs to described each element line at least one separately, described shift register contains a plurality of registers of group that are divided into many signal line similar number of distributing to each element line, the a plurality of registers that belong to same group interconnect, and each register is connected with a signal line in an element line.
Preferred each imaging apparatus is made of the components of photo-electric conversion and the switch element that is connected in these components of photo-electric conversion.
Preferably, the above-mentioned imaging apparatus that belongs to described each element line comprises two imaging apparatuss that adjoin each other, in described two imaging apparatuss one with described many signal line in one be connected, another in described two imaging apparatuss is connected with in described many signal line another.
Preferably, the area image sensor of the present invention address wire that also comprises many address wires and be connected in these address wires is selected circuit.Each of described many address wires respectively with belong to described a plurality of element row in the imaging apparatus of a corresponding element row be connected, described address wire selects circuit to have many structure can selecting simultaneously in described many address wires.
According to a second aspect of the invention, provide the area image sensor that a plurality of imaging apparatuss is configured to multiple lines and multiple rows.This area image sensor has: the many signal line and the analog/digital converter that is connected to described each holding wire of distributing to the row or two row of imaging apparatus.In each row of described imaging apparatus, every imaging apparatus of crossing over the number identical with the distribution bar number of described holding wire continuously and arranging forms group, and simultaneously, in group, each imaging apparatus is connected to different holding wires.And in each row of described imaging apparatus, in this big group, there are two connection patterns for the holding wire of group unit in every cross over continuously more than two and the group of arranging forms big group at least.
Preferably, in each row of described imaging apparatus, every group number be 2 power several form big group when counting.
Preferably, in each row of described imaging apparatus, form different more than 2 kinds big groups of group's number.
Preferably, area image sensor of the present invention also has: respectively distribute 1 for each row of described imaging apparatus, utilize the whole address wires that connect of imaging apparatus in 1 this row, the address wire that can select many ground in these address wires to constitute is simultaneously selected circuit; Obtain the digital signal of exporting separately from described analog/digital converter, the shift register of simultaneously these digital signals being exported by many conveyer lines; And the two conversion switch circuits (duplexer) or the multi-path converter circuit that switch described conveyer line, output digital signal.
Signal voltage that preferred described analog/digital converter is relatively imported and set reference voltage, the count value during with two voltages unanimity outputs to described shift register as digital signal.
Description of drawings
Fig. 1 is the circuit diagram of expression based on the major part of the area image sensor of first embodiment of the invention.
Fig. 2 is the circuit diagram of the imaging apparatus of above-mentioned area image sensor.
Fig. 3 is the block diagram of the A/D converter of the above-mentioned imageing sensor of expression.
Fig. 4 A is the action sequential chart regularly of the above-mentioned A/D converter of explanation.
Fig. 4 B is the sequential chart of explanation for comparative example of the present invention.
Fig. 5 is another action sequential chart regularly of the above-mentioned A/D converter of explanation.
Fig. 6 is the circuit diagram of expression based on the major part of the area image sensor of second embodiment of the invention.
Fig. 7 is the circuit diagram of imaging apparatus of the area image sensor of Fig. 6.
Fig. 8 is the figure of the connection mode of explanation imaging apparatus.
Fig. 9 is the block diagram of employed A/D converter in the area image sensor of second embodiment.
Figure 10 is the figure of the above-mentioned A/D converter action of explanation.
Figure 11 is the figure of explanation signal processing sequence.
Figure 12 is the figure of another signal processing sequence of explanation.
Figure 13 is the figure of the further processing sequence of another signal of explanation.
Figure 14 is the circuit diagram of expression based on the major part of the area image sensor of third embodiment of the invention.
Figure 15 is the figure of connection mode of imaging apparatus in the area image sensor of explanation third embodiment of the invention.
Figure 16 A is the figure that signal processing sequence as a comparative example is described.
Figure 16 B is the figure of signal processing sequence in the area image sensor of explanation the 3rd embodiment.
Figure 17 is the figure of another signal processing sequence in the area image sensor of explanation the 3rd embodiment.
Figure 18 is the circuit diagram of expression based on the major part of the area image sensor of fourth embodiment of the invention.
Figure 19 is the figure of connection mode of imaging apparatus in the area image sensor of explanation fourth embodiment of the invention.
Figure 20 is the circuit diagram of expression based on the major part of the area image sensor of fifth embodiment of the invention.
Figure 21 is the figure of connection mode of imaging apparatus in the area image sensor of explanation fifth embodiment of the invention.
Figure 22 is the figure of the variation of explanation the 5th embodiment.
Figure 23 is the figure of the connection mode of imaging apparatus in the above-mentioned variation of explanation.
Embodiment
Specify embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is the pie graph of expression based on the CMOS profile type imageing sensor of first embodiment of the invention.Area image sensor 1 for example can be used as parts that constitute digital camera and uses, but the present invention is not limited to this.
Illustrated area image sensor 1 has the light accepting part 1A of rectangle, and this light accepting part comprises a plurality of photodiodes 10 and a plurality of switch elements 20.It is right that each photodiode 10 and a corresponding switch element 20 are combined into, and constitutes an imaging apparatus.The unit area that comprises this imaging apparatus is equivalent to a pixel.A plurality of imaging apparatuss are configured to rectangular.The vertical arrangement of imaging apparatus is called " row ", and horizontal arrangement is called " OK ".
Corresponding to imaging apparatus each row be provided with 4 signal line Lij (i, j=1,2,3 ...).For example, be provided with holding wire L11, L12, L13, L14 for the imaging apparatus of first row, each holding wire is connected with the output 20A of corresponding a plurality of switch elements.Equally, the imaging apparatus for secondary series is provided with holding wire L21, L22, L23, L24.The output of each holding wire is connected with analog/digital converter (A/D converter) 30, and the output of transducer 30 is connected with shift register 40.
And, corresponding to imaging apparatus each the row be provided with 1 address wire Ak (k=1,2,3 ...).For example, be provided with address wire A1 for the imaging apparatus of first row, this address wire is connected with the grid 20B of corresponding a plurality of switch elements.Equally, the imaging apparatus for second row is provided with address wire A2.Each address wire selects circuit (ASC) 50 to be connected with address wire.
Fig. 2 is the circuit diagram of imaging apparatus.Switch element 20 is by 3 transistors, promptly resets to follow to amplify with transistor T R2 and source electrode with transistor T R1, switch to constitute with transistor T R3.Resetting with transistor T R1 and switch is CMOS type device with transistor T R2.And every row is provided with reset line (symbol of first row is R1), and every row are provided with common wire (symbol of first row is C1) (these lines omit in Fig. 1).Reset with the source electrode of transistor T R1, grid, and drain electrode, be connected with output, reset line R1 and the common wire C1 of photodiode 10 respectively.Switch is with the source electrode of transistor T R2, grid, and drain electrode, respectively with common wire C1, address wire A1, and source electrode follow the source electrode that amplifies with transistor T R3 and be connected.Source electrode is followed the grid that amplifies with transistor T R3 and is connected with the output of photodiode 10, and drain electrode is connected with holding wire L11.Source electrode is followed and is amplified the output 20A that is equivalent to switch element 20 with the contact of the drain electrode of transistor T R3 and holding wire L11, and switch is equivalent to the input and output grid 20B of switch element 20 with the contact of the grid of transistor T R2 and address wire A1.When grid 20B is a "on" position, switch element 20 flows into holding wire L11 corresponding to the signal charge of light income from photodiode 10 when connecting (ON), by this holding wire to A/D converter 30 applied signal voltages.
Here, note belonging to the switch element 20 and holding wire L11～L14 of first row, see their annexation.Be arranged in the switch element 20 of first row, per 4 are connected in same holding wire.Particularly, 1+4n (n=0,1,2 ...) the output 20A of switch element 20 is connected in holding wire L11,2+4n switch element 20 is connected in holding wire L12.And the output 20A of 3+4n switch element 20 is connected in holding wire L13, and 4+4n switch element 20 is connected in holding wire L14 (also is same for other row).Adopt the technical meaning of this spline structure to narrate in the back.
Fig. 3 is the block diagram of primary structure of the A/D converter 30 of presentation video transducer.A/D converter 30 comprises comparator (CM) 31 and counter (CT) 32.By the signal voltage (Sv) of holding wire L input analog signal, import reference voltage (Rv) (with reference to Fig. 4 A) simultaneously in the comparator 31 with the proportional increase of Action clock.Reference voltage is to select each set selection cycle (cycle time (CTM)) of circuit 50 and import in address wire.The signal voltage Sv and the reference voltage Rv of input in the 31 compare cycle times of comparator import block signals in the moment of two voltage unanimities to counter 32.The number of counter 32 counting clocks when comparator 31 is accepted block signal, outputs to shift register 40 (Fig. 1) with the clock count (CCN) in this moment as digital pixel signal.
Address wire selects circuit 50 once to select 4 address wires respectively, makes with the corresponding imaging apparatus of these address wires to be in on-state.Particularly, circuit 50 is at first selected address wire A1～A4, makes with the corresponding imaging apparatus of these address wires to be in on-state (result is to transducer 30 output signal voltages from imaging apparatus).Then, through above-mentioned " CTM cycle time " afterwards, select address wire A5～A8, make with the corresponding imaging apparatus of these address wires to be in on-state.Below repeat this selection action.
Then, with reference to Fig. 4 A, 4B and Fig. 5 all actions of area image sensor 1 are illustrated.Fig. 4 A and Fig. 5 are the action sequential charts regularly of explanation A/D converter 30, and Fig. 4 B is the sequential chart for conventional example relatively.
At first, address wire selects circuit 50 to conclude the address wire A1～A4 that selects from first row to fourth line.Like this, the switch element 20 from first row to fourth line that is connected with these address wires A1～A4 is in on-state.Simultaneously, from the light-emitting diode 10 paired,, the signal voltage of light-to-current inversion is supplied to A/D converter 30 by a signal line of correspondence with each switch element of connecting 20.
Shown in Fig. 4 A, reference voltage Rv and signal voltage Sv that A/D converter 30 relatively increased in the CTM in cycle time.And the clock count CCN when consistent outputs to shift register 40 as data image signal and (during the address wire of fifth line to the eight row of this picture signal below selecting, exports from shift register 40 A/D converter 30 with both.)。
When the selection of address wire A1～A4 finishes,, first row is resetted to the photodiode 10 of fourth line by selecting the reset line (only having represented reset line R1 among Fig. 2) of first row to fourth line.On the other hand, then select the address wire of fifth line to the eight row, carry out and above-mentioned same processing.By repeating a series of like this action, can access view data with all corresponding frames of light accepting part 1A.
Here, for example consider that frame frequency is 60fps, all numbers of address wire are the situation of N.In this case, the processing time of each A/D converter 30 is 1 frame 1/60 second (in fact can produce some errors).And in this processing time, A/D converter 30 carries out N/4 time AD conversion.Thus, the needed time of AD conversion (cycle time) is 1/ (15 * N) seconds.On the other hand, according to existing mode (respectively selecting a signal line and an address wire), in the processing time (1/60 second) of a frame, amount to and carry out N time AD conversion for each row.So be 1/ (60 * N) seconds cycle time.
Like this, according to the present invention (Fig. 4 A), (Fig. 4 B) compares with conventional example, is increased to 4 times cycle time, can reduce the rate of change of one-period time internal reference voltage.Consequently, with the Action clock of A/D converter as identical situation under, the bit number of the digital pixel signal of each pixel increases (being that the tonal gradation number increases).
According to the present invention, making cycle time is that half shown in Fig. 4 A gets final product (Fig. 5).By shortening CTM cycle time, frame frequency is increased.In this case, cycle time of the present invention is also long than existing cycle time (Fig. 4 B), and the tonal gradation number of each pixel is more than existing.
And, according to the present invention,, also can realize and have now same or be higher than existing tonal gradation number even the Action clock of A/D converter is set lowlyer than existing.By lowering Action clock, have the advantage that can reduce consumption electric power in the A/D converter.
In the above-described embodiments, it is rectangular to be that a plurality of imaging apparatuss are arranged in, but the present invention is not limited to this.For example also can be that a plurality of imaging apparatuss are arranged in honeycomb.And, distribute to the bar number of holding wire of each row of imaging apparatus, also can be more than 5.
And, in the above-described embodiments, do not adjoin each other between switch element 20 that is connected with a signal line (for example holding wire L11) and the switch element 20.But, a plurality of switch elements that are connected with the same signal line configuration that also can adjoin each other.According to the explanation of example shown in Figure 1, the switch element 20 that belongs to first row (left column) is divided into 4 groups (first group to the 4th group), belongs to the configuration that adjoins each other of each switch element 20 of organizing.On this basis, the switch element 20 that for example belongs to first group is connected with holding wire L11, belong to simultaneously second group switch element 20 and holding wire L12, belong to the 3rd group switch element 20 and holding wire L13, the switch element 20 that belongs to the 4th group is connected respectively with holding wire L14.The switch element of each row is divided into several groups, and is relevant with the number that is listed as employed holding wire for this.For example, when using 5 signal line for row, the switch element 20 of these row is divided into 5 groups.Under these circumstances, belonging to same group plural switch element 20 (they are connected with common holding wire), must be the structure that can not be in on-state simultaneously.
A/D converter 30 also is not limited to be to use the mode of skewed reference voltage.For example, also can be the converter that compares type one by one.In this case, the reference voltage that digitally produces in applied signal voltage and the converter compares one by one.
Fig. 6 is the pie graph of expression based on the area image sensor of second embodiment of the invention.For in the inscape of the area image sensor of second embodiment with the identical or similar elements of inscape of the area image sensor of first embodiment, all use identical reference marks.About this point, also be same among Shuo Ming the 3rd to the 5th embodiment in the back.
As shown in Figure 6, area image sensor 1 with image pickup part 1A comprises a plurality of photodiodes 10, a plurality of switch element 20, a plurality of analog/digital converter (A/D converter) 30, shift register 40, address wire selection circuit 50, two conversion switch circuit 60, the holding wire L of longitudinal extension and the address wire A of horizontal expansion.
Fig. 7 is the circuit diagram of an imaging apparatus of expression.Switch element 20 is to follow amplification with transistor T R1, switch with transistor T R2 and source electrode by resetting to be constituted with transistor T R3.Reset and constitute by the CMOS structure with transistor T R2 with transistor T R1 and switch.And though omitted among Fig. 6, each row is provided with reset line R (symbol of first row is R1), and each row is provided with common wire C (symbol of first row is C1).Reset with the source electrode of transistor T R1, grid, and drain electrode, be connected with output, reset line R1 and the common wire C1 of photodiode 10 respectively, switch is with the source electrode of transistor T R2, grid, and drain electrode, respectively with common wire C1, address wire A1, and source electrode follow the source electrode that amplifies with transistor T R3 and be connected.Source electrode is followed the grid that amplifies with transistor T R3 and is connected with the output of photodiode 10, and drain electrode is connected with holding wire L11.Wherein, source electrode is followed and is amplified the output 20A that is equivalent to switch element 20 with the contact of the drain electrode of transistor T R3 and holding wire La1, and switch is equivalent to the input and output grid 20B of switch element 20 with the contact of the grid of transistor T R2 and address wire A1.In each pixel, when making input and output grid 20B make switch element 20 be in on-state, flow into holding wire from the signal charge after the light-to-current inversion of photodiode 10 as "on" position, by these holding wires to A/D converter 30 applied signal voltages.
Then,, note imaging apparatus and holding wire La1, the La2 of first row, be described in detail these regular pattern as an example.Also have,, also be suitable for and the identical regular pattern of first row for each row beyond first row.
Fig. 8 is the key diagram for the mode of rule that first row are described.As shown in the drawing, be arranged in the imaging apparatus P1～P32 in first row, every two continuous formation groups (g1, g2, g3 etc.), simultaneously, in a group, two adjacent imaging apparatuss are connected to different holding wire L1 (La1), L2 (La2).And every two continuous groups constitute a big group.For example, organizing G1 greatly is made of g1 of group and g2.Among the figure, " OM " means pattern, and " CF " means clock frequency, and " Px " means pixel, and " SL " means holding wire.And " 1 " expression is connected, and " 0 " expression disconnects.
Here, for example observe big group G1, for the holding wire L1 of the g1 of group that wherein comprises, the connection mode of L2, different respectively with connection mode for holding wire L1, the L2 of the g2 of group.This also is same for other big group of G2～G8.And in each big group, two imaging apparatuss that are positioned at 2n+1 (n=0,1) are connected to different holding wires.For example, in big group G1, P1 is connected to different holding wires with P3.And in big group G2, P5 is connected to different holding wires with P7.
And then, as shown in Figure 8, form bigger group G# 1 by G1 and G2.Group G# 1 comprises the (g1～g4) of the individual group in 4 (=22).Equally, form group G# 2, form group G# 3, form group G# 4 by G7 and G8 by G5 and G6 by G3 and G4.And, form bigger group G% 1 by G# 1 and G#2.Group G% 1 comprises 8 (=2
3) individual group (g1～g8).Equally, form group G% 2 by G# 3 and G#4.And, form bigger group G﹠amp by G% 1 and G% 2; 1.Group G﹠amp; 1 comprises 16 (=2
4) individual group (g1～g16).
As can be seen from Figure 8, to about the connection mode of the holding wire of group G# 1 with to identical about the connection mode of holding wire of group G# 4, to about the connection mode of the holding wire of group G# 2 with identical to connection mode about the holding wire of organizing G#3.But, to about the connection mode of the holding wire of group G# 1 with different to connection mode about the holding wire of organizing G#2.In group G# 1, two imaging apparatuss (P1 and P5) that are positioned at 4n+1 (n=0,1) are connected to different holding wire La1, La2.Similarly, in group G# 2, two imaging apparatuss (P9 and P13) that are positioned at 4n+1 (n=0,1) are connected to different holding wire La1, La2.
And then in group G% 1, two imaging apparatuss (P1 and P9) that are positioned at 8n+1 (n=0,1) are connected to different holding wire La1, La2.Similarly, in group G% 2, two imaging apparatuss (P17 and P25) that are positioned at 8n+1 (n=0,1) are connected to different holding wire La1, La2.And, at group G﹠amp; In 1, two imaging apparatuss (P1 and P17) that are positioned at 16n+1 (n=0,1) are connected to different holding wire La1, La2.
According to such mode of rule, under the situation of carrying out gross sample scanning (extracting signal out) from whole imaging apparatuss, each group (two imaging apparatuss that comprised among the g1～g32) (be the right of P1 and P2, P3 and P4's is right, etc.) be on-state simultaneously.Particularly, at first P1, P2 are on-state simultaneously, make the signal voltage for first row and second row be input to A/D converter 30 simultaneously by holding wire.Then, be on-state in the time of by P3, P4, make signal voltage be input to A/D converter 30 (also is same for other row) simultaneously by holding wire for the third line and fourth line.
Carrying out (1/2 sampling scanning) under the address wire selection scan condition between two according to the ratio of alternative, in group G1, imaging apparatus P1, P3 are on-state simultaneously, and in group G2, imaging apparatus P5, P7 are on-state simultaneously.Like this, the signal voltage of two row parts is just by holding wire while input a/d converter 30.
And, carrying out under the 1/4 sampling scan condition, in group G# 1, imaging apparatus P1, P5 are on-state simultaneously, in group G# 2, imaging apparatus P9, P13 are on-state simultaneously.Equally, carrying out under the 1/8 sampling scan condition, in group G% 1, imaging apparatus P1, P9 are on-state simultaneously, and in group G% 2, imaging apparatus P17, P25 are on-state simultaneously.And, carrying out under the 1/16 sampling scan condition, at group G﹠amp; In 1, imaging apparatus P1, P17 are on-state simultaneously.
As shown in Figure 9, each A/D converter 30 comprises comparator 31 and counter 32.As shown in figure 10, in the comparator 31 by holding wire input as analog signal and the signal voltage (the picture in picture indicating goes out) of sampled maintenance, the reference voltage of input simultaneously and the proportional tilt variation of Action clock.Signal voltage and reference voltage that comparator 31 is relatively imported are imported block signals in the moment of two voltage unanimities to counter 32.The number of counter 32 counting clocks when comparator 31 is accepted block signal, outputs to shift register 40 with the clock count in this moment as digital pixel signal.
As shown in Figure 6, shift register 40 is provided with register 41.Each register 41 is connected with the output of A/D converter 30.Form corresponding with the output of the A/D converter 30 of two of every row of register 41 is provided with by two sections, is connected in the first conveyer line 42A for corresponding one group with holding wire L1, is connected in the second conveyer line 42B for corresponding one group with holding wire L2.Such shift register 40, synchronous with shift pulse after will depositing each register 41 in from the digital pixel signal of each A/D converter 30 temporarily, transmit digital pixel signal one by one by two conveyer line 42A, 42B.At this moment, conversion switch circuit 60 is interlock with the action of shift register 40, with suitable moment switching conveyer line 42A, 42B.For example, conversion switch circuit 60 with state that the first conveyer line 42A is connected under export digital pixel signal on the first conveyer line 42A in turn.After this output is over, switches to the second conveyer line 42B and be connected, export the digital pixel signal on the second conveyer line 42B in turn.Like this, the digital pixel signal of going by shift register 40 serials output two.
Then, with reference to Figure 11～Figure 13, the action of area image sensor 1 is illustrated.In order to understand operating principle easily, suppose that image pickup part 1A has 4 row, 4 row and amounts to 16 pixels.
Figure 11 scans the gross sample that address wire A1～A4 selects to scan one by one as pattern.Also have, this pattern is a comparative example, is not based on the present invention.On the other hand, Figure 12 is the gross sample scanning that two scannings are selected in expression at every turn simultaneously, and Figure 13 is that expression is to select 1/2 sampling scanning of one each two scannings simultaneously of ratio in two.Express time flow chart in the epimere of each figure, the action of pattern ground expression shift register in the hypomere.
As shown in figure 11, selecting based on address wire under the each situation of selecting scan address line A1～A4 in turn of signal ASS, address wire select circuit 50 by judgment frame signal FS (F1, F2, F3 ...) and select address wire A1-A4 in turn.Here so-called frame signal is meant the signal that is used to provide the timing that is taken into 1 frame image data periodically.The frequency of frame signal is consistent with frame frequency.
When having selected an address wire A1, the switch element 20 of first row that is connected with this address wire A1 is on-state, from the photodiode 10 paired, supply with the signal voltage of light-to-current inversions to A/D converter 30 by holding wire simultaneously with the switch element connected 20.In Figure 11, " OD " means dateout.And " F11 " is the dateout that expression is exported when having selected address wire A1 for frame signal F1.Similarly, " F23 " is the dateout that expression is exported when having selected address wire A3 for frame signal F2.
Skewed reference voltage when as shown in figure 10, the relatively more each selection of A/D converter 30 scans and the signal voltage of analog input.Clock count when consistent outputs to shift register 40 as digital pixel signal to A/D converter 30 with both.Shift register 40 output digital pixel signals are until selection scanning end of a period once., similarly in turn select address wire A2, A3, A4, from the digital pixel signal of shift register 40 for each each row of selection scanning output thereafter.In other words, address wire shown in Figure 11 selects the one-period of signal ASS and dateout partly to be equivalent to line period, finish the processing of 1 frame by 4 line periods, according to such gross sample scanning, A/D converter 30 must carry out the AD conversion process for per 1 frame 4 times, and also correspondence becomes high frequency to Action clock (clock frequency) therewith.The clock frequency of this moment is " f ".
Then, consider each gross sample scanning of selecting the reality of two address wire A1～A4 of scanning (frame frequency and above-mentioned be identical conditions).In this case, as shown in figure 12, address wire selects circuit 50 to select two address wires (A1 and A2, A3 and A4) simultaneously when the judgment frame signal, scans.
Particularly, be on-state by first, second switch element of going 20 of selecting address wire A1, A2 at first simultaneously, make to be connected in these address wires.Consequently, from the photodiodes 10 of paired two row of the switch element 20 that is in on-state, by holding wire signal voltage is supplied to A/D converter 30.
A/D converter 30 is for selecting benchmark voltage and signal voltage each time, and the clock count during with two voltages unanimity outputs to shift register 40 as data image signal.The data image signal of shift register 40 outputs two row is until selection end of a period once.Similarly simultaneously select address wire A3, A4, from the data image signal of shift register 40 outputs two row thereafter.This situation address wire shown in Figure 12 selects the one-period of signal and dateout partly to be equivalent to line period, by the processing of the frame that finishes two line periods.
Here, the difference that scans with foregoing gross sample is, is the data image signals that obtained two row by selection once.And, as shown in figure 12, owing to shift register 40 is to switch conveyer line 42A, 42B by conversion switch circuit 60 in line period, so it is also different by this conversion switch circuit 60 this point to be exported in the serial of two digital pixel signals of going.At this moment, conversion switch circuit 60 switches conveyer line 42A, 42B, makes from the digital pixel signal of shift register 40 to export according to the order of row.
In other words, according to gross sample scanning of the present invention, by the AD conversion process of A/D converter 30, each frame carries out twice.Consequently, can set line period longer, making clock frequency be than about the low f/2 of the gross sample scanning of front.
And then, consider 1/2 inferior gross sample scanning of frame frequency and above-mentioned similarity condition.In this case, as shown in figure 13, when address wire is selected circuit 50 each judgement frame signal F1, F2, select scanning and interior 2n+1 (n=0,1) corresponding address wire A1, the A3 of group G1 simultaneously.When selecting two address wire A1, A3 simultaneously, be connected with these address wires A1, A3 first, the switch element of the third line 20 is on-state.Simultaneously, from the photodiodes 10 of paired two row of the switch element 20 that is in on-state, by holding wire L1, L2 the signal voltage of light-to-current inversion is supplied to A/D converter 30.
A/D converter 30 outputs to shift register 40 for selecting each time with data image signal.The data image signal of shift register 40 outputs two row is until selection end of a period once.Because this situation address wire shown in Figure 13 selects the one-period of signal and dateout partly to be equivalent to line period, so by the processing of the frame that finishes a line period.
In 1/2 such sampling scanning, be the data image signal that obtains two row by selection scanning once, but this data image signal is the data every delegation.In other words, as shown in figure 13, owing to shift register 40 is to switch conveyer line 42A, 42B by conversion switch circuit 60 in line period, so export by the digital pixel signal serial of these conversion switch circuit 60 interlacing.At this moment, even in the digital pixel signal of delegation, also as shown in figure 13, the digital pixel signal of the second, the 4th row goes out of use.Therefore, finally extract the data image signal of 4 pixels out from 16 pixels of 4 row, 4 row, the data volume of a frame is 1/4 of gross sample scanning.
Like this, according to 1/2 sampling scanning, by the AD conversion process of A/D converter 30, each frame can be set line period longer by once finishing, and making clock frequency is f/4.Based on same principle,, can make clock frequency be respectively f/8, f/16, f/32 according to 1/4,1/8,1/16 sampling scanning.
Describing with reference to Fig. 8 again, during gross sample scanning, because two row of two row of every every P1, P2 and P3, P4 obtain view data, is f/2 so can make clock frequency.
And, during 1/2 sampling scanning,, be f/4 so can make clock frequency owing to be that two row of every P1, P3 and two row of P5, P7 obtain view data.
And then, during 1/4 sampling scanning,, be f/8 so can make clock frequency owing to be that two row of every P1, P5 and two row of P9, P13 obtain view data.
Further, owing to be that two row of every P1, P9 and two row of P17, P25 obtain view data, be f/16 so can make clock frequency.
When 1/16 sampling of sampling rate minimum scans,, be about f/32 so can make clock frequency owing to be that two row of every P1, P17 and two row of P33, P49 (P33 illustrates omission later on) obtain view data.
So, according to this form of implementation, for example when 1/2 sampling scanning, the Action clock (clock frequency) that scans the A/D converter 30 under the address wire A situation with each selection is compared, this Action clock can be decremented to f/4, so, can reduce the consumption of electric power significantly by Action clock and the proportionate relationship that consumes electric power.
And when 1/4 sampling scanning, Action clock can be decremented to f/8, and consumption electric power can access significantly and successively decrease.If 1/8,1/16 sampling scanning then can obtain better effect on conservation of power.
And, if balance is adjusted the Action clock of A/D converter 30 when taking a sample scanning well, or the line period of address wire selection circuit 50, then can realize high frame frequencyization simultaneously and save electric power.
Figure 14 is the pie graph of expression third embodiment of the invention mesoprosopy imageing sensor.In the 3rd embodiment, each row imaging apparatus P is provided with 4 signal line.Mode of rule according to following explanation on these holding wires is connected with imaging apparatus P.
Figure 15 is the key diagram of the regular pattern of first row in the explanation third embodiment of the invention.As shown in the drawing, be arranged in first row imaging apparatus (P1, P2 ...) every continuous group of 4 formations (g1, g2 ...), 4 imaging apparatuss are connected to different holding wire L1～L4 in a group simultaneously.Two continuous groups form a big group (g1 and g2 form G1 etc.).
For example notice group G1, the connection mode of the g1 of group that wherein comprises for holding wire L1～L4, different separately with the connection mode for holding wire L1～L4 of the g2 of group (other group G2, G3 ... also be same).To 2n+1 of being positioned at each group G1, G2... (n=0,1,2,3 ...) 4 imaging apparatuss (P1, P3, P5, P7 and P9, P11, P13, P15), be connected to different holding wire L1～L4.
According to the understanding of Figure 15, in group G# 1, to be positioned at 4n+1 (n=0,1,2,3 ...) 4 imaging apparatuss (P1, P5, P9, P13), be connected to different holding wire L1～L4.Equally, in group G# 2, to be positioned at 4n+1 (n=0,1,2,3 ...) 4 imaging apparatuss (P17, P21, P25, P29), be connected to different holding wire L1～L4.And then, in group G% 1, to be positioned at 8n+1 (n=0,1,2,3 ...) 4 imaging apparatuss (P1, P9, P17, P25) of rule ordering, be connected to different holding wire L1～L4.
According to such mode of rule, carrying out in order to extract out from whole imaging apparatuss under the gross sample scan condition of signal, imaging apparatus P1～P4 and imaging apparatus P5～P8 are on-state simultaneously, and the signal voltage of continuous 4 row can be transported to A/D converter 30 simultaneously by holding wire.On the other hand, select the 1/2 sampling scan condition of an address wire A from two under, can make imaging apparatus P1, P3, P5, P7 in the group G1 be on-state simultaneously, imaging apparatus P9, P11, P13, P15 in the group G2 are on-state simultaneously.In other words, even under 1/2 sampling scan condition, also can 4 voltages of going be input to A/D converter 30 simultaneously by holding wire.
And, carrying out under the 1/4 sampling scan condition, in group G# 1, can make imaging apparatus P1, P5, P9, P13 be on-state simultaneously, simultaneously, in group G# 2, can make imaging apparatus P17, P21, P25, P29 be on-state simultaneously.
Carrying out under the 1/8 sampling scan condition, can make group G% 1 interior imaging apparatus P1, P9, P17, P25 be on-state simultaneously.
As shown in figure 14, the register 41 of shift register 40, be connected in the first conveyer line 42A for corresponding one group with holding wire L1, be connected in the second conveyer line 42B for corresponding one group with holding wire L2, be connected in the 3rd conveyer line 42C for corresponding one group with holding wire L3, be connected in the 4th conveyer line 42D for corresponding one group with holding wire L4.In other words, shift register 40 can with shift pulse synchronously, transmit digital pixel signal one at a time by 4 conveyer line 42A, 42B, 42C, 42D.At this moment, the action interlock of multicircuit switch circuit 61 and shift register 40 is with suitable moment switching 4 conveyer line 42A, 42B, 42C, 42D.For example, multicircuit switch circuit 61 is exported after the digital pixel signal on the first conveyer line 42A one by one in order, switch to the connection of the second conveyer line 42B, the output digital pixel signal, and then switch to the connection of the 3rd conveyer line 42C, switch to the connection of the 4th conveyer line 42D at last, the output digital pixel signal.Thus, by the serialized 4 line number word picture element signals of 40 pairs of every line outputs of shift register.
Then the action to the 3rd embodiment is illustrated.Also have, in order to understand operating principle easily, imaging apparatus only amounts to 48 pixels by 8 row, 6 row shown in Figure 14 and is constituted.The peripheral circuit of A/D converter 30 and shift register 40 also is corresponding therewith formation.
Figure 16 and Figure 17 are for the key diagram of signal processing sequence is described.Particularly, Figure 16 A is and selects the gross sample of scan address line A1～A8 to scan corresponding time chart one by one as pattern, Figure 16 B scans corresponding time chart with each gross sample of 4 of scannings of selecting simultaneously, and Figure 17 is and the corresponding time chart of 1/2 sampling scanning of at every turn selecting 4 of scannings in the ratio of selecting 1 in 2 simultaneously.Also have, Figure 16 A only is in order to compare with reference to usefulness, in fact not have each pattern of selecting an address wire A of scanning.
Suppose that under the gross sample scan condition of carrying out a selective sequential scan address line A1～A8 shown in Figure 16 A, address wire is selected circuit 50 selective sequential scan address line A1～A8 when at every turn judging frame signal.
When selecting address wire A1 of scanning, the imaging apparatus of first row that is connected with this address wire A1 is an on-state.Simultaneously, supply with signal voltage by holding wire La1, Lb1 to A/D converter 30 from the imaging apparatus that is in on-state.
A/D converter 30 outputs to shift register 40 with digital pixel signal.Shift register 40 output digital image signals are until selection scanning end of a period once., similarly in turn select scan address line A2, A3 etc., from the data image signal of shift register 40 for each each row of selection scanning output thereafter.Address wire shown in Figure 16 A selects the one-period of signal and dateout partly to be equivalent to line period, by the processing of the frame that finishes 8 line periods.A/D converter 30 must carry out the AD conversion process 8 times for a frame, and also correspondence becomes high frequency to Action clock (clock frequency) therewith.
Then, consider frame frequency and above-mentioned same condition, each 4 gross sample scannings of the present invention of selecting scan address line A1～A8.In this case, shown in Figure 16 B, address wire selects circuit 50 whenever to select scan address line A1～A4 and A5～A8 simultaneously when judging frame signal.
At first, when selecting 4 address wire A1 of scanning～A4 simultaneously, the first imaging apparatus P to fourth line that is connected with these address wires A1～A4 is an on-state.Simultaneously, supply with signal voltage by holding wire L1～L4 to A/D converter 30 from the imaging apparatus P that is in on-state.
A/D converter 30 outputs to shift register 40 with data image signal.The data image signal of shift register 40 outputs 4 row is until selection scanning end of a period once., similarly simultaneously select scan address line A5～A8, from the digital pixel signal of shift register 40 outputs 4 row thereafter.In this case, address wire shown in Figure 16 B selects the one-period of signal and dateout partly to be equivalent to line period, by the finish processing of a frame of 2 scan periods.
Here, the difference that scans with foregoing gross sample is, is the data image signals that obtained 4 row by selection scanning once.And, owing to shift register 40 is to switch conveyer line 42A, 42B, 42C, 42D by multicircuit switch circuit 61 in line period, so export the digital pixel signal of 4 row by these multicircuit switch circuit 61 serials.Also have, multicircuit switch circuit 61 switches conveyer line 42A, 42B, 42C, 42D, makes from the digital pixel signal of shift register 40 to export according to the order of row.For example, in the stage (the selection sweep phase of address wire A1～A4) of 4 initial row of output, conveyer line switches to the order of 42A, 42B, 42C, 42D, in the stage (the selection sweep phase of address wire A5～A8) of next one output 4 row, conveyer line switches to the order of 42B, 42C, 42D, 42A.According to above-mentioned gross sample scanning, by the AD conversion process that A/D converter 30 is carried out, each frame carries out twice.Consequently, can set line period longer, making clock frequency be than about the low f/4 of the gross sample scanning of front.
And then, consider that frame frequency and 1/2 inferior gross sample of above-mentioned same condition scan.In this case, as shown in figure 17, address wire select circuit 50 each when judging frame signal in the G1 of selection group simultaneously with 2n+1 (n=0,1,2,3) corresponding address wire A1, A3, A5, A7.
When selecting scanning 4 address wire A1, A3, A5, A7 simultaneously, the imaging apparatus P of the first, the 3rd, the 5th, the 7th row that is connected with these address wires A1, A3, A5, A7 is an on-state.Simultaneously, supply with signal voltage by holding wire L1～L4 to A/D converter 30 from the imaging apparatus P that is in on-state.
A/D converter 30 is for selecting scanning that data image signal is outputed to shift register 40 each time.The data image signal of shift register 40 outputs 4 row is until selection scanning end of a period once.In this case, because address wire shown in Figure 17 selects the one-period of signal and dateout partly to be equivalent to line period, so by the finish processing of a frame of 1 scan period.
In 1/2 such sampling scanning, though be the data image signal that is obtained 4 row by selection scanning once, this data image signal that obtains is the signal every delegation.Because shift register 40 is to switch conveyer line by multicircuit switch circuit 61 with the order of symbol 42A, 42B, 42C, 42D in line period, so the digital pixel signal serial output by these multicircuit switch circuit 61 interlacing.At this moment, even in the digital pixel signal of delegation, the digital pixel signal of the second, the 4th, the 6th row goes out of use.Therefore, finally extract the digital pixel signal of 12 pixels out from 48 pixels of 8 row, 6 row, the data volume of a frame is 1/4 of gross sample scanning.
Like this, according to the 1/2 sampling scanning of the 3rd embodiment, by the AD conversion process of A/D converter 30, each frame can be set line period longer by once finishing, and making clock frequency is f/8.Based on same principle, according to 1/4,1/8 sampling scanning, can make clock frequency is about f/16, f/32.
Then the 4th embodiment is illustrated.Figure 18 is the pie graph of the area image sensor of the 4th embodiment.The area image sensor of the 4th embodiment is the transducer that is applicable to colored input mode.Be provided with in each imaging apparatus with the RGB three primary colors in colour filter of the same colour.Particularly, the camera element unit that is listed as by 2 row 2 shown in the imaginary line is a pixel, and as an example, colour filter can be that the upper left G of being, the upper right R of being, lower-left are that B, bottom right are the configuration of G.In such structure, each imaging apparatus is called " sub-pixel ".So a pixel is equivalent to 4 sub-pixels.
In the 4th embodiment, identical with the 3rd embodiment about the number (4) of the holding wire L of each row.And holding wire is different with the 3rd embodiment with the connection mode of imaging apparatus.
Figure 19 is for the figure for the connection mode of the imaging apparatus (sub-pixel SPX) of first row among the 4th embodiment is described.The formation and the 3rd embodiment of the imaging apparatus group of the 4th embodiment are same.From this figure as can be known, about each group (g1, g2 ...) the holding wire connection mode only have two kinds.Particularly, about the g1 of each group, g4, g6, g7, connection mode is [L1 → L2 → L3 → L4].And about the g2 of each group, g3, g5, g8, connection mode is [L3 → L4 → L1 → L2].According to such structure, in each big group of Gi, 4 imaging apparatuss that are positioned at 4n+1,4n+2 (n=0,1) are connected to different holding wire L1～L4.Particularly, in big group G1, imaging apparatus P1, P2, P5, P6 are connected to different holding wire L1～L4.And, organizing greatly in the G2, imaging apparatus P9, P10, P13, P14 are connected to different holding wire L1～L4.
And then in each group G# 1, G# 2,4 imaging apparatuss that are positioned at 8n+1,8n+2 (n=0,1) are connected to different holding wire L1～L4.Particularly, about group G# 1, imaging apparatus P1, P2, P9, P10 are connected to different holding wire L1～L4, and about group G# 2, imaging apparatus P17, P18, P25, P26 are connected to different holding wire L1～L4.And in by the group shown in the symbol G% 1,4 imaging apparatuss (P1, P2, P17, P18) that are positioned at 16n+1,16n+2 (n=0,1) are connected to different holding wire L1～L4.
According to such mode of rule,, identical with the 3rd embodiment carrying out for the action under the gross sample scan condition of extracting signal from whole imaging apparatuss out.On the other hand, carrying out selecting one ratio to select under the 1/2 sampling scan condition of scan address line A in 2, each big group of G1, G2 ... in be positioned at first, second, the 5th, the 6th imaging apparatus is on-state simultaneously.In other words, even 1/2 sampling scanning also can be input to A/D converter 30 with 4 signal voltages of going simultaneously by holding wire.
And, carrying out under the 1/4 sampling scan condition, can make in each big group of G# 1, G# 2 be positioned at first, second, the 9th, the tenth imaging apparatus (P1, P2, P9, P10 and P17, P18, P25, P26) is on-state simultaneously.
Carrying out under the 1/8 sampling scan condition, can make each group in the G% 1 be positioned at first, second, the 17, eighteenth imaging apparatus P1, P2, P17, P18 be on-state simultaneously.In other words, even 1/2,1/4,1/8 sampling scanning also can be input to A/D converter 30 with 4 signal voltages of going together by holding wire L.
Under the gross sample scan condition, address wire selects circuit 50 to select 4 address wires (A1～A4, A5～A8), become "on" position simultaneously.On the other hand, under 1/2 sampling scan condition, address wire is selected circuit 50 limits to divide by unit and is organized G1 greatly, the G2 limit selects to organize greatly 4 address wires (A1, A2, A5, A6) corresponding to 4n+1 and 4n+2 (n+0,1) in G1, the G2 simultaneously, becomes "on" position.And under 1/4 sampling scan condition, address wire is selected 4 address wires (symbol omission) corresponding to 8n+1 and 8n+2 (n+0,1) in circuit 50 selection groups simultaneously G#1, the G#2, becomes "on" position.And then under 1/8 sampling scan condition, address wire is selected 4 address wires (symbol omission) corresponding to 16n+1 and 16n+2 (n+0,1) in the circuit 50 selection groups simultaneously G%1, becomes "on" position.In other words, in gross sample scanning, 1/2,1/4,1/8 sampling scanning, under any one situation, all be every selection run-down, can make 4 address wire A be in on-state simultaneously.
Then, the action of the 4th embodiment is illustrated, also has, about action regularly, identical with the content of Figure 16 corresponding among the 3rd embodiment and Figure 17.
As the pattern of the 4th embodiment, consider the 1/2 inferior gross sample scanning of frame frequency and gross sample scanning for identical conditions.In this case, address wire selects circuit 50 for judging that each time frame signal selects to scan address wire A1, A2, A5, the A6 corresponding to 4n+1 and 4n+2 (n+0,1) in the big group of G1 simultaneously.
When selecting scan address line A1, A2, A5, A6 simultaneously, the imaging apparatus P of the 1st, the 2nd, the 5th, the 6th row that is connected with these address wires A1, A2, A5, A6 is an on-state.Simultaneously, supply with signal voltage by holding wire L1～L4 to A/D converter 30 from the imaging apparatus P that is in on-state.
A/D converter 30 outputs to shift register 40 with data image signal.The data image signal of shift register 40 outputs 4 row is until selection scanning end of a period once.Among big group G2s repeat same action thereafter.So, even 1/2 such sampling scanning is also same with the 3rd embodiment of front, by the processing of the frame that finishes 1 line period.And the data volume of 1 frame is equivalent to 1/4 of gross sample scanning.Like this, the Action clock (clock frequency) about A/D converter 30 becomes about f/8.
And, according to the principle same with the 3rd embodiment,, if carry out 1/4,1/8 sampling scanning, can make clock frequency separately is f/16 and f/32.
And, carrying out for 1/2 when scanning sampling, so clock frequency is about f/8 owing to be that 4 of 4 row of the every P1, the P2 that are connected in unlike signal line L1～L4, P5, P6 and every P9, P10, P13, P14 capablely obtains pixel data.
And then, in 1/4 when scanning sampling, owing to be that 4 row of 4 row of every P1, P2, P9, P10 and every P17, P18, P25, P26 obtain pixel data, so clock frequency is about f/16.
1/8 when scanning sampling of sampling rate minimum, owing to be that 4 row (P33 illustrates omission later on) of 4 row of the every P1, the P2 that are connected to unlike signal line L1～L4, P17, P18 and P33, P34, P49, P50 obtain pixel data, so clock frequency is f/32.
And then the 5th embodiment is illustrated.
Figure 20 is the pie graph of the area image sensor of the 5th embodiment.The area image sensor of the area image sensor of the 5th embodiment and the 4th embodiment is same, is the transducer that is applicable to colored input mode.The trichromatic color filter arrangement of RGB is the pattern same with Figure 18, by pixel of imaging apparatus (sub-pixel) formation of 2 row, 2 row shown in the illusion line.
In the 5th embodiment, be assigned 8 signal line L1～L8 (holding wire of 1 row is 4) for 2 row.
Figure 21 is for the key diagram of the mode of rule of first row among the 5th embodiment is described.In the 5th embodiment, same with the 4th embodiment aspect the formation of group.On the other hand, it is all to note being limited to first row that are listed as, about group (g1, g2 etc.), although have 4 kinds for the connection mode of unit signal line L1～L8, but wherein two kinds is to be object with holding wire L1～L4 only, and other two kinds is to be object with holding wire L5～L8 only.Therefore, 4 imaging apparatus P1, P2, P5, P6 and P9, P10, P13, P14 to 4n+1, the 4n+2 (n=0,1) that are positioned at each big group (G1, G2), can be corresponding to holding wire L1～L4, or among holding wire L5～L8 any one group, be connected to different holding wires (L1～L4, L5～L8).
And, to 4 imaging apparatus P1, P2, P9, the P10 of 8n+1, the 8n+2 (n=0,1) that are positioned at big group of G# 1 and be positioned at 4 imaging apparatus P17, P18, P25, the P26 of 8n+1, the 8n+2 (n=0,1) of big group of G# 2, be connected to different holding wire L1～L8.
And then 4 imaging apparatuss (P1, P2, P17, P18) to the rule ordering of 16n+1, the 16n+2 (n=0,1) that are positioned at big group of G% 1 are connected to different holding wire L1～L4.
And, as shown in figure 20, being listed as all connection modes, first row of odd number are classified same pattern as with the 3rd, and the secondary series of even number and the 4th is classified same pattern as.Like this, first adjacent row and the secondary series, the connection mode of just formation symmetry between the 3rd row and the 4th row.
According to such mode of rule, also can realize the action same with the 4th embodiment.So, carrying out under 1/2,1/4, the 1/8 sampling scan condition, corresponding with sampling scanning separately, the signal voltage of 4 row is input to A/D converter 30 together by 4 among 8 signal line L1～L8.
When gross sample scans, owing to the per 4 row P1～P4 and the P5～P8 that are formation group obtain pixel data, so clock frequency is about f/4.
And, in 1/2 when scanning sampling, owing to be that 4 of 4 row of the P1, the P2 that at every turn are connected in unlike signal line L1～L8, P5, P6 and P9, P10, P13, P14 capablely obtains pixel data, so clock frequency is about f/8.
And then, when 1/4 sampling scanning, owing to be that each big group of G# 1, G# 2 are divided, 4 capable and obtain pixel data according to 4 row of the P1 that is connected to unlike signal line L1～L8, P2, P9, P10, P17, P18, P25, P26 at every turn is so clock frequency is about f/16.
When 1/8 sampling of sampling rate minimum scans, owing to be capablely to obtain pixel data, so clock frequency is f/32 according to 4 of 4 row of the every P1, the P2 that are connected to unlike signal line L1～L4, P17, P18 and P33, P34, P49, P50 (P33 illustrates omissions later on).
Also have,, go back Figure 22 and structure shown in Figure 23 as the variation of the 5th embodiment.
In such variation, also be to dispose 8 signal line for 2 row, the holding wire of per 1 row has 4.As with the difference of the 5th embodiment of front, two relative pixel element P connect with respect to adjacent holding wire.Therefore, to being positioned at 4 imaging apparatuss (P1, P2, P5, P6 and P9, P10, P13, P14) of each big group of G1, G2 4n+1,4n+2 (n=0,1), with odd column holding wire L1, L3, L5, L7 or even column holding wire L2, L4, L6, L8 any one group corresponding, be connected to different holding wire (L1, L3, L5, L7 and L2, L4, L6, L8).
And, note represented big group by symbol G# 1, G# 2, to being positioned at 4 imaging apparatuss (P1, P2, P9, P10 and P17, P18, P25, P26) of each big group of 8n+1,8n+2 (n=0,1), be connected to different holding wire L1～L8.
To being positioned at 4 imaging apparatuss (P1, P2, P17, P18) of big group of G% 1 16n+1,16n+2 (n=0,1), be connected to different holding wire L1, L3, L5, L7.
Even such connection mode also can be realized the same action with front the 5th embodiment.
Under the situation of colored input mode, the colour filter of each imaging apparatus also can be the colour filter that is decomposed into the complementary color system of YMC and G.
More than be the explanation that the present invention is done, obviously also it can be changed into other form.The change of being done does not exceed requirement of the present invention and scope, and whole changes that the colleague is done all should comprise within the scope of the claims.
Claims (4)
1. an area image sensor is characterized in that, its structure has:
Be configured to rectangular a plurality of imaging apparatuss with forming a plurality of element rows and a plurality of element lines;
Many signal line for each element line distribution in described a plurality of element lines;
A plurality of A/D converters that are connected with a corresponding signal line respectively; With
The shift register that is connected with described a plurality of A/D converters,
Each imaging apparatus that belongs to described each element line, respectively only with described many signal line in arbitrary be connected, and each of described many signal line be connected with at least one of the described imaging apparatus that belongs to described each element line,
Described shift register contains a plurality of registers of group that are divided into many signal line similar number of distributing to each element line, and a plurality of registers that belong to same group interconnect, and each register is connected with a signal line in an element line.
2. transducer according to claim 1 is characterized in that:
Each imaging apparatus is made of the components of photo-electric conversion and the switch element that is connected in these components of photo-electric conversion.
3. transducer according to claim 1 is characterized in that:
The described imaging apparatus that belongs to described each element line comprises two imaging apparatuss that adjoin each other, in described two imaging apparatuss one with described many signal line in one be connected, another in described two imaging apparatuss is connected with in described many signal line another.
4. transducer according to claim 1 is characterized in that:
Select in the structure of circuit in many address wires of tool also and the address wire that is connected in these address wires, each of described many address wires respectively with belong to described a plurality of element row in the imaging apparatus of a corresponding element row be connected, described address wire selects circuit to have many structure can selecting simultaneously in described many address wires.
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| Application Number | Priority Date | Filing Date | Title |
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| JP2002298667A JP2004135136A (en) | 2002-10-11 | 2002-10-11 | Area image sensor |
| JP298667/2002 | 2002-10-11 | ||
| JP321014/2002 | 2002-11-05 |
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| CN1703902A CN1703902A (en) | 2005-11-30 |
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| WO1986001678A2 (en) * | 1984-09-10 | 1986-03-27 | Eastman Kodak Company | Single-chip solid-state color image sensor and camera incorporating such a sensor |
| US5153731A (en) * | 1989-12-18 | 1992-10-06 | Olympus Optical Co., Ltd. | Solid state image pick-up device and apparatus capable of providing filtering output with direct and real time manner |
| US5990948A (en) * | 1996-02-29 | 1999-11-23 | Kabushiki Kaisha Toshiba | Noise cancelling circuit for pixel signals and an image pickup device using the noise cancelling circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1986001678A2 (en) * | 1984-09-10 | 1986-03-27 | Eastman Kodak Company | Single-chip solid-state color image sensor and camera incorporating such a sensor |
| US5153731A (en) * | 1989-12-18 | 1992-10-06 | Olympus Optical Co., Ltd. | Solid state image pick-up device and apparatus capable of providing filtering output with direct and real time manner |
| US5990948A (en) * | 1996-02-29 | 1999-11-23 | Kabushiki Kaisha Toshiba | Noise cancelling circuit for pixel signals and an image pickup device using the noise cancelling circuit |
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| CN1703902A (en) | 2005-11-30 |
| JP2004135136A (en) | 2004-04-30 |
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