JP2006074367A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device capable of improving an SN ratio by facilitating read scanning when executing thinning-out read operation in the solid-state imaging device. <P>SOLUTION: The solid-state imaging device has a pair of capacitor elements which is connected in parallel between each of vertical transfer parts and one horizontal signal line, and a switching circuit. The switching circuit allows one of a pair of the capacitor elements to be charged with a pixel signal in a certain row, and also allows the other of a pair of the capacitor elements to be charged with a pixel signal in another row. The switching circuit transfers pixel signals in different rows, with which a pair of the capacitor elements are respectively charged, to the horizontal signal line so as to be added and averaged. Therefore, the thinning-out read operation can be executed by easy scanning. The charging voltage of the capacitor element can be outputted to the horizontal signal line by charging the capacitor element to the level of a voltage after reading out the pixel signal of each pixel as the voltage since the transfer is executed via the capacitor element. Namely, the SN ratio can be improved since the pixel signal can be read out by voltage output. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state image sensor, and more particularly to thinning readout.

  Video cameras and electronic cameras are equipped with a liquid crystal display device for displaying a through image and reproducing and confirming a captured image on the spot. A liquid crystal display device for such a purpose is generally small and has a smaller number of pixels than that of a solid-state imaging device. Therefore, when performing a through image display or the like, the conventional electronic camera has processed as follows. First, the pixel signals of all pixels are read from the solid-state imaging device and temporarily stored in the image memory, and then only the pixel signals for the required number of pixels are read from the image memory according to the number of pixels of the display device and used for display. Yes.

  In this case, since the pixel signals of all the pixels are once read from the solid-state imaging device, it takes a longer time for reading scanning than when only the necessary pixels are read, and the power consumption cannot be reduced. In order to avoid this, if only the pixel signals of some pixels are read out by regular thinning in the solid-state imaging device, pixel signals of all colors may not be obtained. For example, in the Bayer array, when only pixel signals of only odd-numbered rows or only pixels of odd-numbered columns are read, any color component of red or blue is not read at all.

  Therefore, in Patent Document 1, as described in paragraph [0052], when thinning readout is performed in a G stripe RB line sequential arrangement, even-numbered pixels are not read, and odd-numbered pixels are read only partially. Yes. Here, G is a pixel that selectively receives green light (hereinafter also referred to as green pixel), R is a pixel that selectively receives red light (hereinafter also referred to as red pixel), and B is blue. A pixel that selectively receives light (hereinafter also referred to as a blue pixel).

Specifically, for the (4n-3) th row, only the pixels in the 1, 2, 5, 8, 9... Column are read, and for the (4n-1) th row, 1, 4, 5, 6 are read. , 9... Only the pixels in the column are read out. In this specification, n is a natural number.
In this case, as described in Table 5 of Patent Document 1, when viewed in units of 32 pixel blocks in the horizontal direction 8 × vertical direction 4, the arrangement of read pixels is the same. One green pixel, two red pixels, and two blue pixels are read out. Therefore, if color interpolation processing is appropriately performed after such thinning-out reading, color image data can be obtained without reading out pixel signals of all pixels.

In Patent Document 2, the output signal from each pixel is simultaneously read as a current value, and after adding a plurality of current values, converted into a voltage and output, the number of finally read pixel signals is all pixels. The number is thinned out.
JP 2000-4406 A JP-A-10-285472

Although the invention of Patent Document 1 has excellent operational effects as described above, the pixels read in the odd rows do not have the same column spacing. Therefore, there is a possibility that the reading scanning at the time of thinning-out reading and the color interpolation processing after the thinning-out reading are slightly complicated.
The solid-state imaging device of Patent Document 2 functions sufficiently in use, but since the output signal from each pixel is read as a current value, the SN ratio is higher than when the pixel signal is read as a voltage as in Patent Document 1. Is inferior.

An object of the present invention is to provide a technique for facilitating readout scanning at the time of thinning readout and color interpolation processing after readout in a solid-state imaging device capable of thinning readout.
Another object of the present invention is to provide a solid-state imaging device suitable for the above-described object, having a good SN ratio.

  The invention of claim 1 is a solid-state imaging device comprising a plurality of pixels two-dimensionally arranged along vertical columns and horizontal rows, a plurality of vertical transfer units, and at least one horizontal signal line. is there. The plurality of vertical transfer units are respectively arranged corresponding to the pixel columns and connected to the plurality of pixels, and transfer pixel signals generated by the pixels in the vertical direction. Pixel signals from a plurality of vertical transfer units are transferred to the horizontal signal line.

  The invention of claim 1 is characterized by the following points. First, between the horizontal signal line and the plurality of vertical transfer units, a plurality of capacitors are provided for each vertical transfer unit corresponding to the plurality of vertical transfer units. Second, the plurality of capacitors are connected in parallel to each other between the corresponding vertical transfer unit and one horizontal signal line, and are charged by receiving a pixel signal from the vertical transfer unit. Third, a switching circuit for transferring a pixel signal to the horizontal signal line by connecting a plurality of capacitors to the horizontal signal line is provided.

  According to a second aspect of the present invention, there is provided a solid-state imaging device including a plurality of pixels two-dimensionally arranged along a vertical column and a horizontal row, a plurality of vertical transfer units, and a horizontal transfer unit. The plurality of vertical transfer units are respectively arranged corresponding to the pixel columns and connected to the plurality of pixels, and transfer pixel signals generated by the pixels in the vertical direction. Pixel signals from a plurality of vertical transfer units are transferred to the horizontal transfer unit.

  The invention of claim 2 is characterized by the following points. First, it includes a pair of capacitors respectively arranged for a plurality of vertical transfer units, and a switching circuit that transfers a pixel signal to the horizontal transfer unit by connecting the pair of capacitors to the horizontal transfer unit. Second, the pair of capacitors are connected in parallel to the corresponding vertical transfer unit, and are charged by receiving a pixel signal from the vertical transfer unit. Third, when thinning-out reading is performed, the switching circuit charges one row of pixel signals in one row and the other charges another row of pixel signals to charge the pair of capacitors. The processed pixel signals are transferred to the horizontal transfer unit so as to be averaged.

  The invention of claim 3 is the solid-state image pickup device of claim 2, characterized by the following points. First, the plurality of pixels include a first color component pixel arranged in a pine or stripe shape, and a second color component pixel and a third color component pixel arranged line-sequentially between the first color component pixels. including. Second, the pair of capacitors is one of a first capacitor pair charged with a pixel signal of the first color component pixel and a second capacitor pair charged with a pixel signal of the second and third color component pixels. is there. Third, each vertical transfer unit includes a first vertical signal line and a second vertical signal line that transfer pixel signals of one type or two types of color components. Fourth, the horizontal transfer unit includes a first horizontal signal line and a second horizontal signal line. Fifthly, the switching circuit selects one of the first and second vertical signal lines to which the pixel signal of the first color component pixel has been transferred and connects it to the first capacitor pair. After selecting the pixel component pixel signal transferred and connecting it to the second capacitor pair, connect the first capacitor pair to the first horizontal signal line and connect the second capacitor pair to the second horizontal signal line. To do.

  According to a fourth aspect of the present invention, the solid-state imaging device according to the third aspect is characterized by the following points. First, the first vertical signal line is connected to the pixels in the (4n-3) th row and the (4n-2) th row. Second, the second vertical signal line is connected to the pixels in the (4n-1) th row and the 4nth row. Third, when thinning-out reading is performed, the switching circuit connects the first vertical signal line to one of the pair of capacitors and the second vertical signal line to the other, and (4n-3) rows. The operation of adding and averaging the pixel signals of the first and (4n-1) th rows and the operation of reading the pixel signals of the 4nth row by connecting the second vertical signal line to a pair of capacitors are repeated.

  The invention according to claim 5 is the solid-state image pickup device according to claim 3, characterized by the following points. First, the first vertical signal line is connected to the pixels in the (4n-3) th row and the (4n-2) th row. Second, the second vertical signal line is connected to the pixels in the (4n-1) th row and the 4nth row. Third, when thinning-out reading is performed, the switching circuit connects the first vertical signal line to a pair of capacitors and reads out the pixel signal of the (4n-3) -th row, and one of the pair of capacitors. Repeats the operation of connecting the first vertical signal line and connecting the second vertical signal line to the other and reading out the pixel signals of the (4n−2) th and 4nth rows by averaging them together.

  The invention of claim 6 is the solid-state image pickup device of claim 2, characterized by the following points. First, the plurality of pixels include a first color component pixel arranged in a pine or stripe shape, and a second color component pixel and a third color component pixel arranged line-sequentially between the first color component pixels. including. Second, the vertical transfer unit is one of the vertical signal line A connected to the first color component pixel and the vertical signal line B connected to the second and third color component pixels. Third, the plurality of vertical signal lines A and the plurality of vertical signal lines B are alternately arranged in the column order. Fourth, a pair of capacitors is charged with only a pixel signal from any one of the vertical signal lines A or a pixel signal from any one of the vertical signal lines B. Fifth, the horizontal transfer unit includes a first horizontal signal line and a second horizontal signal line. Sixth, the switching circuit connects a pair of capacitors charged with the pixel signal from the vertical signal line A to the first horizontal signal line and connects a pair of capacitors charged with the pixel signal from the vertical signal line B to the first capacitor. Connect to 2 horizontal signal lines.

  The invention according to claim 7 is the solid-state image pickup device according to claim 6, characterized by the following points. When thinning-out readout is performed, the switching circuit performs an operation of reading out the pixel signals of the (4n-3) th row and the (4n-1) th row, and an operation of reading out the pixel signals of the 4nth row. Or the operation of reading out the pixel signal of the (4n-3) th row and the operation of reading out the pixel signals of the (4n-2) th row and the 4nth row are averaged.

  The solid-state imaging device of the present invention has a plurality of capacitors arranged for each vertical transfer unit, and these capacitors are connected in parallel to each other for each corresponding vertical transfer unit. For this reason, in thinning-out readout, one of the capacitors connected in parallel can be charged with a pixel signal in one row, and another capacitor can be charged with a pixel signal in another row. Therefore, if pixel signals in different rows respectively charged in a plurality of capacitors connected in parallel are transferred to the horizontal signal line so as to be averaged, thinning readout can be performed by easy scanning. In addition, since the transfer is performed via a capacitor, the pixel signal of each pixel can be read as a voltage, the capacitor can be charged to that voltage, and the charge voltage of the capacitor can be output to the horizontal signal line. That is, since it can be read out by voltage output, the SN ratio becomes good.

  In one embodiment of the present invention, each vertical transfer unit includes first and second vertical signal lines, and the capacitors connected in parallel to each other are either the first capacitor pair or the second capacitor pair. From the first and second vertical signal lines, the one to which the pixel signal of the first color component is transferred is selected and connected to the first capacitor pair, and the pixel signal of the second or third color component is selected. What is being transferred is selected and connected to the second capacity pair. Thereafter, the first capacitor pair is connected to the first horizontal signal line, and the second capacitor pair is connected to the second horizontal signal line. That is, only the pixel signal of the first color component is transferred to the first horizontal signal line, and only the pixel signals of the second and third color components are transferred to the second horizontal signal line. Processing becomes easy.

  In another embodiment of the present invention, the vertical transfer unit is any one of the vertical signal line A connected to the first color component pixel and the vertical signal line B connected to the second and third color component pixels. . The capacitor charged with the pixel signal from the vertical signal line A is connected to the first horizontal signal line, and the capacitor charged with the pixel signal from the vertical signal line B is connected to the second horizontal signal line. Accordingly, only the pixel signals of the first color component and the second and third color components are transferred to the first horizontal signal line and the second horizontal signal line, so that the color interpolation process after reading becomes easy.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in each figure, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.
FIG. 1 is an equivalent circuit diagram of the solid-state imaging device 2 according to the first embodiment of the present invention. This embodiment corresponds to claims 1 to 4.
As shown in the figure, the solid-state imaging device 2 includes a red pixel R, a green pixel G, and a blue pixel B arranged in a Bayer array, a vertical scanning circuit 8, and a NAND gate that connects each pixel and the vertical scanning circuit 8 for each row. (NAND GATE) Na1 to Na5 and AND GATEs An1 to An5, vertical signal lines VL and vertical signal lines VR arranged for each pixel column, and a constant signal connected to one end of the vertical signal line VL. A current source CSL, a constant current source CSR connected to one end side of the vertical signal line VR, a green horizontal signal line 20 disposed on the other end side of the vertical signal lines VL and VR, and a red-blue horizontal signal line 24; , And a horizontal scanning circuit 30.

In the following description, the term “pixel” includes all of the red pixel R, the green pixel G, and the blue pixel B. Also, in the reference numerals in the figure, those that start with φ indicate drive voltage, and GND in the figure indicates a ground line. In the figure, the number of pixels is described as 5 × 4 because it is complicated, but actually, more pixels are arranged.
Also, at the end of the reference numerals of some elements in the figure, 1, 2, 3, 4, 5 are added to indicate the arrangement rows, and a, b, c are shown to indicate the correspondence with the arrangement columns. , D. Here, the “correspondence with the arrangement column” can be understood by comparing the pixel columns indicated by numbers at the bottom of the figure with the column selection transistors Tha to Thd (functions will be described later) shown at the top of the figure. Thus, a column between the first and second columns of pixels is b column between the second column and the third column, c column between the third column and the fourth column, fourth column and fifth column The distance between the eyes is d columns. Note that no pixels are arranged in the first column of the odd rows. These a, b, c, and d are given to make it easy to distinguish each element when the circuit operation described later is described. When it is not necessary to distinguish between rows and columns, the last 1, 2, a, b, etc. of the reference numerals are omitted as appropriate.

  In the configuration so far, the following two points are greatly different from the conventional one. First, two vertical signal lines (VL, VR) are arranged between the pixel columns. In the figure, it is assumed that one vertical signal line extends on the vertical scanning circuit 8 side (left side) and on the opposite side with respect to one pixel column, and the vertical scanning circuit 8 side is connected to the vertical signal line VL, The opposite side was defined as a vertical signal line VR. Second, a NAND gate Na and an AND gate An are arranged for each row between each pixel and the vertical scanning circuit 8. The second feature will be described with reference to FIG.

  Further, at the other end of the vertical signal line VL and the vertical signal line VR, another green selection circuit MXG and red / blue selection circuit MXR / B, which are another feature of the present embodiment, are alternately arranged in the column order. ing. The other end of the vertical signal line VL is branched into two input signal lines Iα and Iγ, except for the one arranged for the endmost pixel column, and the other end of the vertical signal line VR is input. The signal lines Iβ and Iδ are branched into two. The input signal lines Iα, Iβ, Iγ, and Iδ are all connected only to either the green selection circuit MXG or the red / blue selection circuit MXR / B.

  Then, the pixel signals of the green pixels G in the first and second columns, which are columns corresponding to the a column, are input to the green selection circuit MXGa in the a column. In this example, the pixel signals of the second green pixel G in the odd row and the first green pixel G in the even row are input. In addition, the pixel signals of the red and blue pixels R and B in the second and third columns, which are columns corresponding to the b column, are input to the b / red selection circuit MXR / Bb. In this example, pixel signals of the red pixel R in the third column of the odd row and the blue pixel B in the second column of the even row are input. The same applies to the green selection circuits MXG and red / blue selection circuits MXR / Bd in the other columns.

  Each green selection circuit MXG is connected in parallel with CDS capacitors CcL and CcR that receive a pixel signal of each pixel by correlated double sampling processing. Further, CDS capacitors CcL and CcR are also connected in parallel to each of the red / blue selection circuits MXR / B. As described above, one of the features of this embodiment is that two CDS capacitors CcL and CcR are arranged per pixel column.

Further, one CDS transistor Tc for performing correlated double sampling processing is arranged for each green selection circuit MXG and each red / blue selection circuit MXR / B. All the CDS transistors Tc are switched to a conductive or non-conductive state by receiving a common FPN accumulation pulse φc at their gates.
Further, the CDS capacitors CcL and CcR connected to the green selection circuits MXG are connected to the green horizontal signal line 20, and the CDS capacitors CcL and CcR connected to the red and blue selection circuits MXR / B are connected to the red-blue horizontal signal. A plurality of column selection transistors Th connected to the line 24 are arranged. The column selection transistor Th receives a driving voltage φGH common to every two columns from the horizontal scanning circuit 30 at its gate, and switches to a conductive or non-conductive state.

  Further, output buffer amplifiers 32, 34, output terminals Gout, R / Bout, and horizontal reset transistors TRg, TRrb are connected to output ends of the green horizontal signal line 20 and the red-blue horizontal signal line 24, respectively. . Both horizontal reset transistors TRg and TRrb receive the horizontal reset pulse voltage φRSTH at their gates and become conductive or nonconductive.

As shown in the green pixel G in the fifth row and the second column in the figure, each pixel includes a photodiode PD, a transfer gate FW, a reset gate RG, and a junction field effect transistor JFET (hereinafter referred to as a pixel amplifier). Abbreviated as JFET).
The transfer gate FW is formed as a P-channel type MOS transistor, and transfers the accumulated charge of the photodiode PD to the gate of the JFET according to the gate voltage. The reset gate RG is formed as a P-channel type MOS transistor. When the reset gate RG is turned on (conductive), the gate of the JFET is connected to the power supply (voltage VRD) common to all the pixels, and the JFET is inactivated. When the reset gate RG is off (non-conducting), the JFET is in an operating state. The drain of the JFET receives the substrate potential Vsub common to all pixels.

  FIG. 2 is a circuit diagram focusing on the connection between the vertical scanning circuit 8 and each pixel in FIG. The vertical scanning circuit 8 has one output signal line for each row of pixels, and these output signal lines output row selection signals OPT1 to OPTn from the vertical scanning circuit 8, respectively. The row selection signal OPT is input to one input terminal of a NAND gate Na and an AND gate An arranged one for each row of pixels.

  As shown in the figure, in the odd-numbered row, the other input terminal of the NAND gate Na receives the drive voltage φTG1, and the other input terminal of the AND gate An receives the drive voltage φRSG1. In the even-numbered row, the other input terminal of the NAND gate Na receives the drive voltage φTG2, and the other input terminal of the AND gate An receives the drive voltage φRSG2. The output voltage of the NAND gate Na in a row is supplied in common to the transfer gates FW of all the pixels in the row, and the output voltage of the AND gate An in a row is supplied in common to the reset gates RG of all the pixels in the row. The In a row selected by the vertical scanning circuit 8, the row selection signal OPT is set to a high level, and in a row not selected, the row selection signal OPT is set to a low level.

  FIG. 3 is a circuit diagram showing details of the green selection circuit MXG and the red / blue selection circuit MXR / B. Both the green selection circuit MXG and the red / blue selection circuit MXR / B are multiplexers having the same circuit configuration, and are constant current sources CSML and CSMR, bipolar transistors BiL and BiR, and switches that are n-channel MOS transistors. QαL, QαR, QβL, QβR, QγL, QγR, QδL, and QδR. In the figure, VCC is a power supply line.

All the green selection circuits MXG and red / blue selection circuits MXR / B are connected to the eight selection drive voltages φPαL, φPαR, φPβL, φPβR, φPγL, φPγR, φPδL, via eight common signal lines. Each receives φPδR.
Each of these eight selection drive voltages φPαL to φPδR receives a high level voltage, and turns on the corresponding switch (any one of QαL to QδR) to turn on the corresponding input signal line (Iα to Iδ). Is connected to the corresponding CDS capacitor (either CcL or CcR). Here, “corresponding” means that the characters α, β, γ, δ, L, and R included in the code match. For example, when the selection drive voltage φPαR is at a high level, the switch QαR is turned on, and the input signal line Iα is connected to the CDS transistor CcR.

In the above circuit configuration, the correspondence with the claims is, for example, as follows.
The vertical direction described in the claims corresponds to the column direction of the pixels, that is, the extending direction of the vertical signal lines VL and VR, and the horizontal direction corresponds to the direction orthogonal to the vertical direction (pixel row direction). The first, second, and third color component pixels recited in the claims correspond to the green pixel G, the blue pixel R, and the red pixel R, respectively. The first capacitance pair corresponds to the CDS capacitors CcL and CcR connected to the green selection circuit MXG, and the second capacitance pair is the CDS capacitor CcL connected to the red-blue selection circuit MXR / B, Corresponds to CcR.

  The first vertical signal line corresponds to the vertical signal line VR, and the second vertical signal line corresponds to the vertical signal line VL. The first horizontal signal line and the second horizontal signal line recited in the claims correspond to the green horizontal signal line 20 and the red-blue horizontal signal line 24, respectively. The switching circuit described in claims corresponds to the green selection circuit MXG, the red / blue selection circuit MXR / B, the column selection transistor Th, the CDS transistor Tc, the horizontal reset transistors TRg and TRrb, and the horizontal scanning circuit 30.

FIG. 4 is a timing diagram showing voltage waveforms at various portions when normal reading is performed in the solid-state imaging device 2 described above, that is, when pixel signals of all pixels are read. Hereinafter, the circuit operation of the solid-state imaging device 2 will be described with reference to FIGS. 1, 3, and 4.
First, a high level start pulse STV is input to the vertical scanning circuit 8 in order to drive a vertical shift register (not shown) in the vertical scanning circuit 8. Almost in synchronization with this, a low level clock signal CLKV 1 and a high level clock signal CLKV 2 are input to the vertical scanning circuit 8. Thereby, the row selection signal OPT1 output from the vertical scanning circuit 8 is switched to the high level, the other row selection signals OPT2 to OPTn are set to the low level, and the first row of the solid-state imaging device 2 is selected.

  Note that immediately after the clock signals CLKV1 and CLKV2 are input, the drive voltages φRSG1, φRSG2, φTG1, and φTG2 are all at a low level. Accordingly, in all the rows, the output voltage of the NAND gate Na is high, so that the transfer gate FW is off, and the output voltage of the AND gate is low, so that the reset gate RG is on, and the JFET The gate voltage is reset. The same applies immediately after selection of another row.

  Next, among the eight selection drive voltages, only φPδL and φPδR are set to a high level. As a result, the CDS capacitors CcL and CcR connected to the green selection circuit MXG are connected to the JFET source of the green pixel G in the first row via the input signal line Iδ and the vertical signal line VR. The CDS capacitors CcL and CcR connected to the red / blue selection circuit MXR / B are connected to the source of the JFET of the red pixel R in the first row via the input signal line Iδ and the vertical signal line VR.

  Next, the drive voltage φRSG1 is switched to a high level. As a result, the output voltage of the AND gate An1 in the first row selected by the vertical scanning circuit 8 is switched to a high level, and the reset gate RG in the first row is turned off. In the process in which the drive voltage φRSG1 is switched to a high level, the gate of the JFET is in an electrically floating state and the voltage rises due to capacitive coupling. This capacitive coupling is caused by the capacitance formed between the adjacent regions (source, drain, transfer gate FW, etc.) of the JFET gate.

  Next, the FPN accumulation pulse φc is switched to a high level, and all the CDS transistors Tc are turned on. At this time, since the signal charge of the photodiode PD has not yet been transferred to the gate of the JFET, the source voltage of the JFET is a voltage corresponding to a fixed pattern noise component. Therefore, the charging voltage of the pixel-side electrode in the CDS capacitors CcL and CcR is both (fixed pattern noise component −Vref). Thereafter, the FPN accumulation pulse φc is switched to a low level.

Next, the drive voltage φTG1 is switched to a high level. Thereby, in the first row, the output voltage of the NAND gate Na1 is switched to a low level, each transfer gate FW is turned on, and the signal charge of the photodiode PD is transferred to the gate of the JFET. The JFET outputs a signal voltage (pixel signal) corresponding to the amount of charge accumulated in the gate from the source. As a result, the voltages of the electrodes on the CDS transistor Tc side in the CDS capacitors CcL and CcR are both charged to the same voltage expressed by the following equation.
[Signal voltage-(fixed pattern noise component-Vref)] (1)
That is, the fixed voltage noise component is included in the signal voltage, but the fixed pattern noise component is canceled by the voltage previously charged by the FPN accumulation pulse φc (correlated double sampling processing). Thereafter, the drive voltage φTG1 is switched to a low level.

  Next, the pixel signals in the first row are read in the horizontal direction within the remaining period in which the drive voltage φRSG1 is at a high level. The horizontal reading includes an operation of resetting the voltages of the green horizontal signal line 20 and the red / blue horizontal signal line 24, and an operation of turning on a horizontal shift register (not shown) in the horizontal scanning circuit 30 sequentially one by one. It is done by repeating. Specifically, first, the horizontal reset pulse voltage φRSTH is switched to a high level. Thereby, the horizontal reset transistors TRg and TRrb are turned on, and the voltages of the green horizontal signal line 20 and the red-blue horizontal signal line 24 are reset to Vref. Thereafter, the horizontal reset pulse voltage φRSTH is switched to a low level.

  Next, the horizontal shift register closest to the output buffer amplifier 32 in the horizontal scanning circuit 30 is turned on, and the drive voltage φGHab corresponding to the columns a and b is switched to a high level. Thereby, the column selection transistors Tha and Thb are switched to the on state. Accordingly, the charging voltages (corresponding to pixel signals) of the CDS capacitors CcL and CcR connected to the green selection circuit MXGa in the a column are output via the green horizontal signal line 20 and the output buffer amplifier 32. The pixel signals charged in the CCDS capacitors CcL and CcR connected to the b-row red / blue selection circuit MXR / Bb are output via the red / blue horizontal signal line 24 and the output buffer amplifier 34.

Here, a supplementary description will be given of the signal voltage output to the green horizontal signal line 20. If the output voltage value of the source of the JFET is JS and the capacitance values (farads) of the CDS capacitors CcL and CcR are CF1 and CF2, respectively, the total accumulated charge amount (coulomb) of the pair of CDS capacitors CcL and CcR connected in parallel Is JS × (CF1 + CF2). Here, since there is a parasitic capacitance in the green horizontal signal line 20, if the capacitance value is CFH, it is equivalent to the signal voltage being lowered by the amount that the accumulated charge is distributed to CFH. That is, the output voltage Vsg of the green horizontal signal line 20 is expressed by the following equation.
Vsg = JS × (CF1 + CF2) / (CF1 + CF2 + CFH) (2)
Similarly, the red-blue horizontal signal line 24 has a parasitic capacitance, and the output voltage of the red-blue horizontal signal line 24 is the same as that in the expression (2). In the present embodiment, as an example, CF1 = CF2.

  After the pixel signals in the second and third columns in the first row are read to the green horizontal signal line 20 and the red / blue horizontal signal line 24 as described above, the horizontal reset pulse voltage φRSTH is switched to a high level (described above). As described above, there is no pixel in the odd-numbered row and the first column and is not read out). Thereby, after resetting the voltages of the green horizontal signal line 20 and the red-blue horizontal signal line 24, the horizontal reset pulse voltage φRSTH is switched to a low level.

  Then, the horizontal shift register is shifted by one, the drive voltage φGHcd corresponding to the columns c and d is switched to a high level, and the column selection transistors Thc and Thd are turned on. Thereby, the pixel signals charged in the CDS capacitors CcL and CcR connected to the green selection circuit MXGc in the c column are output to the green horizontal signal line 20 and connected to the red / blue selection circuit MXR / Bd in the d column. The pixel signals charged in the CDS capacitors CcL and CcR are output to the blue horizontal signal line. That is, the pixel signals in the fourth column and the fifth column in the first row are read out.

  By repeating such an operation, the pixel signal in the first row is read every two columns, and then the drive voltage φRSG1 is switched to a low level. As a result, in the first row, the output voltage of the AND gate An1 is switched to a low level, the reset gate RG is switched to the OFF state, and the gate voltage of the JFET is reset. This is the period of “first row horizontal reading” in FIG.

  Next, the clock signals CLKV1 and CLKV2 are input to the vertical scanning circuit 8 to shift the vertical shift register by one and select the second row. Next, of the eight selection drive voltages, only φPβL and φPβR are set to a high level. As a result, the CDS capacitors CcL and CcR connected to the green selection circuit MXG are connected to the green pixels G in the second row via the input signal line Iβ and the vertical signal line VR. The CDS capacitors CcL and CcR connected to the red / blue selection circuit MXR / B are connected to the blue pixels B in the second row through the input signal line Iβ and the vertical signal line VR.

  Next, the drive voltage φRSG2 is switched to a high level. Thereafter, pixel signals in the second row are read out in the same manner as in the first row, except that φTG2 is set to a high level instead of the drive voltage φTG1. That is, the CDS capacitors CcL and CcR connected to the green selection circuit MXG are both charged by the pixel signal of the green pixel G in the second row, and this pixel signal is read from the green horizontal signal line 20. At the same time, the CDS capacitors CcL and CcR connected to the red / blue selection circuit MXR / B are both charged by the pixel signal of the blue pixel B in the second row, and this pixel signal is read from the red / blue flat signal line 24. . Thereby, the reading of the second row is completed.

  Next, the clock signals CLKV1 and CLKV2 are input to the vertical scanning circuit 8 to select the third row. Next, of the eight control drive voltages, only φPγL and φPγR are set to a high level. As a result, the CDS capacitors CcL and CcR connected to the green selection circuit MXG are connected to the green pixels G in the third row via the input signal line Iγ and the vertical signal line VL. The CDS capacitors CcL and CcR connected to the red / blue selection circuit MXR / B are connected to the red pixel R in the third row via the input signal line Iγ and the vertical signal line VL. Thereafter, the drive voltage φRSG1 is switched to a high level, and the pixel signals in the third row are read out as in the case of the first row.

  Next, the clock signals CLKV1 and CLKV2 are input to the vertical scanning circuit 8, and the fourth row is selected. Next, of the eight control drive voltages, only φPαL and φPαR are set to a high level. As a result, the CDS capacitors CcL and CcR connected to the green selection circuit MXG are connected to the fourth row of green pixels G via the input signal line Iα and the vertical signal line VL. The CDS capacitors CcL and CcR connected to the red / blue selection circuit MXR / B are connected to the blue pixels B in the fourth row via the input signal line Iα and the vertical signal line VL. Next, the drive voltage φRSG2 is switched to a high level, and the pixel signals in the fourth row are read out as in the case of the second row.

  By repeating the above operation, pixel signals of all rows are read out. The readout scanning is the same in units of four rows, and the main differences in the four rows are the following two points. First, the driving voltages φRSG1 and φTG1 are used in the odd rows, and the driving voltages φRSG2 and φTG2 are used in the even rows. Second, which of the eight control drive voltages is set to a high level is different. That is, if the (4n-3) th row is selected, φPδL and φPδR are set to a high level, and if the (4n-2) th row is selected, φPβL and φPβR are set to a high level. If the eye is selected, φPγL and φPγR are set to a high level, and if the 4nth row is selected, φPαL and φPαR are set to a high level. The above is the description of the normal reading operation.

FIG. 5 is a timing diagram showing voltage waveforms at various parts when thinning readout is performed in the solid-state imaging device 2 described above. Hereinafter, the circuit operation of thinning readout will be described with reference to FIG. 1, FIG. 3, and FIG.
First, the high level start pulse STV and the clock signals CLKV1 and CLKV2 are input to the vertical scanning circuit 8 as in the case of normal reading, and only the first row is selected. Thereafter, clock signals CLKV1 and CLKV2 are input, and only the second row is selected. Thereafter, the start pulse STV and the clock signals CLKV1 and CLKV2 are input to the vertical scanning circuit 8 almost simultaneously. As a result, the first and third rows are selected simultaneously. As in the case of normal reading, immediately after the clock signals CLKV1 and CLKV2 are input, the transfer gates FW are turned off and the gate voltages of the JFETs are reset in all rows.

  Next, of the eight selection drive voltages, only φPδL and φPγR are set to a high level. Accordingly, among the CDS capacitors connected to the green selection circuit MXG, CcL is connected to the green pixel G in the first row via the input signal line Iδ and the vertical signal line VR, and CcR is connected to the input signal line Iγ. Are connected to the green pixel G in the third row via the vertical signal line VL. Among the CDS capacitors connected to the red / blue selection circuit MXR / B, CcL is connected to the red pixel R in the first row via the input signal line Iδ and the vertical signal line VR, and CcR is the input signal. The line is connected to the red pixel R in the third row via the line Iγ and the vertical signal line VL.

  Next, the drive voltage φRSG1 is switched to a high level, and the selected JFETs in the first and third rows are set in an operating state. Next, the FPN accumulation pulse φc is switched to a high level to turn on the CDS transistor Tc. Thereby, the CDS capacitors CcL and CcR are each charged with a voltage corresponding to the fixed pattern noise component of one pixel connected as described above. Thereafter, the FPN accumulation pulse φc is switched to a low level.

  Next, the drive voltage φTG1 is switched to a high level. As a result, the transfer gates FW of the pixels in the first and third rows are turned on, the signal charge of the photodiode PD is transferred to the gate of the JFET, and the JFET outputs a signal voltage (pixel signal) from the source. Thereby, the CDS capacitors CcL and CcR are each charged with a pixel signal of one pixel. At this time, the previously charged fixed pattern noise component is canceled out. Thereafter, the drive voltage φTG1 is switched to a low level.

  Next, in the remaining period in which the drive voltage φRSG1 is at a high level, the pixel signals of all the columns in the first and third rows are read in the horizontal direction by the same scanning as in the normal reading. Since the CDS capacitors CcL and CcR are charged with the pixel signals in the first row and the third row, the signal voltages output to the green horizontal signal line 20 and the red-blue horizontal signal line 24 are in the case of normal reading. Unlike the above, the pixel signals in the first and third rows are summed and averaged.

  Specifically, if the output voltage value of the source of the JFET in the first row is JS1, and the output voltage value of the source of the JFET in the third row is JS3, the total of the pair of CDS capacitors CcL and CcR connected in parallel The accumulated charge amount is (JS1 × CF1 + JS3 × CF2). Here, when the parasitic capacitance CFH of the green horizontal signal line 20 is taken into consideration, the output voltage Vsg of the green horizontal signal line 20 is expressed by the following equation.

Vsg = (JS1 × CF1 + JS3 × CF2) / (CF1 + CF2 + CFH)
... (3)
In other words, since CF1 and CF2 are equal in this embodiment, if the influence of the parasitic capacitance CFH is removed, it is equivalent to the sum of the charging voltages of the two CDS capacitors CcL and CcR being output. The output voltage of the red / blue horizontal signal line 24 is the same as that in the expression (3). When the horizontal readout of the pixel signals in the first and third rows is completed, the drive voltage φRSG1 is switched to a low level. This is the “1st, 3rd row horizontal readout” period in FIG.

Next, the clock signals CLKV1 and CLKV2 are input to the vertical scanning circuit 8 one pulse at a time, the vertical shift register is shifted by one, and the second and fourth rows are selected simultaneously.
Next, of the eight selection drive voltages, only φPαL and φPαR are set to a high level. As a result, the CDS capacitors CcL and CcR connected to the green selection circuit MXG are connected to the fourth row of green pixels G via the input signal line Iα and the vertical signal line VL. The CDS capacitors CcL and CcR connected to the red / blue selection circuit MXR / B are connected to the blue pixels B in the fourth row via the input signal line Iα and the vertical signal line VL. That is, the second and fourth rows are selected, but the second row is not read, and only the pixel signals of the fourth row are read alone. Thereafter, the drive voltage φRSG2 is switched to a high level, and the pixel signal in the fourth row is read out as in the case of the fourth row in normal readout, and then the drive voltage φRSG2 is switched to a low level.

Next, the clock signals CLKV1 and CLKV2 are input to the vertical scanning circuit 8 by three pulses at a time, and the vertical shift register is shifted by three to simultaneously select the fifth and seventh rows. Thereafter, among the eight selection drive voltages, only φPδL and φPγR are set to the high level, and the pixel signals in the fifth and seventh rows are mixed and read out as in the first and third rows.
Next, the clock signals CLKV1 and CLKV2 are input to the vertical scanning circuit 8 one pulse at a time, the vertical shift register is shifted by one, and the sixth and eighth rows are selected simultaneously. Thereafter, among the eight selection drive voltages, only φPαL and φPαR are set to the high level, and the pixel signals in the eighth row are read out independently, as in the case of the fourth row.

  By repeating the above operation, the pixel signals of all rows are read out. The readout scanning is the same in units of 4 rows. That is, φPδL and φPγR among the selection drive voltages are set to a high level, and the pixel signals of the (4n-3) and (4n-1) rows are mixed and read, and then, among the selection drive voltages, φPαL, The operation of setting φPαR to a high level and reading the pixel signal of the 4nth row independently is repeated. The above is the description of the thinning readout operation.

As described above, in the thinning readout in the first embodiment, the operation of simultaneously reading the (4n-3) th and (4n-1) th rows and the operation of reading the 4nth row independently are repeated. Accordingly, the read time is half that of the normal read in which all rows are read one by one.
The pixel signal output from each pixel is the source voltage of the JFET, which is output to the green horizontal signal line 20 and the red / blue horizontal signal line 24 after charging the CDS capacitors CcL and CcR. Therefore, noise is smaller than when reading with current.

  Since a signal obtained by averaging the pixel signals of the (4n-3) th row and the (4n-1) th row is output from the green horizontal signal line 20 and the red / blue horizontal signal line 24, one of them is read out. Compared with the case where the other is not read, twice the amount of incident light contributes to the generation of the image signal. Accordingly, the light utilization rate is increased. Further, since the pixel signals of two green pixels G (or red pixels R) located across one row are averaged, the magnitude of the noise is about 1 / √2 when only one is read out. That is, the SN ratio can be improved by about 3 dB.

  Here, the (4n-3) th and (4n-1) th rows that are mixedly read are rows in which green pixels G and red pixels R are arranged (hereinafter referred to as GR rows), and are read out independently. The 4nth row is a row in which the green pixel G and the blue pixel B are arranged (hereinafter referred to as GB row). In general, moire is more visually noticeable in the red component than in the blue component. Therefore, in the present embodiment in which mixed readout is performed with respect to the GR row, moire and noise during thinning readout can be effectively reduced.

  When the pixel signals in the (4n-3) th and (4n-1) th rows are mixed and read, the center of gravity of sampling is the (4n-2) th row which is the middle of both. Since the 4n-th row is read out independently, the center of sampling is repeated in the (4n-2) -th row and the 4n-th row, so that the sampling interval at the thinning-out readout can be made equal over all rows. Therefore, if the solid-state imaging device 2 of this embodiment is mounted on a digital camera, the continuous shooting speed can be doubled and a good image signal can be obtained.

  In the thinning readout according to the first embodiment, the example in which the mixed reading is performed for the GR row and the GB row is read independently has been described. The present invention is not limited to such an embodiment. The operation of independently reading the (4n-3) row that is the GR row and the operation of reading the mixed (4n-2) row and the 4n row that are the GB rows may be sequentially repeated. Correspondence). In this case, when reading the (4n-3) th row, only φPδL and φPδR among the selection drive voltages are set to the high level, and when the (4n-2) th row and the 4nth row are mixed and read, the selection drive. Of the voltages, only φPβL and φPαR (or only φPβR and φPαL) may be set to a high level. Also in this case, the sampling centers of gravity are equally spaced.

  The operation of reading the pixel signals in the (4n-3) th row and the (4n-1) th row and the operation of reading the pixel signals in the (4n-2) th row and the 4nth row may be sequentially repeated. . In this case, when (4n-3) line and (4n-1) are mixedly read, only φPδL and φPγR (or only φPδR and φPγL) of the selection drive voltages are set to a high level, and (4n-2 ) When mixed reading of the row and the 4nth row is performed, only φPβL and φPαR (or only φPβR and φPαL) of the selection drive voltages may be set to a high level. In this case, the same effect as described above can be obtained except that the sampling centers of gravity are not equally spaced.

  The example in which two CDS capacitors CcL and CcR are connected in parallel to each of the green selection circuit MXG and the red / blue selection circuit MXR / B has been described, but the number of CDS capacitors connected in parallel is three or more. But you can. For example, four CDS capacitors are connected in parallel to each of the green selection circuit MXG and the red / blue selection circuit MXR / B, and the (8n-7) th row, (8n-5) th row, (8n-3) ) The operation of reading the mixed line (8n-1) and the operation of reading the 8n line alone may be repeated.

  FIG. 6 is an equivalent circuit diagram of the solid-state imaging device 50 according to the second embodiment of the present invention. This embodiment corresponds to claims 1, 2, 6, and 7. In addition, at the end of the reference numerals of some elements in the figure, 1, 2, 3, 4, 5 indicating arrangement rows are added, and a, b, c, d indicating the correspondence with the arrangement columns are added. did. The “correspondence with the arrangement column” is the same as in the first embodiment. When it is not necessary to distinguish between rows and columns, the last 1, 2, a, b, etc. of the reference numerals are omitted as appropriate.

  As shown in the figure, a solid-state imaging device 50 includes a red pixel R, a green pixel G, and a blue pixel B arranged in a Bayer array, a vertical scanning circuit 60, and a NAND gate Na that connects each pixel to the vertical scanning circuit 60 for each row. The AND gate An, the vertical signal line VSL arranged for each pixel column, the constant current source CS connected to one end of the vertical signal line VSL, and the green arranged on the other end of the vertical signal line VSL. A horizontal signal line 70, a red / blue horizontal signal line 72, and a horizontal scanning circuit 78 are provided.

  Further, output buffer amplifiers 32, 34, output terminals Gout, R / Bout, and horizontal reset transistors TRg, TRrb are connected to output ends of the green horizontal signal line 70 and the red-blue horizontal signal line 72, respectively. . Note that no pixel is arranged in the first column of the odd-numbered rows. Further, in the figure, since it is complicated, the number of pixels is described as 5 × 4. However, more pixels are actually arranged.

The main difference between the second embodiment and the first embodiment is that in this embodiment, there is one vertical signal line between pixel columns, and the other end of each vertical signal line VSL is connected to a green horizontal signal. The circuit configuration is connected to the line 70 or the red / blue horizontal signal line 72.
In this embodiment, the other end of each vertical signal line VSL is branched into two, and both of the branched branches are the same horizontal signal line (green horizontal signal line 70, red) by a similar circuit arranged separately. One of the blue horizontal signal lines 72). The vertical signal lines (VSLa, VSLc) connected to the green horizontal signal line 70 and the vertical signal lines (VSLb, VSLd) connected to the red / blue horizontal signal line 72 are alternately arranged in a column sequence. .

  One of the branches at the other end of the vertical signal line VSL is an XY selection transistor Qx, a relay transistor Dx which is an n-channel depletion type MOS transistor, a CDS capacitor Cx, a column selection transistor Thx, and the green horizontal signal line 70 or red-blue. It is connected to the horizontal signal line 72. The other branched side passes through the XY selection transistor Qy, the relay transistor Dy that is an n-channel depletion type MOS transistor, the CDS capacitor Cy, and the column selection transistor Thy, and the same horizontal signal line (green horizontal signal line 70 or red) as the branched one. It is connected to the blue horizontal signal line 72). Here, for easy identification, the letter x is included in the sign of the element corresponding to one of the branches (on the vertical scanning circuit 60 side in the figure), and the letter y is included in the other.

  The XY selection transistor Qx receives the drive voltage φSHVx at the gate common to all columns, and the XY selection transistor Qy receives the drive voltage φSHVy at the gate common to all columns. Each relay transistor Dx (Dy) has a source connected to the ground line GND via a separate constant current source Zx (Zy), and a drain connected to the power supply line VCC. In addition, since it becomes complicated in the drawing, only a part of the constant current sources Zx and Zy is indicated.

  Further, at the other end of each vertical signal line VSL, one of the branches is connected to a CDS transistor Tx that performs correlated double sampling processing together with the CDS capacitor Cx, and the other is subjected to correlated double sampling processing together with the CDS capacitor Cy. A CDS transistor Ty to be performed is connected. The CDS transistor Tx receives the FPN accumulation pulse φcx at the gate in common for all the columns, and switches to the conductive or nonconductive state. The CDS transistor Ty receives the FPN accumulation pulse φcy at the gate in common for all columns, and switches to a conductive or non-conductive state.

  The gates of the column selection transistors Thx and Thy receive the driving voltage φGH common to the two pixel columns from the horizontal scanning circuit 78, and are switched to the conductive or nonconductive state. Therefore, if the column selection transistors Thx and Thy and the XY selection transistors Qx and Qy are all conductive, it is equivalent to a plurality of capacitors (CDS capacitors Cx and Cy) being connected in parallel as described in the claims. is there.

  FIG. 7 is a circuit diagram focusing on the connection between the vertical scanning circuit 60 and each pixel in FIG. Similarly to the first embodiment, the vertical scanning circuit 60 has one output signal line for each pixel row, and these output signal lines receive the row selection signals OPT1 to OPTn from the vertical scanning circuit 60, respectively. receive. The NAND gate Na and the AND gate An are the same as in the first embodiment in that the row selection signal OPT is received at one input terminal, but the input voltages to the other input terminal are different.

  That is, in each row, which of the drive voltages φTG1 and φTG2 is input to the other input terminal of the NAND gate Na and which of the drive voltages φRSG1 and φRSG2 is input to the other input terminal of the AND gate An is different. Specifically, in the (4n-3) th and (4n-2) th rows, the other input terminal of the NAND gate Na receives the drive voltage φTG1, and the other input terminal of the AND gate An receives the drive voltage φRSG1. . On the other hand, in the (4n-1) th row and the 4nth row, the other input terminal of the NAND gate Na receives the drive voltage φTG2, and the other input terminal of the AND gate An receives the drive voltage φRSG2.

In the above circuit configuration, the correspondence with the claims is, for example, as follows.
The pair of capacitances recited in the claims corresponds to the CDS capacitors Cx and Cy. The vertical signal line A described in the claims corresponds to the vertical signal lines VSLa and VSLac. The vertical signal line B described in the claims corresponds to the vertical signal lines VSLb and VSLd. The switching circuit according to the present invention includes XY selection transistors Qx and Qy, relay transistors Dx and Dy, constant current sources Zx and Zy, CDS transistors Tx and Ty, column selection transistors Thx and Thy, horizontal reset transistors TRg and TRrb, horizontal scanning This corresponds to the circuit 78. The correspondence of other elements is the same as in the first embodiment.

  FIG. 8 is a timing chart showing voltage waveforms at various parts when normal reading is performed in the solid-state imaging device 50 described above. The circuit operation will be described below with reference to FIGS. Note that readout scanning is the same in units of four rows. The main difference in readout scanning of each row is that the driving voltages φRSG1 and φTG1 are used in the (4n-3) th and (4n-2) th rows, and the driving voltage φRSG2 is used in the (4n-1) th and 4nth rows. φTG2 is used.

  First, as in the first embodiment, a start pulse STV and clock signals CLKV1, CLKV2 are input to the vertical scanning circuit 60. As a result, the row selection signal output from the vertical scanning circuit 60 is high only at OPT1, and the first row is selected. Immediately after the clock signals CLKV1 and CLKV2 are input, the transfer gates FW are off in all the pixels and the gate voltages of the JFETs are reset (selection in the second and subsequent rows), as in the first embodiment. The same applies immediately after).

Next, the drive voltages φRSG1, φSHVx, φSHVy are simultaneously switched to a high level. As a result, in the first row, the output voltage of the AND gate An1 is switched to the high level, the reset gate RG is turned off, and the gate of the JFET is in a floating state. Further, the XY selection transistors Qx and Qy in all columns are turned on.
Next, the FPN accumulation pulses φcx and φcy are simultaneously switched to a high level, all the CDS transistors Tx and Ty are turned on, and one electrode of the CDS capacitors Cx and Cy is connected to the constant voltage source Vref. At this time, the signal charge of the photodiode PD is not yet transferred to the gate of the JFET, and a voltage corresponding to the fixed pattern noise component is output from the source of the JFET, and this voltage is output to the gates of the relay transistors Dx and Dy. Applied. As a result, the source voltages of the relay transistors Dx and Dy are in accordance with the gate voltages, and the CDS capacitors Cx and Cy are charged to a voltage corresponding to the fixed pattern noise component. Thereafter, the FPN accumulation pulses φcx and φcy are simultaneously switched to a low level.

  Next, the drive voltage φTG1 is switched to a high level. Thereby, in the first row, the output voltage of the NAND gate Na1 is switched to a low level, the transfer gate FW is turned on, and the signal charge of the photodiode PD is transferred to the gate of the JFET. The JFET outputs a signal voltage (pixel signal) corresponding to the amount of charge accumulated in the gate from the source. As a result, the pixel signals are charged in the CDS capacitors Cx and Cy through the relay transistors Dx and Dy so that the fixed pattern noise component charged earlier is canceled out.

  The XY selection transistors Qx and Qy are elements having the same parameters such as the threshold voltage, and the relay transistors Dx and Dy are also elements having the same parameters. Therefore, in normal reading, the CDS capacitors Cx and Cy are both charged to the same voltage (the same applies to the second and subsequent rows). That is, the pixel signals of the green pixels G in the second and fourth columns in the first row are charged equally to the CDS capacitors Cx and Cy in the a and c columns, respectively, and the red pixels R in the third and fifth columns in the first row. Are charged equally to the CDS capacitors Cx and Cy in the b and d columns, respectively. Thereafter, the drive voltage φTG1 is switched to a low level.

  Next, the drive voltages φRSG1, φSHVx, φSHVy are simultaneously switched to a low level. As a result, the transfer gate FW in the first row is turned off, and the XY selection transistors Qx and Qy in all the columns are turned off. Further, the relay transistors Dx and Dy of all the columns have the gates in a floating state, but are MOS transistors, so that the charges accumulated in the gates during the period in which φTG1 is at a high level are held, and the source voltage does not change. In this state, the operation of resetting the voltages of the green horizontal signal line 70 and the red-blue horizontal signal line 72 to Vref and the operation of turning on the horizontal shift register of the horizontal scanning circuit 78 in order are repeated. Is read out horizontally.

Specifically, first, the horizontal reset pulse voltage φRSTH is switched to a high level. As a result, the horizontal reset transistors TRg and TRrb are turned on, and the voltages of the green horizontal signal line 70 and the red / blue horizontal signal line 72 are reset to Vref. Thereafter, the horizontal reset pulse voltage φRSTH is switched to a low level.
Next, the horizontal scanning circuit 78 switches the drive voltage φGHab corresponding to the a and b columns to a high level. As a result, the column selection transistors Thxa, Thya, Thxb, and Thyb are turned on, the pixel signals charged in the CDS capacitors Cxa and Cya in the a column are read out to the green horizontal signal line 70, and the CDS capacitors Cxb and Cyb in the b column are charged. The pixel signal thus read is read out to the red / blue horizontal signal line 72.

Here, the signal voltage output to the green horizontal signal line 70 is the same as that in the normal reading in the first embodiment in consideration of the parasitic capacitance. That is, the output voltage value of the JFET source is JS, the capacitance values of the CDS capacitors Cx and Cy are CFx and CFy, the parasitic capacitance value of the green horizontal signal line 70 is CFG, and the output voltage of the green horizontal signal line 70 is Vgreen. For example, the following equation is obtained.
Vgreen = JS × (CFx + CFy) / (CFx + CFy + CFG) (4)
The output voltage of the red / blue horizontal signal line 72 is the same. In the present embodiment, as an example, CFx = CFy.

  This is the reading of the pixel signals in the second and third columns in the first row. Next, the horizontal reset pulse voltage φRSTH is switched to a high level, the voltages of the green horizontal signal line 70 and the red-blue horizontal signal line 72 are reset, and then the horizontal reset pulse voltage φRSTH is switched to a low level. Then, the drive voltage φGHcd corresponding to the c and d columns is switched to a high level, and the pixel signals in the fourth and fifth columns are similarly read out. By repeating such an operation, the pixel signal in the first row is read every two columns. This is the “first row selection period” in FIG.

  Next, after the clock signals CLKV1 and CLKV2 are input to the vertical scanning circuit 60 and the second row is selected, the drive voltages φRSG1, φSHVx, and φSHVy are switched to a high level. Thereafter, as in the case of the first row, the FPN accumulation pulses φcx and φcy are simultaneously switched to a high level to charge the CDS capacitors Cx and Cy with fixed pattern noise components, and then the FPN accumulation pulses φcx and φcy are simultaneously set to a low level. Switch to.

  Next, the drive voltage φTG1 is switched to a high level. Thus, in the second row, the output voltage of the NAND gate Na2 is switched to a low level, the transfer gate FW is turned on, and the signal charge of the photodiode PD is transferred to the gate of the JFET. Accordingly, the pixel signals of the green pixels G in the first and third columns in the second row are charged in the CDS capacitors Cx and Cy in the a and c columns, respectively. The pixel signals of the blue pixels B in the second and second columns in the second row are charged in the CDS capacitors Cx and Cy in the b and d columns, respectively.

Next, the drive voltages φRSG1, φSHVx, φSHVy are switched to a low level, and the XY selection transistors Qx, Qy of all the columns are turned off. Then, as in the case of the first row, horizontal readout of the pixel signals of the second row is performed every two columns.
Next, the clock signals CLKV1 and CLKV2 are input to the vertical scanning circuit 60, and after selecting the third row, the drive voltages φRSG2, φSHVx, and φSHVy are simultaneously switched to a high level. Thereafter, as in the first and second rows, the FPN accumulation pulses φcx and φcy are switched to a high level, and the CDS capacitors Cx and Cy are charged with a fixed pattern noise component, and then the FPN accumulation pulses φcx and φcy are switched to a low level. .

Next, the drive voltage φTG2 is switched to a high level, and the pixel signals in the second to fifth columns in the third row are charged in the CDS capacitors Cx and Cy in the a to d columns, respectively. Next, the drive voltages φRSG2, φSHVx, φSHVy are switched to a low level, the XY selection transistors Qx, Qy of all the columns are turned off, and then the pixel signals in the third row are read in the horizontal direction in the same manner as described above.
Next, after the clock signals CLKV1 and CLKV2 are input to the vertical scanning circuit 60 and the fourth row is selected, the drive voltages φRSG2, φSHVx, and φSHVy are switched to a high level. Thereafter, the FPN accumulation pulses φcx and φcy are switched to a high level, the fixed pattern noise components are charged in the CDS capacitors Cx and Cy, and then the FPN accumulation pulses φcx and φcy are switched to a low level.

  Next, the drive voltage φTG2 is switched to a high level, and the pixel signals in the first to fourth columns in the fourth row are charged in the CDS capacitors Cx and Cy in the a to d columns, respectively. Next, after the drive voltages φRSG2, φSHVx, and φSHVy are switched to a low level, the pixel signals in the fourth row are read out in the horizontal direction in the same manner as described above. By repeating the above operation, the pixel signals in the fifth and subsequent rows are similarly read out. The above is the description of the normal reading operation.

FIG. 9 is a timing chart showing voltage waveforms at various parts when thinning readout is performed in the solid-state imaging device 50. Hereinafter, the thinning-out reading operation will be described with reference to FIGS. Also in this case, readout scanning is the same in units of four rows.
First, the start pulse STV and the clock signals CLKV1 and CLKV2 are input to the vertical scanning circuit 60 in the same procedure as in the thinning readout in the first embodiment, and the first and third rows are selected simultaneously.

  Next, the drive voltages φRSG1 and φSHVx are simultaneously switched to a high level. As a result, the gates of the JFETs in the first row are in a floating state, and only one Qx of the XY selection transistors in all the columns is turned on. That is, since the selected AND gate An3 in the third row receives the drive voltage φRSG2 instead of the drive voltage φRSG1, the JFET in the third row remains reset.

Next, the FPN accumulation pulse φcx is switched to a high level. As a result, only one Tx of the CDS transistors in all the columns is turned on, and the CDS capacitor Cx is charged with a fixed pattern noise component. Thereafter, the FPN accumulation pulse φcx is switched to a low level.
Next, the drive voltage φTG1 is switched to a high level. Thereby, in the first row, the signal charge of the photodiode PD is transferred to the gate of the JFET, and the CDS capacitor Cx is charged with the pixel signal in each column of the first row. Next, after the drive voltage φTG1 is switched to a low level, the drive voltages φRSG1 and φSHVx are simultaneously switched to a low level. Thereby, the transfer gate FW in the first row is turned off, the gate of the JFET in the first row is reset, and the XY selection transistor Qx is turned off.

  Next, the drive voltages φRSG2 and φSHVy are simultaneously switched to a high level. As a result, the gates of the JFETs in the third row are in a floating state, and only one Qy of the XY selection transistors in all the columns is turned on. Note that the JFET in the first row remains reset. Next, the FPN accumulation pulse φcy is switched to a high level. As a result, only one Ty of the CDS transistors in all the columns is turned on, and the CDS capacitor Cy is charged with a fixed pattern noise component. Thereafter, the FPN accumulation pulse φcy is switched to a low level.

  Next, the drive voltage φTG2 is switched to a high level. As a result, in the third row, the signal charge of the photodiode PD is transferred to the gate of the JFET, and the CDS capacitor Cy is charged with the pixel signal in each column of the third row. Next, after the drive voltage φTG2 is switched to a low level, the drive voltages φRSG2 and φSHVy are simultaneously switched to a low level. As a result, the transfer gate FW in the third row is turned off, the gate of the JFET in the third row is reset, and the XY selection transistor Qy is turned off. Since the relay transistors Dx and Dy are MOS transistors, the same voltage (signal voltage) as that immediately before the XY selection transistors Qx and Qy are turned off is continuously output from the source. In this state, the pixel signal is read out in the horizontal direction as in the case of normal reading.

However, since the CDS capacitor Cx is charged with the pixel signal of the first row and the CDS capacitor Cy is charged with the pixel signal of the third row, the output voltage of the green horizontal signal line 70 is the first voltage. Similar to the thinning-out readout of the embodiment, the sum is averaged. Accordingly, if the output voltage value of the source of the JFET in the first row is JS1, and the output voltage value of the source of the JFET in the third row is JS3, the output voltage Vgreen of the green horizontal signal line 70 is as follows: .
Vgreen = (JS1 × CFx + JS3 × CFy) / (CFx + CFy + CFH)
... (5)
The same applies to the output voltage of the red / blue horizontal signal line 72. This is the period of “1, 3rd row horizontal readout” in FIG.

  Next, the clock signals CLKV1 and CLKV2 are input to the vertical scanning circuit 8 one pulse at a time, the vertical shift register is shifted by one, and the second and fourth rows are selected simultaneously. Next, the drive voltages φRSG2, φSHVx, φSHVy are simultaneously switched to a high level. As a result, the gates of the JFETs in the fourth row are in a floating state, and the XY selection transistors Qx and Qy in all the columns are turned on. Although the second row is also selected, since the AND gate An2 in the second row receives φRSG1 instead of the drive voltage φRSG2, the JFET in the second row remains reset.

  Next, the FPN accumulation pulses φcx and φcy are simultaneously switched to a high level. As a result, the CDS capacitors Cx and Cy are charged with the fixed pattern noise component of each pixel in the fourth row. That is, as with the thinning readout in the first embodiment, the second row is selected, but the pixel signal is not read out, and the charging voltages of the CDS capacitors Cx and Cy are the same for each column. Thereafter, the FPN accumulation pulses φcx and φcy are switched to a low level. Next, the drive voltage φTG2 is switched to a high level. Thereby, the CDS capacitors Cx and Cy are charged with the pixel signals of the respective columns in the fourth row. Next, after the drive voltage φTG2 is switched to a low level and the drive voltages φRSG2, φSHVx, and φSHVy are switched to a low level, the pixel signals in the fourth row are read in the horizontal direction in the same manner as in the normal reading.

Next, the clock signals CLKV1 and CLKV2 are inputted to the vertical scanning circuit 60 every three pulses, the vertical shift register is shifted by three, and the fifth and seventh rows are selected simultaneously. Thereafter, the pixel signals in the 5th and 7th rows are read out by averaging the pixel signals in the same manner as in the 1st and 3rd rows.
Next, the clock signals CLKV1 and CLKV2 are input to the vertical scanning circuit 60 one pulse at a time, the vertical shift register is shifted by one, and the sixth and eighth rows are selected simultaneously. Thereafter, the pixel signal of the eighth row is read out independently by the same scanning as in the case of the fourth row. By repeating the above operation, the pixel signals in the ninth and subsequent rows are similarly read out. That is, after the pixel signals of the (4n-3) th row and the (4n-1) th row are mixed and read, the operation of reading the pixel signal of the 4nth row alone is repeated. The above is the description of the thinning readout operation.

  As described above, also in the second embodiment, the pixel signal of each pixel is first read as the source voltage of the JFET, and is output as a voltage to the green horizontal signal line 70 and the red-blue horizontal signal line 72. In the thinning-out readout of the present embodiment, the (4n-3) th and (4n-1) -th rows are the same as in the thinning-out readout of the first embodiment in the Bayer array in which the odd-numbered rows are GR rows. The mixed read operation and the fourth read operation are repeated. Therefore, the same effect as the first embodiment can be obtained.

  Further, in the present embodiment, only one vertical signal line between the pixel columns is required, and wiring becomes easy. In the present embodiment, the drive voltages φSHVx and φSHVy and the two FPN accumulation pulses φcx and φcy are used instead of the eight selection drive voltages φPαL to φPδR and one FPN accumulation pulse φc. That is, there are fewer types of drive voltages than in the first embodiment.

  In the thinning-out readout according to the present embodiment, mixed readout is performed on the GR row and the GB row is read out independently, but the opposite is also possible. That is, the operation of independently reading the (4n-3) th row that is the GR row and the operation of reading the mixed (4n-2) th and 4nth rows that are the GB row may be sequentially repeated. Also in this case, the sampling centroids are equally spaced. Alternatively, the operation of mixing and reading the pixel signals of the (4n-3) th row and the (4n-1) th row and the operation of reading the pixel signals of the (4n-2) th row and the 4nth row are repeated. Also good. In this case, the same effect as described above can be obtained except that the sampling centroids are not equally spaced.

  The example in which two similar circuits are connected in parallel between the vertical signal line VSL and the green horizontal signal line 70 (or the red-blue horizontal signal line 72) has been described. However, three or more similar circuits have been described. May be connected in parallel. The “similar circuit” here corresponds to the XY selection transistor Qx, the relay transistor Dx, the constant current source Zx, the CDS capacitor Cx, the CDS transistor Tx, and the column selection transistor Thx. In that case, the number corresponding to the drive voltage φSHVx may be input by the number of parallel connections. If, for example, four “similar circuits” are connected in parallel, the (8n-7) th row, the (8n-5) th row, and (8n-3) are the same as those described in the supplementary items of the first embodiment. ) The operation of reading the mixed line and the (8n-1) th row and the operation of reading the 8nth row alone can be repeated.

  In the first and second embodiments, an example in which the pixel array is a Bayer square array has been described. However, the present invention is also applicable to a G stripe RB line sequential square array. Specifically, in the second embodiment, pixels in even rows are arranged on the vertical scanning circuit 60 side with respect to the vertical signal line VSL connected to the pixels. Therefore, in the second embodiment, if the even row pixels are arranged on the right side of FIG. 6 with respect to the vertical signal line VSL while the connection relation between the even row pixels and the vertical signal line VSL is the same, The present invention can be applied after changing the pixel arrangement to the G stripe RB line sequentially.

  The present invention is not limited to the primary colors of red, green, and blue, and can be applied to, for example, a complementary color system. Furthermore, the present invention is not limited to the square arrangement, but can be applied to a honeycomb arrangement.

  As described above in detail, the present invention can be used greatly in the field of solid-state imaging devices.

1 is an equivalent circuit diagram of a solid-state imaging device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram focusing on a connection portion between a vertical scanning circuit and each pixel in FIG. 1. FIG. 2 is a circuit diagram showing details of a green selection circuit MXG and a red / blue selection circuit MXR / B in FIG. 1. FIG. 3 is a timing diagram illustrating voltage waveforms of respective units when normal reading is performed in the solid-state imaging device according to the first embodiment. FIG. 3 is a timing diagram illustrating voltage waveforms of respective units when performing thinning readout in the solid-state imaging device according to the first embodiment. It is an equivalent circuit schematic of the solid-state image sensor in the 2nd Embodiment of this invention. FIG. 7 is a circuit diagram focusing on a connection portion between the vertical scanning circuit and each pixel in FIG. 6. FIG. 10 is a timing diagram illustrating voltage waveforms of respective units when performing normal reading in the solid-state imaging device according to the second embodiment. FIG. 10 is a timing diagram illustrating voltage waveforms of respective units when performing thinning readout in the solid-state imaging device according to the second embodiment.

Explanation of symbols

2 Solid-state imaging device 8 Vertical scanning circuit 20 Green horizontal signal line 24 Red-blue horizontal signal line 30 Horizontal scanning circuits 32 and 34 Output buffer amplifier 50 Solid-state imaging device 60 Vertical scanning circuit 70 Green horizontal signal line 72 Red-blue horizontal signal line 78 Horizontal Scan circuit An1-An5 AND gate B Blue pixel BiL, BiR Bipolar transistors CcL, CcR, Cxa-Cxd, Cya-Cyd CDS capacitors CSL, CSR, CSML, CSMR, CSa-CSd, Zx-Zy constant current sources Dxa-Dxd, Dya to Dyd Relay transistor FW Transfer gate G Green pixel Gout Output terminals Iα, Iβ, Iγ, Iδ Input signal line JFET Junction field effect transistor MXG Green selection circuit MXR / B Red-blue selection circuit Na1 to Na5 Nand gate PD Photodiode QαL, QαR, QβL, Q βR, QγL, QγR, QδL, QδR Switches Qxa to Qxd, Qya to Qyd XY selection transistor R Red pixel R / Bout Output terminal RG Reset gate Tca to Tcd, Txa to Txd, Tya to Tyd CDS transistors Tha to Thd, Thxa to Thxd, Thya to Thyd Column selection transistor TRg, TRrb Horizontal reset transistor VL, VR, VSLa to VSLd Vertical signal line

Claims (7)

A plurality of pixels arranged two-dimensionally along vertical columns and horizontal rows;
A plurality of vertical transfer units which are respectively arranged corresponding to the columns of pixels and connected to the plurality of pixels, and which transfer pixel signals generated by the pixels in the vertical direction;
A solid-state imaging device comprising: at least one horizontal signal line to which the pixel signals from a plurality of the vertical transfer units are transferred;
Between the horizontal signal line and the plurality of vertical transfer units, each having a plurality of capacitors arranged for each of the vertical transfer units corresponding to the plurality of vertical transfer units,
The plurality of capacitors are connected in parallel between the corresponding vertical transfer unit and one horizontal signal line, and are charged by receiving the pixel signal from the vertical transfer unit,
A solid-state imaging device comprising: a switching circuit that transfers the pixel signal to the horizontal signal line by connecting a plurality of the capacitors to the horizontal signal line. A plurality of pixels arranged two-dimensionally along vertical columns and horizontal rows;
A plurality of vertical transfer units which are respectively arranged corresponding to the columns of pixels and connected to the plurality of pixels, and which transfer pixel signals generated by the pixels in the vertical direction;
A solid-state imaging device comprising a horizontal transfer unit to which the pixel signals from a plurality of vertical transfer units are transferred,
A pair of capacitors arranged for each of the plurality of vertical transfer units, and a switching circuit that transfers the pixel signal to the horizontal transfer unit by connecting the pair of capacitors to the horizontal transfer unit,
The pair of capacitors are connected in parallel to the corresponding vertical transfer unit, are charged by receiving the pixel signal from the vertical transfer unit,
When thinning readout is performed, the switching circuit charges one of the pair of capacitors with the pixel signal of a certain row, and the other charges the pixel signal of another row with the pair of capacitors. The charged pixel signal is transferred to the horizontal transfer unit so as to be averaged. The solid-state imaging device according to claim 2,
The plurality of pixels include a first color component pixel arranged in a pine or stripe shape, and a second color component pixel and a third color component pixel arranged line-sequentially between the first color component pixels. ,
The pair of capacitors is one of a first capacitor pair that charges the pixel signal of the first color component pixel and a second capacitor pair that charges the pixel signal of the second and third color component pixels. And
Each of the vertical transfer units includes a first vertical signal line and a second vertical signal line that transfer the pixel signals of one type or two types of color components,
The horizontal transfer unit includes a first horizontal signal line and a second horizontal signal line,
The switching circuit selects one of the first and second vertical signal lines to which the pixel signal of the first color component pixel is transferred and connects the selected one to the first capacitor pair. After selecting and transferring the pixel signal of the third color component pixel to the second capacitor pair, the first capacitor pair is connected to the first horizontal signal line, and the second capacitor pair is connected to the second capacitor pair. A solid-state image sensor connected to the second horizontal signal line. The solid-state imaging device according to claim 3,
The first vertical signal line is connected to the pixels in the (4n-3) th row and the (4n-2) th row,
The second vertical signal line is connected to the pixels in the (4n-1) th row and the 4nth row,
When thinning-out reading is performed, the switching circuit connects the first vertical signal line to one of the pair of capacitors and connects the second vertical signal line to the other, and (4n-3) rows. An operation of adding and averaging the pixel signals of the first and (4n-1) th rows, and an operation of reading the pixel signals of the 4nth row by connecting the second vertical signal line to the pair of capacitors. A solid-state imaging device that is repeated (where n is a natural number). The solid-state imaging device according to claim 3,
The first vertical signal line is connected to the pixels in the (4n-3) th row and the (4n-2) th row,
The second vertical signal line is connected to the pixels in the (4n-1) th row and the 4nth row,
When thinning-out reading is performed, the switching circuit connects the first vertical signal line to the pair of capacitors, reads the pixel signal in the (4n-3) th row, and one of the pair of capacitors. The first vertical signal line is connected to the other and the second vertical signal line is connected to the other, and the pixel signals of the (4n-2) th and 4nth rows are summed and averaged and read out. A solid-state imaging device characterized by repetition. The solid-state imaging device according to claim 2,
The plurality of pixels include a first color component pixel arranged in a pine or stripe shape, and a second color component pixel and a third color component pixel arranged line-sequentially between the first color component pixels. ,
The vertical transfer unit is one of a vertical signal line A connected to the first color component pixel and a vertical signal line B connected to the second and third color component pixels;
The plurality of vertical signal lines A and the plurality of vertical signal lines B are alternately arranged in a column sequence,
The pair of capacitors is charged with only the pixel signal from any one of the vertical signal lines A or the pixel signal from any one of the vertical signal lines B,
The horizontal transfer unit includes a first horizontal signal line and a second horizontal signal line,
The switching circuit connects the pair of capacitors to which the pixel signal from the vertical signal line A is charged to the first horizontal signal line, and the pair to which the pixel signal from the vertical signal line B is charged. A solid-state imaging device, wherein the capacitor is connected to the second horizontal signal line. The solid-state imaging device according to claim 6,
When thinning-out reading is performed, the switching circuit reads out the pixel signals of the (4n-3) th row and the (4n-1) th row so that the pixel signals are summed and averaged, and the pixel signal of the 4nth row. Or an operation of reading out the pixel signals in the (4n-3) th row, and an operation of reading out the pixel signals in the (4n-2) th and 4nth rows. The solid-state image sensor characterized by repeating.

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