JP5971959B2 - Matrix substrate, detection apparatus, and detection system - Google Patents

Description

  The present invention relates to a matrix substrate, a detection apparatus, and a detection system that are applied to medical image diagnostic apparatuses, nondestructive inspection apparatuses, analysis apparatuses using radiation, and the like.

2. Description of the Related Art In recent years, thin film semiconductor manufacturing technology has been developed in which a matrix substrate having an array of pixels (pixel array) in which switch elements such as TFTs (thin film transistors) and conversion elements such as photoelectric conversion elements are combined, and a detection device and a radiation detection device using the matrix substrate It is also used.
In such a detection device, in recent years, it has been studied to build a demultiplexer on the same substrate as the pixel array. Patent Document 1 discloses the following content. A plurality of detection devices are provided corresponding to the plurality of gate lines, respectively, between the external gate terminals provided to correspond one-to-one with the terminals of the external shift register and the plurality of gate lines (drive lines). It has a demultiplexer composed of TFTs. Then, a clock signal (control signal) is given to all of the plurality of TFTs via the clock line (control wiring), so that the demultiplexer sequentially selects the drive lines of the pixel array.

Japanese Patent Laid-Open No. 08-256292

However, in Patent Document 1, every time the demultiplexer sequentially selects the drive lines of the pixel array, a clock signal (control signal) is supplied to all the plurality of TFTs via the clock line (control wiring). Therefore, the frequency of the clock signal (control signal) on the clock line (control wiring) is increased. In particular, the frequency of the clock signal (control signal) is increased when the number of drive lines increases due to the increase in area or definition of the pixel array, or when the gate line scanning time is shortened for high-speed operation. Becomes higher. For this reason, power consumption at the clock line (control wiring) increases.
Accordingly, an object of the present invention is to provide a detection device, a detection system, and a detection device driving method capable of reducing power consumption while limiting the number of external gate terminals.

In view of the above problems, the matrix substrate of the present invention has a plurality of pixels arranged in a matrix, and a plurality of drive lines commonly connected to the plurality of pixels in the row direction are arranged side by side along the column direction. The drive circuit for driving the pixel and the connection terminals for electrically connecting the plurality of drive lines are provided in a number smaller than the number of the plurality of drive lines, and have a plurality of unit circuits. A demultiplexer electrically connects the plurality of connection terminals and the plurality of drive lines, and each of the plurality of unit circuits includes a predetermined connection terminal and a plurality of the plurality of connection terminals. A plurality of transistors electrically connecting a plurality of predetermined two or more drive lines of the drive lines, and a control electrode of the plurality of transistors for supplying a conduction voltage and a non-conduction voltage of the transistors; Multiple control arrangements A matrix substrate that is electrically connected to the plurality of unit circuits comprises a first unit circuit, wherein the second unit circuit adjacent to the first unit circuit, the first The control terminal of the second transistor located closest to the second unit circuit among the first transistor and the second transistor included in the plurality of transistors included in the unit circuit, and the second unit circuit a control terminal of the third transistor located in the most the first unit circuit side among the plurality of transistors you located far from the contained and the second of said first transistor than the transistor, the said are connected to the same control wiring among the plurality of control lines, a control terminal of the first transistor is electrically different other control wiring and the same control line of said plurality of control lines Characterized in that it is connected.
Further, the detection device of the present invention is a detection device comprising the matrix substrate, the drive circuit, and a control circuit for supplying a conduction voltage and a non-conduction voltage of the transistor to the control wiring, The control circuit supplies a conduction voltage and a non-conduction voltage of the transistor to the control wiring at a frequency that is half the frequency of driving the pixel.

  According to the present invention, since the frequency of the control signal (clock signal) can be reduced, power consumption in the clock line can be reduced. Accordingly, the present invention can provide a detection device, a detection system, and a detection device driving method capable of reducing power consumption while limiting the number of external gate terminals.

1A and 1B are an equivalent circuit diagram and a timing chart for explaining a first embodiment according to a detection device and a matrix substrate of the present invention. It is a cross-sectional schematic diagram of a pixel related to the detection device and the matrix substrate and a conceptual diagram of the detection device. It is an equivalent circuit diagram for demonstrating 2nd Embodiment which concerns on the detection apparatus and matrix substrate of this invention. It is a timing chart for demonstrating 2nd Embodiment which concerns on the detection apparatus and matrix substrate of this invention. It is the conceptual diagram and equivalent circuit diagram of a detection apparatus for demonstrating 3rd Embodiment which concerns on the detection apparatus and matrix substrate of this invention. It is a conceptual diagram of the detection apparatus for demonstrating 3rd Embodiment which concerns on the detection apparatus and matrix substrate of this invention. It is a timing chart for demonstrating 3rd Embodiment which concerns on the detection apparatus and matrix substrate of this invention. It is a conceptual diagram for demonstrating the application example to the detection system of the detection apparatus of this invention.

(First embodiment)
As shown in FIG. 1A, the matrix substrate and the detection device for the detection device of the present embodiment have a pixel array including a plurality of pixels 101 arranged in a matrix on a support substrate 100. The pixel 101 is for outputting an electrical signal corresponding to radiation or light, and includes a conversion element 102 that converts the radiation or light into electric charge, and a switch element that outputs an electric signal corresponding to the electric charge generated by the conversion element 102. 103. Here, in this embodiment, the conversion element 102 includes a scintillator that converts radiation into light and a photoelectric conversion element that converts the light into electric charge, but the present invention is not limited thereto. As the conversion element 102, a direct conversion element that directly converts radiation into electric charges without using a scintillator may be used. As the switch element 103, an amorphous silicon or polycrystalline silicon thin film transistor (TFT) can be used. Here, silicon can be used for the TFT, but the present invention is not limited to this, and other semiconductor materials such as germanium may be used. Preferably, a polycrystalline silicon TFT is used as the switch element 103. The first main electrode of the switch element 103 is electrically connected to the first electrode of the conversion element 102, and the bias line 106 is electrically connected to the second electrode of the conversion element 102. In FIG. 1A, the bias line 106 extends in the column direction, and is commonly connected to the plurality of conversion elements 102 arranged in the column direction via the second electrodes. A plurality of bias lines 106 are provided side by side along the row direction, and the plurality of bias lines 106 are coupled by a common line 107 to form a common bias line 108. The common bias line 108 is electrically connected to an external power supply circuit (not shown) via a connection terminal 109. A signal line 105 is electrically connected to the second main electrode of the switch element 103. The signal line 105 extends in the column direction, and is connected in common to the plurality of switch elements 103 arranged in the column direction via their second main electrodes. A plurality of signal lines 105 are provided along the row direction, and each signal line 105 is electrically connected to an external readout circuit (not shown) via a connection terminal 119. . The connection terminals 109 and 119 are disposed between the end portion of the support substrate 100 and the effective pixel region.

  A drive line 104 extending in the row direction is electrically connected to the control electrode of the switch element 103. The drive line 104 is commonly connected to the switch elements 103 of a plurality of pixels arranged in the row direction via their control electrodes. The plurality of drive lines 104 are provided side by side along the column direction, and are electrically connected to an external drive circuit (not shown) via the connection terminals 110. Here, the connection terminal 110 is disposed on the support substrate 100 between an end of a certain side of the support substrate 100 and the pixel array. Further, the connection terminals 110 are provided in a number smaller than the number of drive lines 104, in other words, the number of rows of pixels in the pixel array. A demultiplexer 111 that connects the plurality of connection terminals 110 and the plurality of drive lines 104 is disposed between the plurality of connection terminals 110 and the plurality of drive lines 104. The demultiplexer 111 includes two or more first transistors provided in a one-to-one correspondence with each of the two or more drive lines 104 between one connection terminal 110 and the corresponding two or more drive lines 104. (First thin film transistor) (first TFT) 112 is included. The first TFT 112 corresponds to a unit circuit transistor in the present invention. In the present invention, an element existing between one connection terminal 110 and two or more corresponding drive lines 104 is referred to as a demultiplexer unit circuit. The element related to the drive line 104 corresponding to the first row of each unit circuit is the first level, the element related to the drive line 104 corresponding to the second row is the second level, and the third level and the fourth level thereafter. Called. FIG. 1A shows a form in which each unit circuit includes first and second stage elements.

In the present embodiment, two first TFTs 112 of each unit circuit are provided. The first TFT 112 is for supplying the conduction voltage of the switch element 103 to each of the two or more drive lines 104. One of the two main electrodes is electrically connected to the connection terminal 110, and the other is It is electrically connected to the corresponding drive line 104. This conduction voltage is a voltage for setting the pixel in a selected state, and corresponds to the first voltage of the present invention. In addition, first control wirings 114 a and 114 b are provided for supplying the conduction voltage and non-conduction voltage of the TFT to the control electrode of the first TFT 112. The first control wires 114a and 114b correspond to the control wires in the present invention. In this embodiment, two first control lines 114a, 114b are provided, the first connection terminal 116a,其s through 116 b, the control signals CLK ₁ and CLK ₂ from an external control circuit (not shown) Supplied. In the following description, the unit circuit corresponding to the first selected row in the pixel array is defined as the first unit circuit, and the second unit circuit, the third unit circuit in the order of disposition from the first unit circuit. A unit circuit is used. Then, odd-numbered unit circuits such as the first and third are set as odd-numbered unit circuits, and even-numbered unit circuits such as the second and fourth are set as even-numbered unit circuits.

  In the odd unit circuit, the first control wiring 114a is electrically connected in common to the control electrode of the first TFT 112 in the first stage, and the first control wiring 114b is connected to the control electrode of the second TFT 112 in the second stage. Commonly connected electrically. On the other hand, in the even unit block adjacent to the odd unit circuit, the first control wiring 114b is electrically connected in common to the control electrode of the first TFT 112 in the first stage, and the first TFT 112 in the second stage is connected. The first control wiring 114a is electrically connected in common to the control electrode. That is, the first control wiring 114 has the following connection when there is a predetermined unit circuit (for example, the third unit circuit) and another unit circuit (for example, the fourth unit circuit) adjacent thereto. It becomes a relationship. The control terminal of the TFT located on the most other unit circuit side among the plurality of TFTs included in the predetermined unit circuit, and the TFT located on the most predetermined unit circuit side among the plurality of TFTs included in the other unit circuit Are connected in common to the same first control wiring. The first control wiring 114a is electrically connected to the first connection terminal 116a, and the first control wiring 114b is electrically connected to the first connection terminal 116b. The demultiplexer 111 according to the present embodiment is configured to be capable of performing a one-to-two demultiplex operation. However, the present invention is not limited to this, and a one-to-two or more demultiplex operation is possible. Any configuration is possible. An integrated circuit is preferably used for each external circuit connected to each connection terminal. When using an integrated circuit, each circuit may be individually provided in the integrated circuit, and some or all of each circuit may be provided in the same integrated circuit.

Next, the operation of the demultiplexer 111 of this embodiment will be described with reference to FIGS. Here, in FIG. 1B, control signals supplied to the connection terminals 110 corresponding to the drive lines 104 in the first row and the second row are sent to the drive lines 104 in the VGPAD ₁ , the third row, and the fourth row. the control signal supplied to the connection terminal 110 corresponding to VGPAD _2. In the same manner, control signals supplied to the connection terminals 110 corresponding to the drive lines 104 in the n-3th row and the n-2th row are represented as VGPAD _{(n / 2) -1} , n-1 row, and n. A control signal supplied to the connection terminal 110 corresponding to the drive line 104 in the row is VGPAD _{n / 2} . The control signal supplied to the first connection terminal 116a is CLK ₁ and the control signal supplied to the control terminal 116b is CLK ₂ . The voltages of the drive lines 104 in the _{1st to nth} rows are _denoted by VG1 to VGn, respectively.

First, CLK ₁ becomes a conduction voltage (hereinafter referred to as Hi) of the first TFT 112. This Hi voltage is larger than a value obtained by adding a threshold voltage of the first TFT 112 to a Vcom voltage described later. On the other hand, CLK ₂ is a non-conducting voltage (hereinafter referred to as Lo) of the first TFT 112. During this time, a voltage is applied and VGPAD ₁ becomes a voltage higher than the conduction voltage of the switch element 103 (hereinafter referred to as Vcom), and VGPAD _{2 to} VGPAD _{n / 2} are non-conductive voltages of the switch element 103 (hereinafter referred to as Voff). It becomes. As a result, the voltage VG ₁ of the drive line 104 in the first row, which is a predetermined drive line, becomes the conduction voltage of the switch element 103 (hereinafter referred to as Von), and the voltage of the drive line 104, which is a drive line different from the predetermined drive line. VG _{2 to} VG _n become Voff.

Next, VGPAD _{1 to} VGPAD _{n / 2} become Voff while CLK ₁ remains Hi and CLK ₂ remains Lo. Thereby, all of VG ₁ to VG _n become Voff.

Next, CLK ₁ becomes Lo, CLK ₂ becomes Hi, and then VGPAD ₁ becomes Vcom again. Further, VGPAD _{2 to} VGPAD _{2n / 2} are Voff. Thereby, VG ₂ becomes Von, and VG ₁ and VG ₃ to VG _n become Voff. This is the demultiplexer operation of the first unit block of the demultiplexer 111.

Next, VGPAD _{1 to} VGPAD _{n / 2} become Voff while CLK ₁ remains Lo and CLK ₂ remains Hi. Thereby, all of VG ₁ to VG _n become Voff.

Next, CLK ₁ is Lo, while CLK ₂ is Hi, VGPAD ₂ is Vcom _{becomes, VGPAD 1, VGPAD 3 ~VGPAD n} / 2 becomes Voff. Thereby, VG ₃ becomes Von, and VG ₁ to VG ₂ and VG ₄ to VG _n become Voff.

Next, VGPAD _{1 to} VGPAD _{n / 2} become Voff while CLK ₁ remains Lo and CLK ₂ remains Hi. Thereby, all of VG ₁ to VG _n become Voff.

Further, CLK ₁ switches to Hi and CLK ₂ switches to Lo, and then VGPAD ₂ becomes Vcom again. VGPAD _1, VGPAD _{3 to} VGPAD _{n + 2} are Voff. As a result, VG ₄ becomes Von, and VG _{1 to} VG _{3 and} VG _{5 to} VG _n become Voff. This is the demultiplexer operation of the second unit block of the demultiplexer 111. Thereafter, the same processing is sequentially performed until the multiplexer operation of the n / 2 unit block of the demultiplexer 111 is performed, and the row scanning of the switch element 103 is sequentially performed.

  As described above, in the present invention, by using the demultiplexer 111, the number of connection terminals 110 connected to the external drive circuit can be suppressed to a fraction of the unit circuit at the maximum. However, the total number of connection terminals is increased by the number of first connection terminals 116a and 116b for components included in the unit block.

Here, the frequency f of the control signals CLK ₁ and CLK ₂ means the number of times of oscillation in one second, that is, the number of times of repeating the maximum value (Hi) and the minimum value (Lo) of the voltage in one second, and its reciprocal number. 1 / f means one cycle of the control signal.

Power consumption P of the first control line 114a or 114b has a capacitance value C that is loaded on the first control line 114a or 114b, the control signal CLK ₁ or CLK and _second frequency f, Hi and differential voltage Lo ( Hi-Lo) squared. That is, P = f * C * (Hi-Lo) < ² >. Therefore, if the frequency f of the control signal CLK ₁ or CLK ₂ is halved, the power consumption of the first control wirings 114a and 114b is halved. In the prior art, every time Von is supplied to one drive line 104 and the pixel is driven, it is necessary to supply one cycle of the control signal CLK ₁ or CLK ₂ to the control wiring. , each time Von is sequentially supplied to the two driving lines 104, may be applied to control signals CLK ₁ or CLK ₂ for one cycle to the first control line 114a or 114b. That is, in the present embodiment, one cycle of the control signal CLK ₁ or CLK ₂ is twice that of the conventional technique and the frequency thereof is ½ that of the conventional technique. The power consumption of the wiring is halved compared to the prior art. This is particularly true when the number of drive lines 104 is large due to the increase in area and definition of the pixel array, or the period (scanning frequency) F for sequentially supplying Von to the drive lines 104 for high-speed operation is high. In some cases it is advantageous. As the number of drive lines 104 increases, the number of first TFTs 112 connected to the first control lines 114a and 114b increases, the capacitance value C of the first control lines 114a or 114b increases, and consumption by the first control lines 114a or 114b. This is to increase power. Further, when the scanning frequency F for high-speed operation increases, it is necessary to increase the gate capacitance of the first TFT 112 in order to cope with high-speed operation, the capacitance value C of the first control wiring 114a or 114b increases, and the first control wiring This is to increase the power consumption at 114a or 114b. In particular, when the power consumption in the first control wirings 114a and 114b (power consumption in the demultiplexer 111) is larger than the power consumption in the drive line 104 (power consumption in the pixel array), the effect of the present invention is remarkable. It will be something.

  Next, a cross-sectional structure of the pixel 101 of this embodiment will be described with reference to FIG. In the pixel 101 of this embodiment, the conversion element 102 and the switch element 103 are provided in a one-to-one correspondence. The switch element 103 includes a first semiconductor layer 201, a first impurity semiconductor layer 202, a first insulating layer 203, a first conductive layer 204, and a second insulating layer provided on a supporting substrate 100 having an insulating surface such as a glass substrate. A layer 205 and a second conductive layer 206 are provided. The first semiconductor layer 201 is a TFT channel region, the first impurity semiconductor layer 202 is a source or drain region, the first insulating layer 203 is a gate insulating film, the second conductive layer 204 is a gate electrode, and the third conductive layer 206 is a source or drain. Each functions as a drain electrode. Here, the gate electrode corresponds to the control electrode in the description of FIG. 1, and the source or drain electrode corresponds to the main electrode. In FIG. 2, a staggered TFT using polycrystalline silicon is used for the first semiconductor layer 201. When the staggered TFT using the same polycrystalline silicon is used for the first TFT 112, the manufacturing process becomes simple. Then, the conversion element 102 is disposed above the third insulating layer 207 that covers the switch element 103. The photoelectric conversion element included in the conversion element 102 includes a fourth conductive layer 209, a second impurity semiconductor layer 210, a second semiconductor layer 211, a third impurity semiconductor layer 212, a fifth conductive layer 213, and a sixth conductive layer 214. doing. The fourth conductive layer 209 is electrically coupled to the third conductive layer that is the first main electrode of the switch element 103 via the third conductive layer 208, and functions as a first electrode. The second impurity semiconductor layer 210 is implanted with n-type impurities, and the third impurity semiconductor layer 212 is implanted with p-type impurities. The second semiconductor layer 211 functions as a photoelectric conversion layer of the photoelectric conversion element, the fifth conductive layer 213 functions as the bias line 106, and the sixth conductive layer 214 functions as the second electrode. A scintillator 216 is provided above the fourth insulating layer that covers the plurality of photoelectric conversion elements and functions as a planarization layer. The conversion element 102 and the switch element 103 can be suitably formed by using a known vapor deposition (vapor deposition) method, etching technique, and photolithography technique. In this embodiment, the PIN type photodiode using the second impurity semiconductor layer 210 is described as a photoelectric conversion element. However, the present invention is not limited to this, and the second impurity semiconductor layer 210 is used instead. An MIS photosensor using an insulating layer may be used.

Next, the device configuration of the detection device of the present invention will be described with reference to FIG. The detection device 200 includes a support substrate 100 having at least a pixel array, a demultiplexer 111, and a connection terminal 110. The detection device 200 includes a detection unit 223 having a support substrate 100, a drive circuit 221 that drives the pixel array, and a readout circuit 222 that outputs an electrical signal from the pixel array as image data. The drive circuit 221 is electrically connected to the connection terminal 110 and outputs Vcom and Voff. That is, the driving circuit 221 is for driving the pixel by controlling the selected state and the non-selected state of the pixel. The reading circuit 222 is electrically connected to the connection terminal 119. The detection apparatus 200 further includes a signal processing unit 224 that processes and outputs the image data from the detection unit 223, a control circuit 225 that controls the operation of the detection unit 223 by supplying a control signal to each component, A power supply circuit 226 for supplying a bias to each component is included. The signal processing unit 224 receives a control signal from a control computer (not shown) and provides it to the control circuit 225. Further, the signal processing unit 224 receives the potential information of the signal line 105 from the readout circuit 222 during the radiation irradiation period, and transmits it to a control computer (not shown). The power supply circuit 226 includes a regulator that receives a voltage from an external power supply (not shown) or a built-in battery and supplies a voltage necessary for the pixel array, the drive circuit 221, and the readout circuit 222. The power supply circuit 226 is electrically connected to the connection terminal 109. The control circuit 225 is electrically connected to the first connection terminals 116a and 116b, and outputs control signals CLK ₁ and CLK ₂ . Note that the driving circuit 221, the reading circuit 222, the signal processing unit 224, the control circuit 225, and the power supply circuit 226 are each shown as one block, but each of them is constituted by one integrated circuit. It does not mean that it has been. Each may be constituted by a plurality of integrated circuits, or all of them may be provided in one integrated circuit. Moreover, the above description can be appropriately applied to other embodiments of the present invention.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. 3 (a) and 3 (b). In the following, only differences from the first embodiment will be described in detail, and the same components as those in the first embodiment will be assigned the same reference numerals and detailed description thereof will be omitted.

In the first embodiment shown in FIG. 1A, two drive lines 104 are provided in a one-to-one correspondence between one connection terminal 110 and two corresponding drive lines 104. A demultiplexer 111 including a unit circuit having two first TFTs 112 is used. On the other hand, in the present embodiment, as shown in FIG. 3, a unit block of the first demultiplexer circuit 111a having two first TFTs 112a is provided between one connection terminal 110 and four corresponding drive lines 104. It has been. The unit block of the second demultiplexer circuit 111b having four second transistors (second thin film transistors) (second TFTs) 112b between the unit block of the first demultiplexer circuit 111a and the corresponding four drive lines 104. Is provided. A unit block of the first demultiplexer circuit 111 a connected to one connection terminal 110 and a unit block of the second demultiplexer circuit 111 b connected to the four drive lines 104 are connected in series via the connection node 120. The As a result, the unit block of the first demultiplexer circuit 111a and the unit block of the second demultiplexer circuit 111b constitute a unit circuit of the demultiplexer. That is, the demultiplexer of this embodiment has a configuration in which two 1-to-2 demultiplexer circuits are connected in series. In the present embodiment, in the unit block of the first demultiplexer circuit 111a, an element related to the connection node 120 connected to the drive line 104 corresponding to the first row of each unit block is referred to as a first stage. Similarly, an element related to the connection node 120 connected to the drive line 104 corresponding to the second row is referred to as a second stage. In the unit block of the second demultiplexer circuit 111b, the element related to the drive line 104 corresponding to the first row of each unit block is set to 2 and the element related to the drive line 104 corresponding to the first row and the second row is set to 2. The steps are referred to as the third step and the fourth step. The first TFT 112a at the first stage is connected to the second TFT 112b at the first stage and the second TFT 112b at the third stage, and the first TFT 112a at the second stage is connected to the second TFT 112b at the second stage and the second TFT 112b at the fourth stage. Further, in addition to the first control wirings 114a and 114b, second control wirings 115a and 115b for supplying a conduction voltage and a non-conduction voltage of the TFT to the control electrode of the second TFT 112b are provided. In this embodiment, two second control lines 115a, 115b are provided, the second connection terminal 117a,其people via 117b, the control signal _{CLK 1b} and _{CLK 2b} from an external control circuit (not shown) Supplied. On the other hand, the control signals CLK _1a and CLK _2a are supplied to the first control wirings 114a and 114b from the external control circuit (not shown) via the first connection terminals 116a and 116b, respectively. In the following, the unit block corresponding to the first selected row in the pixel array is set as the first unit block, the second unit block, the third unit block in order of arrangement from the first unit block. A unit block. Then, odd-numbered unit blocks such as the first and third are assumed to be odd-numbered unit blocks, and even-numbered unit blocks such as second and fourth are assumed to be even-numbered unit blocks.

  In odd-numbered unit blocks of the first demultiplexer circuit 111a, as in the demultiplexer 111 of the first embodiment, the first control wiring 114a is electrically connected in common to the control electrode of the first TFT 112a in the first stage. Is done. The first control wiring 114b is electrically connected in common to the control electrode of the first TFT 112b in the second stage. On the other hand, in the adjacent even number of unit blocks, the first control wiring 114b is electrically connected in common to the control electrode of the first-stage first TFT 112a, and the first control wiring is connected to the control electrode of the second-stage first TFT 112a. 114a are commonly electrically connected. That is, in the first demultiplexer circuit 111a, when there is a predetermined unit block and another unit block adjacent thereto, the following connection relationship is established. The control terminal of the TFT located on the most other unit block side among the plurality of TFTs included in the predetermined unit block, and the TFT located on the most predetermined unit block side among the plurality of TFTs included in the other unit block Are connected to the same control wiring in common.

  Next, in the odd unit blocks of the second demultiplexer circuit 111b, the second control wiring 115a is electrically connected in common to the control electrodes of the first TFT and the second TFT 112b in the second stage. Further, the second control wiring 115b is electrically connected in common to the control electrodes of the first TFT 112b in the third and fourth stages. On the other hand, in the adjacent even number of unit blocks, the second control wiring 115b is electrically connected in common to the control electrodes of the first TFT 112b in the first and second stages, and the first TFT 112b in the third and fourth stages. The second control wiring 115a is electrically connected in common to the control electrodes. That is, also in the second demultiplexer circuit 111b, when there is a first unit block and another unit block adjacent to the first unit block, the following connection relationship is obtained. The control terminal of the TFT located on the most other unit block side among the plurality of TFTs included in the predetermined unit block, and the TFT located on the most predetermined unit block side among the plurality of TFTs included in the other unit circuit Are connected to the same control wiring in common. Further, two TFTs are connected to the same control wiring in one unit block.

Next, the operation of the demultiplexer according to this embodiment will be described with reference to FIGS. 3 and 4A. Here, in FIG. 4A, control signals supplied to the connection terminals 110 corresponding to the drive lines 104 in the first to fourth rows are sent to VGPAD ₁ , and the drive lines 104 in the fifth to eighth rows. the control signal supplied to the connection terminal 110 corresponding to VGPAD _2. The control signal supplied to the first connection terminal 116a is CLK _1a , the control signal supplied to the control terminal 116b is CLK _2a , the control signal supplied to 117a is CLK _1b , and the control signal is supplied to the control terminal 117b. Let the signal be CLK _2b . The voltages of the drive lines 104 in the first to eighth rows are denoted by VG _1b to VG _8b , respectively. In the present embodiment, the first demultiplexer 111a, each time Von is sequentially supplied to the two driving lines 104, may be applied to control signals _{CLK 1a} and _{CLK 2a} of one period. On the other hand, the second demultiplexer 111b, each time Von is sequentially supplied to the four driving lines 104, may be applied to control signal _{CLK 1b} and _{CLK 2b} of one period.

First, CLK _{1a and} CLK _1b become Hi, and CLK _{2a and} CLK _2b become Lo. During this time, a voltage is applied and VGPAD ₁ becomes Vcom, and VGPAD ₂ is in the Voff state. As a result, the voltage VG _1b of the drive line 104 in the first row which is a predetermined drive line becomes the conduction voltage Von of the switch element 103, and the voltages VG _{2b to} VG of the drive line 104 which are drive lines different from the predetermined drive line. _8b becomes Voff.

Next, VGPAD ₁ becomes Voff, CLK _1b remains Hi, CLK _2b remains Lo, CLK _1a switches to Lo, and CLK _2a switches to Hi. During this time, VGPAD ₁ becomes Vcom again. VGPAD ₂ is in the Voff state. As a result, the voltage VG _2b of the drive line 104 in the second row which is a predetermined drive line becomes the conduction voltage Von of the switch element 103, and the voltages VG _1b and VG of the drive line 104 which are drive lines different from the predetermined drive line. _{3b to} VG _8b become Voff.

Next, VGPAD ₁ becomes Voff, CLK _1b switches to Lo, CLK _2b switches to Hi, CLK _1a remains Lo, and CLK _2a remains Hi. During this time, VGPAD ₁ becomes Vcom again. VGPAD ₂ is in the Voff state. As a result, the voltage VG _3b of the drive line 104 in the third row which is a predetermined drive line becomes the conduction voltage Von of the switch element 103, and the voltages VG _{1b to} VG of the drive line 104 which is a drive line different from the predetermined drive line. _2b , VG _{4b to} VG _8b become Voff. Thereafter, the same processing is performed in the same manner, and the scanning of the switching elements 103 in units of rows is performed.

  As described above, in the present invention, by using the demultiplexer 111, the number of connection terminals 110 connected to the external drive circuit can be suppressed to a maximum of 1 / stage of the unit block. However, the second connection terminals 117a and 117b are provided as the whole connection terminals.

FIG. 4B shows a timing chart when performing 2-pixel addition. As shown in FIG. 4B, the operation of adding two pixels can be performed simply by fixing CLK _{1a and} CLK _2a to Hi. Since CLK _{1a and} CLK _2a are fixed to Hi, the power consumption in the demultiplexer is further reduced.

  In the present embodiment, in the first demultiplexer circuit 111a, the number of first TFTs 112a is half that of the first TFTs 112 in the first embodiment. On the other hand, the quantity increases by the amount of the second TFT 112b compared to the first embodiment, but the control signal supplied to the second demultiplexer circuit 111b is twice as long as the control signal of the first embodiment. One cycle may be sufficient. Therefore, the power consumption of the demultiplexer of this embodiment can be suppressed as in the first embodiment.

In this embodiment, an example of a demultiplexer having a configuration in which two 1-to-2 demultiplexer circuits are connected in series has been described. However, m (m is a natural number greater than 1) demultiplexers connected in series It is shown as follows. Here, the demultiplexer circuit closest to the connection terminal 110 is electrically referred to as the first demultiplexer circuit, and the demultiplexer circuit closest to the drive wiring 104 is electrically referred to as the mth demultiplexer circuit. The m-1 demultiplexer circuit includes 2 ^{m-1 m-1} TFTs, and the m demultiplexer circuit includes 2 ^m mTFTs. The m-th TFTs at the first stage and the third stage of the m-th demultiplexer circuit are connected to the m-th TFT at the first stage of the m-1 demultiplexer circuit. The second and fourth mth TFTs of the m-th demultiplexer circuit are connected to the second m-1 TFT of the m-1 demultiplexer circuit. Such a connection is made up to the ^2m-th stage of the ^m -th demultiplexer circuit. In one unit block of the m-th demultiplexer circuit, the control terminals of the ^m- th TFTs from the first stage to the 2 ^m-1 stage are commonly connected to one control wiring, and the 2 ^m-1 +1 stage. The control terminals of the ^m -th TFTs up to the 2m-th stage are commonly connected to another control wiring. Each time Von is sequentially supplied to the 2 ^m−1 drive lines 104, a control signal having one cycle is supplied to the m-th demultiplexer circuit.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIG. 5A, FIG. 5B, FIG. 6, FIG. 7A, and FIG. Here, FIG. 5A is a block diagram for explaining the detection unit 223 in the present embodiment, and FIG. 5B is an equivalent circuit diagram for explaining the detection unit 223 in the present embodiment. FIG. 6 is an enlarged block diagram of a part of the detection unit 223 in the present embodiment. FIG. 7A and FIG. 7B are timing charts for explaining the operation of the present embodiment. In the following, only differences from the first embodiment will be described in detail, and the same components as those in the first embodiment will be assigned the same reference numerals and detailed description thereof will be omitted.

  As shown in FIG. 5A, in the present embodiment, the driving circuit 221 includes a driving printed circuit board 227 and a plurality of (for example, ten) driving integrated circuits 228. That is, a plurality of demultiplexers 111 are provided in one-to-one correspondence with the driving integrated circuit 228. In this embodiment, ten demultiplexers 111 are provided. Here, the driving printed circuit board 227 supplies signals and power to each driving integrated circuit 228, and each driving integrated circuit 228 supplies a signal group such as a control signal and various voltages to the corresponding demultiplexer 111. 229 is supplied.

  As shown in FIG. 5B, in the present embodiment, a third transistor (third thin film transistor) for supplying only Voff (second voltage) to the drive line 104 to each unit circuit of the demultiplexer 111. A (third TFT) 113 is provided for each drive line 104. The third TFT 113 is disposed between the power line 126 and the drive line 104 connected to the third connection terminal 121 to which only Voff is supplied. The control terminal of the third TFT 113 is connected to a control wiring different from the control wiring connected to the control terminal of the first TFT connected to the same drive line 104 among the first control wirings 114a and 114b. Further, a fourth transistor (fourth thin film transistor) (fourth TFT) that supplies the control signal VGPAD supplied to the connection terminal 110 to the two drive lines 104 corresponding to one connection terminal 110 without passing through the first TFT 112. ) 130 is provided on the support substrate 100. The fourth TFT 130 is disposed between the two drive lines 104 corresponding to one connection terminal 110 and the connection terminal 110 corresponding to each unit circuit of the demultiplexer 111. The fourth TFT 130 is provided in parallel with the first TFT 112. The control terminal of each fourth TFT 130 is electrically connected to a fourth connection terminal 131 to which a mode selection signal ADD is supplied. The mode selection signal ADD is a signal for selecting either a first mode in which reading is performed sequentially row by row or a second mode (pixel addition mode) in which reading is performed sequentially row by row by a constant voltage of Hi or Lo. . In this embodiment, as an example, the demultiplexer 111 is provided corresponding to the driving lines 104 for 256 rows corresponding to one driving circuit 228, and 128 connection terminals 110 are provided. The first control wirings 114 a and 114 b are divided corresponding to each driving integrated circuit 228.

As shown in FIG. 6, the driving integrated circuit 228 is provided on the flexible wiring board 160 and bonded to the wiring of the flexible wiring board 160. That is, the driving circuit 221 includes a plurality of flexible wiring boards 160 having the driving integrated circuit 228. The wiring bonded to the driving integrated circuit 228 is connected to each connection terminal 110 by a TAB (Tape Automated Bonding) mounting method, and transmits each control signal VGPAD. The wiring 161a is positioned outside the wiring is bonded to the driving integrated circuit 228 of the wiring of the flexible wiring board 160, b is connected first connection terminal 116a, the b, the control signals CLK ₁ and CLK ₂ is transmitted. That is, the divided first control wirings 114 a and 114 b are electrically connected to the respective wirings 161 a and 161 b for each flexible wiring board 160. Then, the wiring 162 positioned between the wiring bonded to the driving integrated circuit 228 and the wirings 161a and 161b is connected to the third connection terminal 121 or the fourth connection terminal 131, and the non-conduction voltage Voff or mode is selected. A selection signal ADD is transmitted. Since the wiring 162 transmits a constant voltage or a constant voltage signal, the wiring 162 functions as a shield that suppresses the mixing of noise into the control signal VGPAD due to the potential fluctuation of the control signal transmitted through the wirings 161a and 161b. A plurality of (for example, ten) flexible wiring boards 116 having such driving integrated circuits 228 are provided.

  Next, the operation of the demultiplexer 111 of this embodiment will be described with reference to FIGS. Here, FIG. 7A shows the operation in the first mode, and FIG. 7B shows the operation in the second mode.

As shown in FIG. 7A, the operation of the demultiplexer 111 in the first mode is the same as the operation of the first embodiment shown in FIG. 1B except for the following points. The first is that the mode selection signal ADD is fixed to Lo. As a result, the fourth TFT 130 becomes non-conductive. The second point is that the drive line 104 is fixed to Voff when each third TFT 113 becomes conductive. Thereby, even when the first TFT 112 is non-conductive, the potential of the drive line 104 is fixed to Voff. Further, since it becomes possible to supply the control signals CLK ₁ and CLK ₂ only to the target demultiplexer 111 without supplying the control signals CLK ₁ and CLK ₂ to all the demultiplexers 111 at the same time, the power consumption is further increased. Can be reduced.

Next, as shown in FIG. 7B, the operation of the demultiplexer 111 in the second mode is characterized by the following points. The first is that the mode selection signal ADD is fixed to Hi and the control signals CLK ₁ and CLK ₂ are fixed to Lo. The second point is that each control signal VGPAD is sequentially supplied to each connection terminal 110. Accordingly, each control signal VGPAD is sequentially supplied to each of the two drive lines 104 without passing through the first TFT 112, and pixel addition can be performed.

(Fourth embodiment)
Next, an application example to a radiation detection system using the radiation detection apparatus of the present invention will be described with reference to FIG.

  X-rays 6060 generated by an X-ray tube 6050 as a radiation source pass through the chest 6062 of the patient or subject 6061 and enter the detection device 6040 of the present invention. This incident X-ray includes information inside the body of the patient 6061. The scintillator 216 emits light in response to the incidence of X-rays, and this is photoelectrically converted by a photoelectric conversion element to obtain electrical information. This information can be digitally converted and image-processed by an image processor 6070 as a signal processing means, and can be observed on a display 6080 as a display means in a control room.

  Further, this information can be transferred to a remote place by transmission processing means such as a telephone line 6090, and can be displayed on a display 6081 serving as a display means such as a doctor room in another place or stored in a recording means such as an optical disk. It is also possible for a doctor to make a diagnosis. Moreover, it can also record on the film 6110 used as a recording medium by the film processor 6100 used as a recording means.

DESCRIPTION OF SYMBOLS 100 Support substrate 101 Pixel 102 Conversion element 103 Switch element 104 Drive line 105 Signal line 106 Bias line 107 Common line 108 Common bias line 109-110 Connection terminal 111 Demultiplexer 112 1st TFT
114a, 114b first control wiring 116a, 116b first connection terminal

Claims (9)

A plurality of pixels are arranged in a matrix, a plurality of drive lines commonly connected to a plurality of pixels in the row direction are arranged along the column direction, and a driving circuit for driving the plurality of pixels and a plurality of Connection terminals for electrically connecting the drive lines are provided in a number smaller than the number of the plurality of drive lines, and a demultiplexer having a plurality of unit circuits is provided with the plurality of connection terminals and the plurality of connection lines. A drive line is electrically connected, and each of the plurality of unit circuits includes a predetermined connection terminal of the plurality of connection terminals and two or more predetermined drive lines of the plurality of drive lines. a plurality of transistors for electrically connecting, a in matrix substrate control electrode of the plurality of transistors is electrically connected to a plurality of control lines for supplying the conducting voltage and a non-conducting voltage of said transistor And
The plurality of unit circuits include a first unit circuit and a second unit circuit adjacent to the first unit circuit;
A control terminal of the second transistor located closest the second unit circuit side of the first transistor and the second transistor included in the plurality of the transistors included in the first unit circuit, the first the control terminal of the third transistor located in the most the first unit circuit side among the plurality of transistors you located farther from said first transistor than and the second transistor included in the second unit circuit Are electrically connected to the same control wiring of the plurality of control wirings, and the control terminal of the first transistor is another control wiring different from the same control wiring of the plurality of control wirings. A matrix substrate characterized by being electrically connected to the substrate. The demultiplexer is connected to a first demultiplexer circuit including the transistors each connected to a predetermined connection terminal among the plurality of connection terminals, the first demultiplexer circuit, and the drive line. A second demultiplexer circuit,
The matrix substrate according to claim 1, wherein the second demultiplexer circuit includes a second transistor connected in series with the transistor.   The unit circuit further includes a plurality of third transistors that are provided in one-to-one correspondence with the drive lines and supply the drive lines with a second voltage that deselects the pixels. The matrix substrate according to claim 1 or 2, characterized in that The demultiplexer further includes a plurality of fourth transistors provided in parallel with the plurality of transistors,
The common connection to the control electrodes of the plurality of fourth transistors is electrically connected to a connection terminal to which conduction voltages of the plurality of fourth transistors are supplied in a pixel addition mode. 4. The matrix substrate according to any one of 3 above. The pixel includes a switch element that outputs an electrical signal corresponding to a charge generated by a conversion element that converts radiation or light into a charge, and the first voltage for selecting the pixel is a conduction voltage of the switch element. 2. The matrix substrate according to claim 1, wherein the second voltage for deselecting the pixel is a non -conducting voltage of the switch element.   The matrix substrate according to claim 5, wherein the conversion element includes a scintillator that converts radiation into light and a photoelectric conversion element that converts the light into electric charge. A matrix substrate according to any one of claims 1 to 6;
The driving circuit;
A control circuit for supplying a conduction voltage and a non-conduction voltage of the transistor to the control wiring;
A detection device comprising:
The detection circuit according to claim 1, wherein the control circuit supplies the control wiring with a conduction voltage and a non-conduction voltage of the transistor at a frequency half of a frequency driven by the pixel. The driving circuit has a plurality of flexible wiring boards having driving integrated circuits,
A plurality of the demultiplexers are provided in one-to-one correspondence with the driving integrated circuit,
The control wiring is divided into a plurality of one-to-one correspondence with the driving integrated circuit,
The detection device according to claim 7, wherein each of the divided control wirings is electrically connected to a wiring provided on a corresponding flexible wiring board among the plurality of flexible wiring boards. The detection device according to claim 7 or 8,
Signal processing means for processing a signal from the detection device;
Recording means for recording a signal from the signal processing means;
Display means for displaying a signal from the signal processing means;
And a transmission processing means for transmitting a signal from the signal processing means.

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