JP5300444B2 - Integrated circuit device, imaging device and imaging system using the same - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device including a signal processing circuit for performing signal processing of an imaging device, an imaging device including the semiconductor integrated circuit device, a radiation imaging device using the same, and a radiation imaging system. In the present specification, the radiation includes electromagnetic waves, X-rays, α rays, β rays, γ rays, and the like.

  In an imaging apparatus having a detector including a plurality of pixels in a matrix, a detector using a semiconductor integrated circuit device in which a plurality of signal processing circuits for processing signals output from the detector in columns is arranged in an array The image signal from is processed. Here, a typical example of the signal processing circuit includes an amplifier circuit that amplifies a signal from a pixel. Patent Document 1 discloses an imaging device in which such an integrated circuit device is provided on a plurality of semiconductor substrates separately from a detector and is mounted on the detector, and a radiation imaging device using the imaging device.

  In such an imaging apparatus, a signal processing circuit that operates with low current consumption is required in order to reduce power consumption of the entire apparatus. In addition, in an imaging apparatus, an increase in the dynamic range of the entire apparatus is required, and therefore, a signal processing circuit with low noise characteristics is required. In particular, in an imaging apparatus used for a medical radiation imaging apparatus, it is necessary to process a very small signal in order to reduce the radiation exposure to the human body, and a signal processing circuit having a lower noise characteristic is required. It has been demanded. In addition, an imaging apparatus used in a radiation imaging apparatus is required to be reduced in price for the spread. Therefore, it is also required to increase the number of signal processing circuits integrated in one semiconductor integrated circuit device and reduce the number of semiconductor integrated circuit devices to be used. In addition, even if the number of signal processing circuits integrated in the semiconductor integrated circuit device is increased, it is also required to prevent the chip area of the semiconductor chip constituting the semiconductor integrated circuit device from being significantly increased. That is, a semiconductor integrated circuit device including a signal processing circuit used in an imaging device is required to preferably achieve low noise, low power consumption, and a small area.

In order to achieve the above-described requirements, a bias circuit that supplies an operational bias for the amplification circuit included in the signal processing circuit to perform an amplification operation plays an important role. Patent Document 2 discloses a bias circuit that supplies a bias current for driving an amplifier circuit arranged in a linear row in one integrated circuit device. In Patent Document 2, the input-side transistors in the current mirror circuit constituting the bias circuit are distributed and arranged in each amplifier circuit. Thus, a bias circuit including a bias current setting line, a power supply line, and an input side transistor is arranged in common with respect to the amplifier circuits of all signal processing circuits.
JP 2003-57350 A JP 2000-310981 A

  However, in Patent Document 2, when the number of signal processing circuits provided in one semiconductor integrated circuit device increases, the wiring current resistance of the bias current setting line and the power supply line and the potential gradient generated by the current flowing through them increase. Thereby, a gradient occurs between the signal processing circuits in the operation bias supplied to the amplification circuit of each signal processing circuit, and a gradient occurs at the operating point of each amplification circuit. Therefore, a gradient occurs in the amplification characteristics of each amplifier circuit in the semiconductor integrated circuit, and an output gradient in the row direction occurs in the image signal output from each amplifier circuit. Since this output gradient is conspicuous in the image signal, the image quality of the image signal output from the imaging device is significantly degraded.

  The present invention provides a semiconductor integrated circuit device for an imaging apparatus that solves the above-described problems and suppresses reduction in image quality while considering low power consumption, low noise characteristics, and high integration, and an imaging apparatus using the same. It is intended to do.

The integrated circuit device of the present invention includes an amplifier circuit having a bias input terminal, an input terminal electrically connected to a bias source, and an output terminal electrically connected to the bias input terminal. A plurality of signal processing circuits including a bias circuit for supplying an operation bias to the plurality of signal processing circuits, wherein the plurality of signal processing circuits are divided into a plurality of groups, wherein the integrated circuit device is divided into the groups. And the input terminals of the plurality of bias circuits included in one group of the plurality of groups are connected in common by one of the plurality of connection wirings. The amplifier circuit has a grounded gate circuit, and the bias input terminal includes a gate of a transistor constituting the grounded gate circuit. The integrated circuit device of the present invention includes an amplifier circuit having a bias input terminal, an input terminal electrically connected to a bias source, and an output terminal electrically connected to the bias input terminal. An integrated circuit device including a plurality of signal processing circuits having a bias circuit for supplying an operational bias to the amplifier circuit, wherein the plurality of signal processing circuits are divided into a plurality of groups, A plurality of connection wirings are provided, and the input terminals of the plurality of bias circuits included in one group among the plurality of groups are commonly connected by one of the plurality of connection wirings. The amplifier circuit includes a transistor that is a current source of the amplifier circuit and a transistor that constitutes a grounded gate circuit, and the bias circuit is a transistor that is a current source of the amplifier circuit. A first bias circuit having an output terminal electrically connected to the gate, and a second bias circuit having an output terminal electrically connected to the gate of the transistor constituting the gate ground circuit. . The integrated circuit device of the present invention further includes an amplifier circuit having a bias input terminal, an input terminal electrically connected to a bias source, and an output terminal electrically connected to the bias input terminal. An integrated circuit device including a plurality of signal processing circuits having a bias circuit for supplying an operational bias to the amplifier circuit, wherein the plurality of signal processing circuits are divided into a plurality of groups, A plurality of connection wirings are provided, and the input terminals of the plurality of bias circuits included in one group among the plurality of groups are commonly connected by one of the plurality of connection wirings. In the case where n signal processing circuits are included and x signal processing circuits are included in the one group, the number n / x of the plurality of groups is 10 or more and 13 or less, and x is 2 Is a natural number smaller than n And Ru about the number der of n.

The imaging apparatus of the present invention has a plurality of pixels including a conversion element for converting radiation or light into an electric signal, and a detection having a plurality of signal lines for transmitting the electric signals output from the pixels in parallel. And an integrated circuit device for inputting an electric signal transmitted in parallel, the integrated circuit device having a bias input terminal and amplifying the inputted electric signal And a bias circuit having an input terminal electrically connected to a bias source and an output terminal electrically connected to the bias input terminal and supplying an operational bias to the amplifier circuit. A plurality of circuits are provided corresponding to the plurality of signal lines, and the plurality of signal processing circuits are divided into a plurality of groups. Here, the integrated circuit device is provided divided for each group. Multiple connection wiring Wherein the plurality of being connected to a common said input terminals of the plurality of the bias circuit contained in one group is the one of the plurality of the connection wirings of the group, given one of said plurality of signal lines A signal processing circuit corresponding to the signal line and a signal processing circuit corresponding to a signal line not physically adjacent to the predetermined signal line are included in the one group, and the plurality of signal lines signal processing circuits corresponding to the predetermined signal line physically adjacent signal lines among the that contained in the different groups and the one group. In addition, the imaging apparatus of the present invention includes a plurality of pixels including conversion elements for converting radiation or light into electrical signals, and includes a plurality of signal lines for transmitting in parallel the electrical signals output from the pixels. A detector having a bias input terminal, an amplifier circuit for inputting the electric signal transmitted in parallel, and amplifying the input electric signal; and an input terminal electrically connected to the bias source; A bias circuit having an output terminal electrically connected to the bias input terminal and supplying an operational bias to the amplifier circuit, and a plurality of signal processing circuits corresponding to the plurality of signal lines, A plurality of signal processing circuits, and an integrated circuit device divided into a plurality of groups, wherein the integrated circuit device has a plurality of connection wirings divided for each group. , Out of the plurality of groups The input terminals of a plurality of the bias circuits included in one group are connected in common by one of the plurality of connection wirings, and the integrated circuit device includes n signal processing circuits. In the case where x signal processing circuits are included in the one group, the number n / x of the plurality of groups is 10 or more and 13 or less, x is a natural number that is 2 or more and smaller than n, and about n Is a number.

  According to the present invention, it is possible to provide a semiconductor integrated circuit device for an image pickup apparatus that suppresses a reduction in image quality while considering low power consumption, low noise characteristics, and high integration, and an image pickup apparatus using the same. It was.

  Next, embodiments for carrying out the invention will be described in detail.

(First embodiment)
First, the overall configuration of the imaging apparatus of the present invention will be described with reference to FIG. FIG. 2 is a schematic equivalent circuit diagram of the imaging apparatus according to the first embodiment of the present invention.

  The detector 201 and the drive circuit 203 are connected via m (m is a positive integer) drive lines Vg1 to Vgm. The detector 201 and the semiconductor integrated circuit device 204 are connected via n (m is a positive integer) signal lines Sig1 to Sign.

  The detector 201 includes a plurality of pixels 202 each including two conversion elements S11 to Smn including photoelectric conversion elements such as PIN type photodiodes and switching elements T11 to Tmn each including a thin film transistor (TFT). Have. That is, in the detector 201, m × n pixels 202 are arranged in a matrix. The detector 201 is, for example, a flat panel type detector formed of amorphous silicon as a main material on a glass substrate. When used in a radiation imaging apparatus, the detector 201 further has a wavelength converter (not shown) such as a phosphor that converts the wavelength of the radiation into light that can be sensed by the photoelectric conversion element. In the present embodiment, the wavelength conversion body and the photoelectric conversion element constitute a conversion element for converting radiation into an electrical signal. In addition, a photoelectric conversion element is contained in a conversion element as what converts light into an electric signal, and a conversion element can be comprised only with a photoelectric conversion element. In that case, the conversion element converts light into an electrical signal. That is, it can be said that the conversion element in the present invention is for converting radiation or light into an electrical signal.

  A sensor bias voltage is applied from the power supply 111 via the bias line Vs to the common electrode side (in FIG. 2, the cathode side of the photodiode) in the conversion element of each pixel 202. The switch elements of the pixels 202 arranged in the row direction of the detector 201 have their gate electrodes (control electrodes) electrically connected to the drive lines Vg1 to Vgm in common, for example, in units of rows. Further, in the switch elements of the pixels 202 arranged in the column direction of the detector 201, the source electrode which is one of the main electrodes is electrically connected to the signal lines Sig1 to Sign in common for each column, for example. . The switch element has a drain electrode, which is the other main electrode, electrically connected to the conversion element for each pixel. The signal lines Sig1 to Sign transmit electric signals output from a plurality of pixels in parallel, and the electric signals transmitted in parallel are input in parallel to the semiconductor integrated circuit device.

  The semiconductor integrated circuit device 204 amplifies electric signals output in parallel from the respective pixels 202 via the signal lines Sig1 to Sign for each row, converts the signals in series, and outputs them as image data (digital data). The semiconductor integrated circuit device 204 signals the capacitors Cf1 to Cfn and the amplifiers A1 to An each having a switch provided between the inverting input terminal and the output terminal, and the sample and hold circuit unit including the switch and the capacitors CL1 to CLn. For each of the lines Sig1 to Sign. Further, it is configured to include an analog multiplexer 204a, a buffer amplifier circuit 204b, and an A / D converter 204d. In the amplifier circuits A1 to An, the signal line Sig is electrically connected to the inverting input terminal, and a reference power supply for supplying a reference voltage serving as a reference for the amplification operation is connected to the normal input terminal. .

  The analog signals serially converted by the amplifier circuits A1 to An, the analog multiplexer 204a, and the buffer amplifier circuit 204b are input to the A / D converter 204d via the analog data line 204c. The A / D converter 204d converts the input analog signal into a digital signal and outputs image data (digital data) via the digital output bus 204e.

  2 shows one semiconductor integrated circuit device 204 and a region of the detector 201 corresponding to the semiconductor integrated circuit device 204 for the sake of explanation and simplification, but the entire device will be described in FIG. 3 below. It has become a form.

  FIG. 3 is a plan view showing a schematic configuration of the imaging apparatus according to the first embodiment of the present invention shown in FIG. The detector 201 is provided on an insulating substrate 301 such as a glass substrate. The semiconductor integrated circuit device 204 is mounted on a TCP (Tape Carrier Package) 302, and one side of the TCP 302 has a detector 201 so that the signal line Sig and the semiconductor integrated circuit device 204 are electrically connected. Implemented in the surrounding area. The other side of the TCP 302 is mounted on a PCB (Printed Circuit Board) 303, and an image signal from the semiconductor integrated circuit device 204 is output to the outside through the PCB 303. As shown in FIG. 3, a plurality of semiconductor integrated circuit devices 204 are provided for the detector 201. When the detector 201 includes pixels of M rows and N columns, the semiconductor integrated circuit device 204 corresponds to pixels for n columns, and N / n devices as a whole are provided.

  Next, a semiconductor integrated circuit device used in the imaging device of the present invention will be described with reference to FIG. FIG. 1 is a schematic equivalent circuit diagram of a semiconductor integrated circuit device 204 used in the imaging apparatus according to the first embodiment of the present invention. In FIG. 1, the capacitors Cf1 to Cfn, the switches, the sample hold circuit unit, the analog multiplexer 204a, the buffer amplifier circuit 204b, and the A / D converter 204d shown in FIG. 2 are omitted for simplification of explanation and drawings. ing.

  In FIG. 1, as shown in FIG. 2, the semiconductor integrated circuit device 204 has amplifier circuits A1 to An for signal lines Sig1 to Sign. Corresponding to each of the amplifier circuits A1 to An, first bias circuits B1 to Bn for supplying an operation bias for causing the amplifier circuit to perform an amplification operation are provided. That is, in the integrated circuit device 204, the signal processing circuit E1 including the amplifier circuit A1 and the first bias circuit B1 corresponding to the signal line Sig1 in the first column is amplified corresponding to the signal line Sig2 in the second column. A signal processing circuit E2 including a circuit A2 and a first bias circuit B2 is provided. A signal processing circuit Ex including an amplifier circuit Ax and a first bias circuit Bx is provided corresponding to the x-th signal line Sigx. That is, the semiconductor integrated circuit device 204 has signal processing circuits E1 to En corresponding to the signal lines Sig1 to Sign for each column of the detector 201.

  The amplifier circuit A of the present embodiment includes AMP1 that is a current source of the amplifier circuit A, AMP2 and AMP3 that are input differential pairs, AMN1 and AMN2 that are active loads, and AMP4 and AMP5 that constitute a gate ground circuit. Have. The gate of the current source AMP1 is a bias input terminal of the amplifier circuit A. The gate ground circuit of the amplifier circuit A can increase the amplification gain of the amplifier circuit. The gates of AMP4 and AMP5 serve as bias input terminals for the grounded gate circuit. The amplifier circuit A of the present embodiment has two signal input terminals, a normal input terminal and an inverted input terminal, and a signal output terminal out, and has a so-called differential amplifier circuit configuration. Here, AMP1 to AMP5 are PMOS transistors, and AMN1 to AMN2 are NMOS transistors. The signal line Sig is electrically connected to the inverting input terminal inn of the amplifier circuit A, and the sample and hold circuit unit is electrically connected to the signal output terminal out. The normal input terminal inp of the amplifier circuit A is electrically connected to a reference power source Vref that supplies a reference potential of the amplifier circuit. The reference power source Vref supplies a reference potential as a reference signal serving as a reference for the amplification operation to the normal input terminal inp of the amplifier circuit. Therefore, the reference potential is supplied to the signal input terminal of the amplifier circuit, unlike an operation bias for causing the amplifier circuit to perform an amplification operation.

  The first bias circuit B of the present embodiment includes BMN1 and BMN2 that constitute a current mirror circuit, and BMP1 that is an output element of the first bias circuit B. A constant current source bias1 as a bias source is electrically connected to a drain and a gate of BMN1 as an input element of the bias circuit via a bias (current setting) line BL1. On the other hand, a constant potential source Vss that provides a constant potential such as a ground potential is connected to the sources of BMN1 and BMN2 via a power supply line SL1. The drain of BMN2 is connected to the drain and gate of BMP1, and the gate of BMP1 and the gate of current source AMP1 of amplifier circuit A are connected to form a current mirror circuit. In this embodiment, the drain and gate of BMN1 and the sources of BMN1 and BMN2 are external input terminals of the first bias circuit B, and are electrically connected to a bias source such as a constant current source bias1 and a constant potential source Vss. Is done. Further, the drain and gate of BMP1 give a bias to the gate of AMP1 which is the bias input terminal of the amplifier circuit A. That is, the drain and gate of BMP1 are the output terminals of the bias circuit and are electrically connected to the bias input terminal of the amplifier circuit A. Here, BMP1 is a PMOS transistor, and BMN1 and BMN2 are NMOS transistors.

  Further, the signal processing circuit E of the present embodiment includes a second bias circuit b that applies a gate bias to the gates of the AMP4 and AMP5 of the grounded gate circuit of the amplifier circuit A. The second bias circuit b also supplies an operation bias for causing the amplifier circuit to perform an amplification operation. The signal processing circuit E1 includes a second bias circuit b1 corresponding to the gate ground circuit of the amplifier circuit A1, and the signal processing circuit E2 includes a second bias circuit b2 corresponding to the gate ground circuit of the amplifier circuit A2. Each is provided. The signal processing circuit Ex is provided with a second bias circuit bx corresponding to the gate ground circuit of the amplifier circuit Ax. That is, the semiconductor integrated circuit device 204 has second bias circuits b1 to bn corresponding to the signal processing circuits E1 to En. The second bias circuit b includes bMP3 serving as an input element, bMN1 and bMN2 constituting a current mirror circuit, bMP2 serving as an output element, and bMP1 serving as a current source. A constant voltage source bias2 that is a bias source is electrically connected to a gate of bMP3 that is an input element of the second bias circuit b via a bias line BL2. On the other hand, a constant potential source Vss that provides a constant potential such as a ground potential is connected to the sources of bMN1 and bMN2 via a power supply line SL2. The drain of bMN1 is connected to the drain and gate of bMP2, and the gate of bMP2 is connected to the gates of AMP4 and AMP5 of the gate ground circuit of the amplifier circuit A. In the present embodiment, the gate of bMP3 and the sources of bMN1 and bMN2 serve as external input terminals connected to bias sources such as the constant voltage source bias2 and the constant potential source Vss. Further, the drain and gate of bMP2 apply a bias to the gates of AMP4 and AMP5, which are gate bias input terminals of the amplifier circuit A, and serve as output terminals of the second bias circuit. Here, bMP1 to bMP3 are PMOS transistors, and bMN1 to bMN2 are NMOS transistors. The constant voltage source bias2 applies a bias to the bMP3 in conjunction with a reference power supply Vref that supplies a reference potential to the normal input terminal inp of the amplifier circuit A.

  In the present embodiment, the plurality of signal processing circuits E1 to En of the semiconductor integrated circuit 204 are divided into a plurality of groups. In the present embodiment, among the signal processing circuits E1 to En, the signal processing circuits E1 to Ex are included in a first group (Group1) which is one group. A plurality of such groups are provided and included in one semiconductor integrated circuit 204. Here, x is a natural number greater than or equal to 2 and smaller than n, and is a divisor of n. That is, in the semiconductor integrated circuit device 204 including n signal processing circuits E corresponding to pixels of m rows and n columns of the detector 201, x signal processing circuits E are provided in one group. , N / x such groups are provided. In one group, the external input terminals of the bias circuits are connected by a common connection wiring. In the present embodiment, the drain and gate of BMN1 of each first bias circuit B are connected within the group by a bias line BL1, and the sources of BMN1 and BMN2 of each first bias circuit B are power sources within the group. Connected by line SL1. In addition, the gate of bMP3 of each second bias circuit b is connected by a bias line BL2 within the group, and the sources of bMN1 and bMN2 of each second bias circuit b are connected by a power line SL2 within the group. Yes.

  A connection wiring for commonly connecting the external input terminals of the bias circuits is divided for each group. That is, the plurality of signal processing circuits of the semiconductor integrated circuit device are divided into a plurality of groups, and the semiconductor integrated circuit device has a plurality of connection wirings divided and provided for each group. In each group, the external input terminals of the respective bias circuits are connected in common by connection wirings divided for each group. In the present embodiment, among the first bias circuits B1 to Bn, the first bias circuits B1 to Bx belong to the first group (Group1). The drains and gates of BMN1 of the first bias circuits B1 to Bx are connected to the bias line BL1-2 of the second group (Group2), which is another group, by the divided bias line BL1-1. Further, the sources of BMN1 and BMN2 of the first bias circuits B1 to Bx are connected to the power supply line SL1-2 of the second group (Group2) which is another group by the divided power supply line SL1-1. In the present embodiment, among the second bias circuits b1 to bn, the second bias circuits b1 to bx belong to the first group (Group1). The sources of bMN1 and bMN2 of the second bias circuits b1 to bx are connected to the bias line BL2-2 of the second group (Group2), which is another group, by the divided bias line BL2-1. Further, the gates of bMP3 of the second bias circuits b1 to bx are connected to the power supply line SL2-2 of the second group (Group2) which is another group by the divided power supply line SL2-1. Note that the number of groups divided in one semiconductor integrated circuit device 204 is n / number obtained by dividing the number n of all signal processing circuits in the semiconductor integrated circuit device 204 by the number x of signal processing circuits in one group. x. The number n / x of this group is preferably 10 or more. This is because the fluctuation of the continuous image signal is desirably 1/10 or less of the noise component generated at random. As a result, the wiring gradient of the connection wiring such as the bias line and the power supply line and the potential gradient generated by the current flowing through them are divided, and the output gradient in the row direction of the image signal is divided accordingly. As a result, the output gradient of the image signal is reduced and dispersed in the row direction, so that it is possible to suppress a significant deterioration in the image quality of the image signal. Further, by connecting x external input terminals of the bias circuit, it is equivalent to effectively multiplying the gate width of the transistor serving as the external input terminal by x. Since the flicker noise of the transistor is inversely proportional to the product of the gate width and the gate length of the transistor, the noise of the signal processing circuit caused by the bias circuit is about 1 / √x compared to the case of not being connected in common.

  Here, the semiconductor integrated circuit device 204 has a plurality of bias sources such as a constant current source and a constant voltage source, and each group has a bias source corresponding to the group of signal processing circuits divided into a plurality of groups. It is preferable. It is preferable that the bias source for each group is connected corresponding to the connection wiring of the group. For example, as an extreme example of a configuration having a common bias source for a group of a plurality of signal processing circuits in a semiconductor integrated circuit device, which is another embodiment of the present invention shown in FIG. Consider a configuration having a common bias source. A connection line LL that connects a bias source bias1 and the like common to all the signal processing devices and a plurality of connection lines BL and the like is provided. When electromagnetic noise, resonance noise from the control circuit, or the like is mixed into the operation bias supplied from the common bias source bias1 or the like via the connection line LL and each connection line, the amplification of each amplifier circuit in the semiconductor integrated circuit Variations occur in the characteristics. This variation causes streak-like noise in the semiconductor integrated circuit unit in the image signal output from the imaging device in the row unit. Since the streak noise is conspicuous in the image signal, the image quality of the image signal output from the imaging device is significantly deteriorated. In the present embodiment, the constant current source bias1-1 that is a bias source corresponding to the plurality of first bias circuits B1 to Bx included in the plurality of signal processing circuits E1 to Ex belonging to the first group (Group1) is provided. Is provided. The constant current source bias1-1 is electrically connected to the drain and gate of the BMN1 which is an input element of each of the first bias circuits B1 to Bx via the bias line BL1-1. A constant potential source Vss is provided corresponding to the plurality of first bias circuits B1 to Bx. The constant potential source Vss is electrically connected to the sources of BMN1 and BMN2 of each of the first bias circuits B1 to Bx via the power supply line SL1-1. A constant voltage source bias2-1 that is a bias source is provided corresponding to the plurality of second bias circuits b1 to bx included in the plurality of signal processing circuits E1 to Ex belonging to the first group (Group1). . The constant voltage source bias2-1 is electrically connected to a gate of bMP3 which is an input element of each of the second bias circuits b1 to bx via a bias line BL2-1. Further, a constant potential source Vss is provided corresponding to the plurality of second bias circuits b1 to bx. The constant potential source Vss is electrically connected to the sources of bMN1 and bMN2 of each of the second bias circuits b1 to bx via the power supply line SL2-1. As described above, each group divided into the semiconductor integrated circuit device 204 has a plurality of bias sources connected corresponding to the connection wiring commonly connected to the external input terminal of each bias circuit. As a result, streak-like noise that may occur in the image signal is dispersed in the row direction, and it becomes possible to make the streak-like noise inconspicuous, and a significant reduction in the image quality of the image signal can be suppressed.

  Furthermore, in this embodiment, in each group, the output terminals of the bias circuits are connected in common by the connection wiring, and are connected in common to the bias input terminals of the amplifier circuits. In the present embodiment, the gate of BMP1 of the first bias circuit B1 to Bx belonging to the first group (Group1) is divided from the connection wiring CL1-2 of the second group (Group2) which is another group. They are commonly connected by a connection wiring CL1-1. The gate of BMP1 of the first bias circuits B1 to Bx and the connection wiring CL1-1 are connected in common with the gate of AMP1 of the corresponding amplifier circuits A1 to Ax. In the present embodiment, among the second bias circuits b1 to bn, the drain and gate of bMP2 of the second bias circuits b1 to bx belonging to the first group are connected to the second group which is another group. The connection wiring CL2-2 is connected to the divided connection wiring CL2-1. Then, the drain, gate and connection wiring CL2-1 of bMP2 of the second bias circuits b1 to bx are connected in common with the gates of AMP4 and AMP5 which are input terminals of the gate ground circuit of the corresponding amplifier circuits A1 to Ax. Has been. Thus, by connecting x output terminals of the bias circuit, it is equivalent to effectively multiplying the gate width of the transistor serving as the output terminal by x. Since the flicker noise of the transistor is inversely proportional to the product of the gate width and the gate length of the transistor, the noise of the signal processing circuit caused by the bias circuit is about 1 / √x compared to the case of not being connected in common. Here, a simulation was performed on the relationship between the number x of signal processing circuits included in the group and the noise output. The results are shown in FIG. The simulation of FIG. 4 is performed for a configuration in which 260 signal processing circuits are arranged in one semiconductor integrated circuit device. In FIG. 4, when the number x of signal processing circuits included in a group is increased, the influence of noise caused by the bias circuit is improved, so that the noise characteristics of the signal processing circuit are reduced. When x is set to 20, it is reduced by about 95%, and even if x is further increased, the noise characteristic reduction effect of the signal processing circuit is not dramatically improved. Therefore, regarding the noise characteristic reduction effect of the signal processing circuit, x is preferably 20 or more, and accordingly n / x is preferably 13 or less. Considering the above-described effect on the potential gradient and the effect of reducing the noise characteristics of the signal processing circuit, it is desirable that the number n / x of groups in one semiconductor integrated circuit device is 10 or more and 13 or less. In FIG. 1, the constant current input to the external input terminal of the first bias circuit B is set small to reduce power consumption, and the ratio of the gate width of BMP1 to AMP1 (mirror ratio R (R is a real number). It is effective to design large))). By applying FIG. 1, the effective mirror ratio can be reduced, and the noise generated in BMN1, BMN2, and BMP1 of the first bias circuit 5 is propagated to the amplifier circuit A by R / x times, and the noise characteristics of the signal processing circuit Is improved. The power consumption and layout area of the amplifier circuit A are almost determined from the required performance. If the power consumption and layout area of the first bias circuit B of FIG. 1 are designed to be as small as possible, the mirror ratio R between BMP1 and AMP1 will eventually increase to some extent. When there is a difference in power consumption between the first bias circuit B and the amplifier circuit A in FIG. 1, that is, when the mirror ratio R is increased, the effective mirror ratio can be reduced by applying the present invention. Noise characteristics are improved. That is, when the power consumption W1 of the amplifier circuit A in FIG. 1 and the power consumption W2 of the first bias circuit B are in the relationship of W1> W2, the effect of this embodiment is greatly obtained and the noise characteristics are improved.

  In this embodiment, the external input terminal of each bias circuit is connected to each group by a common connection wiring, so that a significant deterioration in image quality due to the output gradient can be suppressed. Further, by connecting the output terminal of each bias circuit in common to each group and connecting it in common to the bias input terminal of each amplifier circuit, noise reduction of the obtained image signal is achieved. By disposing the bias circuits in a distributed manner, the degree of freedom in design for achieving low power consumption and small area is increased, and a suitable circuit design corresponding to the required characteristics of the image signal can be achieved. Easy to do. As a result, it is possible to suitably achieve low noise, low power consumption, and small area required as a semiconductor integrated circuit device including a signal processing circuit used in an imaging device.

  The signal processing circuit in the present invention is not limited to the form described in this embodiment, and various forms can be used. An example of another signal processing circuit will be described with reference to FIG. Note that in FIG. 5, for the sake of explanation and simplification of the drawing, description will be made using one signal processing circuit.

  FIG. 5A is a schematic equivalent circuit diagram of a first example of a signal processing circuit applicable to the present invention. In the first example, the amplification circuit A ′ of the signal processing circuit E ′ does not include AMN1 and AMN2 constituting the gate ground circuit of the amplification circuit A of FIG. In addition, the second bias circuit b is also omitted. The rest of the configuration is the same as that described with reference to FIG. FIG. 5B is a schematic equivalent circuit diagram of a second example of a signal processing circuit applicable to the present invention. The first bias circuit B ′ of the second example is changed to a current mirror circuit composed of BMN1 and BMN2 of the first bias circuit B of the first example, and BMN1 in which the constant voltage source bias2 is connected to the gate. It is configured using. Accordingly, a constant voltage source bias2 is used instead of the constant current source bias1 of the first example. The rest of the configuration of the signal processing circuit E ″ is the same as that of the first example, and a description thereof will be omitted. FIG. 5C is a schematic diagram of a third example of the signal processing circuit applicable to the present invention. In the first bias circuit B ″ ′ of the third example, BMN2 and BMP1 of the first bias circuit B ′ of the first example are omitted, and the gate and drain of BMN1 are output terminals. ing. In addition, the amplifier circuit A ″ of the third example is a source follower circuit having AMN1 as an input and AMN2 as a load. Such a configuration is used when an input signal is output with an amplification gain of approximately 1 and transmitted to the subsequent stage. The signal processing circuit E ′ ″ is used by shifting the level of the input signal and transmitting it to the subsequent stage. The signal processing circuit E ′ ″ is current-generated by the BMN1 of the first bias circuit B ″ ′ and the load AMN1 of the source follower circuit. The other signal processing circuit described here is an example, and various amplifier circuits, bias circuits, and second bias circuits can be appropriately combined, and a constant current source as a bias source and The constant voltage source is appropriately selected according to the configuration of the signal processing circuit used.

  In this embodiment, the image pickup apparatus in which the detector and the semiconductor integrated circuit device are provided on different substrates has been described. However, the present invention is not limited to this. The present invention can also be applied to an imaging device in which a detector and a semiconductor integrated circuit device are prepared on the same semiconductor substrate. As an example of the detector prepared on the semiconductor substrate, FIG. 6 shows a schematic equivalent circuit diagram of a detector using an amplification type pixel such as a CMOS sensor.

  In FIG. 6, PD11 to PDNN are photodiodes, MN11 to MNNN are source followers, and MN1b to MNNb are current sources. The source followers MN11 to MNNN are connected to the current sources MN1b to MNNb to form a source follower circuit. The outputs of the photodiodes PD11 to PDNN are amplified by a source follower circuit and output. A current mirror circuit is configured by connecting the gate terminals of the current sources MN1b to MNNb, which are loads of the source follower circuit, and the gate terminals and the drain terminals of MN1a to MNNa, which are bias circuits. The output of the source follower circuit is common for each column, and the photodiodes PD11 to NN are selected by the switches S11 to SNN. By making the load of the source follower circuit common to each column, an increase in layout area due to an increase in the number N of arrangements is reduced. When the output terminals bs21 to bs2N of the bias circuit are connected two by two, the gate width of the transistor constituting the bias circuit is effectively doubled. Since the noise caused by the bias circuit is about {fraction (1/2)} as compared with the configuration in which the output terminals bs21 to bs2N are not connected, the noise of the source follower circuit output is reduced.

(Second Embodiment)
The semiconductor integrated circuit device according to this embodiment will be described with reference to FIG. The same constituent elements as those in the first embodiment are given the same numbers or symbols, and descriptions thereof are omitted. FIG. 7 is a schematic equivalent circuit diagram of the semiconductor integrated circuit device according to the present embodiment.

  The present embodiment is different from the first embodiment in that the first group includes x signal processing circuits E1 to E (2x−) corresponding to the odd-numbered signal lines Sig1 to Sig (2x−1). 1) is included. The second group includes x signal processing circuits E2 to E2x corresponding to the even-numbered signal lines Sig2 to Sig2x. That is, in the present embodiment, a signal processing circuit corresponding to a predetermined signal line among a plurality of signal lines included in the detector, and a signal processing circuit corresponding to a signal line that is not physically adjacent to the predetermined signal line, Are included in one group of semiconductor integrated circuit devices. As in the first embodiment, the plurality of signal processing circuits of the semiconductor integrated circuit device are divided into a plurality of groups, and the semiconductor integrated circuit device has a plurality of connection wirings divided and provided for each group. Have. In each group, the external input terminals of the respective bias circuits are connected in common by connection wirings divided for each group. In addition, the semiconductor integrated circuit has a plurality of bias sources, each group has a bias source corresponding to the group of signal processing circuits divided into a plurality, and each group bias source corresponds to the connection wiring of the group. Connected. Further, in one group of semiconductor integrated circuit devices, the output terminals of the respective bias circuits are commonly connected by connection wirings, and are commonly connected to the bias input terminals of the respective amplifier circuits. In the present embodiment, in addition to the effects of the first embodiment, it is difficult to recognize the characteristic difference by increasing the spatial frequency at which the characteristic difference between the signal processing circuits appears, and the image quality of the image signal is significantly reduced. There is an effect that can be suppressed more.

  In the present embodiment, groups corresponding to odd columns and even columns are provided, but the present invention is not limited thereto. For example, a group may be constituted by a plurality of signal processing circuits corresponding to every two or three columns of signal lines, or a plurality of signal processing circuits corresponding to every two consecutive signal lines. A single group may be configured.

(Third embodiment)
Next, a radiation imaging system using a radiation imaging apparatus which is an imaging apparatus according to the present invention will be described with reference to FIG.

  As shown in FIG. 8, X-rays 6060 generated by an X-ray generator 6050 serving as a radiation source pass through a chest 6062 of a patient or subject 6061 and enter a radiation imaging apparatus 6040. This incident X-ray includes information inside the body of the patient 6061. Corresponding to the incidence of X-rays, the phosphor of the radiation imaging apparatus 6040 emits light and photoelectrically converts the light to obtain electrical information. This information can be digitally converted and image-processed by an image processor 6070 serving as signal processing means, and observed on a display 6080 serving as display means in the control room.

  Further, this information can be transferred to a remote place by transmission processing means such as a telephone line 6090 and displayed on a display 6081 serving as display means such as a doctor room in another place or recorded on a recording medium such as an optical disk by recording means such as an optical disk device. Can be saved. Therefore, it is possible for a remote doctor to make a diagnosis. It can also be recorded on the film 6110 by the film processor 6100.

  In the present invention, the plurality of signal processing circuits of the semiconductor integrated circuit device are divided into a plurality of groups, and the semiconductor integrated circuit device has a plurality of connection wirings provided for each group. In each group, the external input terminals of the respective bias circuits are connected in common by connection wirings divided for each group. And the connection by connection wiring is divided | segmented for every group. Thereby, the wiring resistance of the connection wiring connected to the bias source and the potential gradient generated by the current flowing through them are divided, and the output gradient in the row direction of the image signal is divided accordingly. As a result, the output gradient of the image signal is reduced and dispersed in the row direction, so that it is possible to suppress a significant deterioration in the image quality of the image signal.

  In the present invention, the semiconductor integrated circuit has a plurality of bias sources, and each group has a bias source corresponding to the group of signal processing circuits divided into a plurality of groups, and the bias source for each group is a connection wiring of the group. Are connected correspondingly. As a result, streak-like noise that may occur in the image signal is dispersed in the row direction, and it becomes possible to make the streak-like noise inconspicuous, and a significant reduction in the image quality of the image signal can be suppressed.

  Furthermore, in the present invention, in one group of semiconductor integrated circuit devices, the output terminals of the respective bias circuits are electrically connected in common by the connection wiring, and are commonly connected to the bias input terminals of the respective amplifier circuits. As a result, the influence of noise caused by the bias circuit is improved, so that the noise characteristics of the signal processing circuit are reduced, and the image quality of the image signal becomes better.

  In the present invention, by disposing the bias circuits in a distributed manner, the degree of freedom in design for achieving low power consumption and a small area is improved, and the bias circuit is suitable for the characteristics of the required image signal. Circuit design can be easily performed.

  INDUSTRIAL APPLICABILITY The present invention can be applied to a medical radiation imaging apparatus that converts radiation such as X-rays or γ-rays into an electrical signal and outputs an image signal, or an imaging apparatus used in a digital camera, etc. Is done.

1 is a schematic equivalent circuit diagram of a semiconductor integrated circuit device used in an imaging device according to a first embodiment of the present invention. 1 is a schematic equivalent circuit diagram of an imaging apparatus according to a first embodiment of the present invention. 1 is a plan view illustrating a schematic configuration of an imaging apparatus according to a first embodiment of the present invention. It is a graph which shows the simulation result performed about the relationship between the number x of a signal processing circuit, and a noise output. 1 is a schematic equivalent circuit diagram showing an example of a signal processing circuit applicable to the present invention. It is a schematic equivalent circuit diagram which shows the other detector applicable to the imaging device of this invention. FIG. 6 is a schematic equivalent circuit diagram of a semiconductor integrated circuit device according to a second embodiment of the present invention. It is the schematic which shows the radiation imaging system using the radiation imaging device which is an imaging device which concerns on this invention. FIG. 6 is a schematic equivalent circuit diagram of a semiconductor integrated circuit device used in an imaging device according to another embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 201 Detector 202 Pixel 203 Drive circuit 204 Integrated circuit device S11-Smn Conversion element T11-Tmn Switch element Vg1-Vgm Drive line Sig1-Sign Signal line E, E1-En Signal processing circuit A, A1-An Amplifier circuit B, B1 ˜Bn first bias circuit b, b1 to bn second bias circuit bias1 constant current source bias2 constant voltage source Vss constant potential source BL bias line SL power supply line CL connection wiring

Claims (12)

An amplifier circuit having a bias input terminal;
A bias circuit having an input terminal electrically connected to a bias source and an output terminal electrically connected to the bias input terminal, and supplying an operation bias to the amplifier circuit;
An integrated circuit device including a plurality of signal processing circuits having
The plurality of signal processing circuits are divided into a plurality of groups,
There are a plurality of connection wirings provided separately for each group, and the input terminal of the plurality of bias circuits included in one group of the plurality of groups is one of the plurality of connection wirings. Connected in common ,
2. The integrated circuit device according to claim 1, wherein the amplifier circuit has a grounded gate circuit, and the bias input terminal includes a gate of a transistor constituting the grounded gate circuit. An amplifier circuit having a bias input terminal;
A bias circuit having an input terminal electrically connected to a bias source and an output terminal electrically connected to the bias input terminal, and supplying an operation bias to the amplifier circuit;
An integrated circuit device including a plurality of signal processing circuits having
The plurality of signal processing circuits are divided into a plurality of groups,
There are a plurality of connection wirings provided separately for each group, and the input terminal of the plurality of bias circuits included in one group of the plurality of groups is one of the plurality of connection wirings. Connected in common,
  The amplifier circuit includes a transistor that is a current source of the amplifier circuit and a transistor that forms a grounded gate circuit, and the bias circuit is electrically connected to a gate of the transistor that is a current source of the amplifier circuit. An integrated circuit device comprising: a first bias circuit having an output terminal; and a second bias circuit having an output terminal electrically connected to a gate of a transistor constituting the grounded gate circuit. . An amplifier circuit having a bias input terminal;
A bias circuit having an input terminal electrically connected to a bias source and an output terminal electrically connected to the bias input terminal, and supplying an operation bias to the amplifier circuit;
An integrated circuit device including a plurality of signal processing circuits having
The plurality of signal processing circuits are divided into a plurality of groups,
There are a plurality of connection wirings provided separately for each group, and the input terminal of the plurality of bias circuits included in one group of the plurality of groups is one of the plurality of connection wirings. Connected in common,
When n signal processing circuits are included and x signal processing circuits are included in the one group, the number n / x of the plurality of groups is 10 or more and 13 or less, and x is 2 or more. An integrated circuit device having a natural number smaller than n and a divisor of n. Further, a plurality of bias sources are provided corresponding to the plurality of groups, and one of the bias sources corresponding to the one group among the plurality of bias sources and the connection wiring of the one group are electrically connected. integrated circuit device according to any one of claims 1-3 to be connected. Integrated circuit device according the output terminals of the plurality of the bias circuit of claims 1 to be electrically connected in common to any one of 4 included in one group of the plurality of groups. The amplifier circuit has a transistor which is a current source of the amplifier circuit, the bias input terminal integrated circuit device according to claim 1, any one of 5, including a gate of said transistor. A detector having a plurality of pixels including a conversion element for converting radiation or light into an electrical signal, and having a plurality of signal lines for transmitting in parallel the electrical signal output from the pixel;
An amplifier circuit having a bias input terminal for inputting an electric signal transmitted in parallel and amplifying the input electric signal; an input terminal electrically connected to a bias source; and the bias input terminal A plurality of signal processing circuits corresponding to a plurality of the signal lines, each of the signal processing circuits including a bias circuit that has an output terminal electrically connected and supplies an operation bias to the amplifier circuit. An integrated circuit device in which the circuit is divided into a plurality of groups;
An imaging device having
The integrated circuit device includes a plurality of connection wirings provided separately for each group, and a plurality of the input terminals of the plurality of bias circuits included in one group among the plurality of groups. Connected in common by one of the connecting wires ,
A signal processing circuit corresponding to a predetermined signal line among the plurality of signal lines and a signal processing circuit corresponding to a signal line not physically adjacent to the predetermined signal line are included in the one group. and which signal processing circuit corresponding to the predetermined signal line physically adjacent signal lines among the plurality of signal lines, capturing characterized that you have been included in the different groups and the one group apparatus. A detector having a plurality of pixels including a conversion element for converting radiation or light into an electrical signal, and having a plurality of signal lines for transmitting in parallel the electrical signal output from the pixel;
An amplifier circuit having a bias input terminal for inputting an electric signal transmitted in parallel and amplifying the input electric signal; an input terminal electrically connected to a bias source; and the bias input terminal A plurality of signal processing circuits corresponding to a plurality of the signal lines, each of the signal processing circuits including a bias circuit that has an output terminal electrically connected and supplies an operation bias to the amplifier circuit. An integrated circuit device in which the circuit is divided into a plurality of groups;
An imaging device having
The integrated circuit device includes a plurality of connection wirings provided separately for each group, and a plurality of the input terminals of the plurality of bias circuits included in one group among the plurality of groups. Connected in common by one of the connecting wires,
When the integrated circuit device has n signal processing circuits and x signal processing circuits in the one group, the number n / x of the plurality of groups is 10 or more and 13 or less, An imaging apparatus, wherein x is a natural number greater than or equal to 2 and less than n and is a divisor of n. The detector includes N columns of pixels, and the integrated circuit device is provided corresponding to the n columns of pixels among the N columns of pixels, and N / n integrated circuits are provided. The imaging device according to claim 8, wherein a circuit device is provided. The integrated circuit device further includes a plurality of bias sources corresponding to the plurality of groups, and one bias source corresponding to the one group among the plurality of bias sources and the connection wiring of the one group. The imaging device according to any one of claims 7 to 9 , wherein and are electrically connected. The bias circuit has an output terminal electrically connected to the bias input terminal, and the output terminals of a plurality of the bias circuits included in one group among the plurality of groups are electrically common. The imaging device according to any one of claims 7 to 10, which is connected. Imaging system including an imaging device; and a signal processing means for processing the signal from the imaging device in any one of claims 7 11.

Images