JP3305259B2 - Active matrix type liquid crystal display device and substrate used therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device and a matrix substrate used for the liquid crystal display device.

[0002]

2. Description of the Related Art As is well known, in an active matrix type liquid crystal display device, two glass substrates are fixed to face each other.
Liquid crystal is sealed in the gap, and a transparent common electrode is formed on one glass substrate, and a large number of transparent pixel electrodes are formed in a matrix on the other glass substrate, and each pixel electrode is Circuits for individually applying voltages are formed.

FIG. 15 shows a general structure of an active matrix type liquid crystal display device of this type, and more specifically, is a plan view of the same device in which the pixel electrode is formed. . This active matrix liquid crystal display device has a pixel matrix PX (i, j) of m rows and n columns.
(I = 1 to m, j = 1 to n), a part of which is shown in FIG. In the figure, rectangles arranged vertically and horizontally are indicated by broken lines, each of which represents a pixel.

As shown in the figure, each pixel is regularly arranged in a horizontal direction (column direction) and a vertical direction (row direction), and n data lines D correspond to each column of these pixels.
j (j = 1 to n) are formed, and m gate lines Gi (i = 1 to m) are formed corresponding to each row of the pixels. Here, each data line Dj (j = 1 to n) is a line that supplies a signal voltage to each pixel PX (i, j) (i = 1 to m, j = 1 to n). In addition, the gate line Gi (i = 1 to 1)
m) is the gate voltage for writing the signal voltage to the pixel, and the pixel voltage PX (i, j) (i = 1 to m, j = 1)
To n).

Each pixel PX (i, j) has a TFT (Thin Film Transistor) 1 in addition to the pixel electrodes described above. The TFT 1 has a source electrode connected to the data line Dj, a gate electrode connected to the gate line Gi, and a drain electrode connected to the pixel electrode. Here, the liquid crystal is interposed between the pixel electrode and the above-described common electrode. The capacitance 2 in FIG. 15 represents the liquid crystal capacitance sandwiched between the pixel electrode and the common electrode.
The TFT 1 functions as a switching element for switching whether to perform writing to the pixel, that is, whether to apply a signal voltage supplied via the data line Dj to the liquid crystal capacitor 2.

Next, the operation of the active matrix type liquid crystal display device will be described. In this active matrix type liquid crystal display device, m gate lines Gi (i = 1
To m) are sequentially scanned, and an image of one screen is displayed every fixed field cycle. Here, there are two methods of scanning a gate line, a non-interlace method and an interlace method.
There are types. FIGS. 16A and 16B show that m = 480.
The scanning order of each gate line in each of these methods is shown as an example.

In the non-interlace method, one field period is required, and a gate voltage is sequentially applied to the 480 gate lines G1 to G480 for a certain period of time as illustrated on the left side of FIG. The same operation is repeated every time a new one is switched. Such application of the gate voltage to each gate line is performed by a gate driver (not shown).

In each field period, each gate line G
A gate voltage is applied to each of 1 to G480 once. Here, assuming that a gate voltage is applied to a certain gate line Gi, the gate voltage becomes n which forms the i-th row of the pixel matrix.
The voltage is applied to the gate of each TFT 1 of the pixels PX (i, j) (j = 1 to n), and these TFTs 1 are turned on. Further, during the period in which the gate voltage is applied to the gate line Gi, a signal voltage for n pixels is output to n data lines Dj (j = 1 to n) by a data driver (not shown). The signal voltages for these n pixels are respectively applied to the liquid crystal capacitors 2 of the pixels PX (i, j) (j = 1 to n) via the above-described TFTs 1 in the conductive state. As a result, n pixels PX (i, j) (j = 1
To n), a line image corresponding to one horizontal scanning line is displayed. Such application of the gate voltage and the signal voltage is performed for the first row to the 480th row of the pixel matrix, whereby an image for one screen is displayed.

On the other hand, in the interlace system, as shown on the right side of FIG. 16, for example, in a certain field period, for example, odd-numbered gate lines G1, G3, G5,.
When the gate voltage is applied to the gate line 79, the even-numbered gate lines G2, G4, G6,.
A gate voltage is applied to 0, scanning of a different gate line is performed in each field cycle, and an operation of displaying an image for one screen in two field cycles is repeated. In the case of this interlace method, the gate voltage has only to be applied to one gate line Gi once every two field periods, so that there is an advantage that power consumption can be saved.

[0010]

Incidentally, the above-mentioned conventional active matrix type liquid crystal display device has a data line for each column constituting a pixel matrix, so that the number of pixels per row is large. Requires the use of a large number of data drivers accordingly. However, since the data driver is a relatively expensive component, the use of a large number of the data driver makes the entire device expensive. For example, a VGA-compatible liquid crystal display panel having 1920 pixels in the column direction and 480 pixels in the row direction has 192 pixels.
It has zero data lines and 480 gate lines. 2
Assuming that the liquid crystal display panel is constituted by the above-mentioned prior art using a data driver and a gate driver having 40 output terminals, eight data drivers are provided along the column direction and gate drivers are provided along the row direction. It is necessary to provide two. When eight data drivers are used in this way, the liquid crystal display panel becomes expensive.

In addition, the above-described conventional technique has a problem that it is difficult to form a liquid crystal display panel having a small display area. In other words, a data wiring terminal portion, which is a frame portion of the liquid crystal display panel, is provided with a large number of terminals for supplying signal voltages to the above-described data lines. It is necessary to reduce the size of the data wiring terminal. And
In order to reduce the size of the data wiring terminals, it is necessary to narrow the pitch of the terminals corresponding to the data lines. However, the liquid crystal display panel according to the prior art has a large number of data lines, so The demands for conversion will be extremely severe. For this reason, it is difficult to manufacture the data wiring terminal portion, which causes a problem such as a decrease in yield.

The present invention has been made in view of the above circumstances, and provides an active matrix type liquid crystal display device capable of driving each pixel with a smaller number of data lines as compared with the related art, and a substrate used therefor. It is intended to be.

[0013]

According to the present invention, there is provided a substrate for an active matrix type liquid crystal display device, wherein a plurality of data lines and a plurality of gate lines are provided in a matrix on a substrate, and a thin film transistor and a pixel electrode connected to the thin film transistor are provided. Is provided in correspondence with each of the plurality of gate lines, and the plurality of gates are controlled such that the pixel electrode is controlled by a signal from one of the corresponding gate lines among the gate lines arranged with the pixel electrodes interposed therebetween. Wire and arrange the thin film
A transistor which forms a transistor and is electrically connected to the pixel electrode;
The rain electrode serves as the gate electrode forming the thin film transistor.
It is characterized by crossing . In the substrate for an active matrix type liquid crystal display device of the present invention,
One data line supplies a signal voltage to the pixel electrodes arranged on both sides thereof. Also, by applying a gate voltage to one of the gate lines disposed across the pixel electrodes on both sides of the data line, a signal voltage is applied to half of the pixel electrodes arranged along the gate line. Is written, and by applying a gate voltage to the other gate line, a signal voltage is written to the other half of the pixels.
Therefore, according to the substrate of the present invention, the number of data lines is reduced to half that of the conventional one, so that the number of expensive data drivers can be reduced by half.

It is preferable that a gate electrode forming a TFT is constituted by the gate line itself, and a drain electrode electrically connected to the pixel electrode crosses the gate electrode. With this structure, even if a photomask shift occurs between the gate electrode forming step and the drain electrode forming step in the process of manufacturing the substrate for an active matrix liquid crystal display device, even if the alignment of the drain electrode with respect to the gate electrode is shifted. Since the parasitic capacitance Cgd between the gate and the drain of the two TFTs sandwiched between the adjacent data lines is equal to that of the normal case and the feedthrough voltage ΔVp is equal, the occurrence of flicker and uneven brightness is prevented. be able to.

In the substrate for an active matrix type liquid crystal display device, a storage capacitor is provided corresponding to each of the pixel electrodes, and a data line is formed between the adjacent data lines.
A storage capacitor line is provided in a boundary region between the pixels not provided in parallel with the data line, and one storage line is provided for two pixel columns.
It is possible to adopt a configuration in which a capacitor line is shared, and one electrode of the storage capacitor is connected to a pixel electrode corresponding to the storage capacitor, and the other electrode of the storage capacitor is connected to the storage capacitor line. According to this invention, since the storage capacitor is connected to each pixel electrode, the ability of each pixel to hold the signal voltage can be increased. In addition, a write current for two pixels flows from each storage capacitor on both sides of each storage capacitor line. Therefore, by outputting a signal voltage to each data line so that a signal voltage of the opposite polarity is applied to the adjacent data line, a write current flowing through each storage capacitor line is canceled, and a write shortage occurs. Generation can be prevented.

An active matrix type liquid crystal display device according to the present invention is characterized in that the above substrate is used as one substrate of a pair of substrates sandwiching liquid crystal. In the active matrix type liquid crystal display device, each time the field cycle is switched, an operation of sequentially supplying a gate voltage to one of the gate lines arranged across the pixel is performed, and the operation of sandwiching the pixel electrode is performed. Scanning means for alternately repeating the operation of sequentially supplying a gate voltage to the other gate line of the gate lines arranged in the above. According to this invention, the signal voltage is written to all the pixels in the pixel matrix in a period of two fields. Therefore, power consumption accompanying writing of a signal voltage can be reduced.

Further, the active matrix type liquid crystal display device of the present invention has a gate driver for sequentially outputting a gate voltage from an output terminal in each field cycle, and sequentially from an output terminal of the gate driver every time the field cycle is switched. An operation of sequentially supplying an output gate voltage to one of the gate lines disposed across the pixel electrode, and a step of applying a gate voltage sequentially output from an output terminal of the gate driver across the pixel electrode A demultiplexer that alternately repeats an operation of sequentially supplying the other of the arranged gate lines to the other gate line, wherein the demultiplexer and the pixel are manufactured by a common manufacturing process. is there. According to this invention, the same operation and effect as those of the above device can be obtained. Further, by providing the demultiplexer, the number of gate drivers can be reduced by half. In addition, since the demultiplexer and the pixel are formed by a common manufacturing process,
It can be manufactured without increasing the manufacturing cost.

Further, in the active matrix type liquid crystal display device according to the present invention, the first start pulse is sequentially shifted, and the output signal of each stage is used as a gate voltage, and one of the gate lines arranged with the pixel electrode interposed therebetween. A first shift register for supplying a gate line and a second start pulse are sequentially shifted, and an output signal of each stage is supplied as a gate voltage to the other one of the gate lines disposed across the pixel electrode. And a second shift register, wherein the first and second shift registers and the pixel are manufactured by a common manufacturing process. According to this invention, the same operation and effect as those of the above device can be obtained. Further, the provision of the first and second shift registers eliminates the need for externally attaching a gate driver. Further, since each shift register and pixel are formed by a common manufacturing process, the shift register and the pixel can be manufactured without increasing the manufacturing cost.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. [First Basic Configuration Example ] FIG. 1 is a plan view showing a substrate configuration of an active matrix liquid crystal display device which is a first basic configuration example of the present invention. As in FIG. 15 described above, each rectangle indicated by a broken line is a pixel matrix P
Each pixel constituting X (i, j) (i = 1 to m, j = 1 to n) is shown. The active matrix type liquid crystal display device shown in FIG. 15 has a pixel matrix PX (i, j) (i =
1 to m, j = 1 to n), one for each data line Dj
And one gate line Gj for each row. On the other hand, in the active matrix type liquid crystal display device according to the basic configuration example shown in FIG. 1, the pixel matrix PX (i, j) (i = 1 to m, j = 1 to n) is divided into two columns each. As described above, n / 2 data lines are formed, and each data line is a TFT1 of 2m pixels on each side.
Are connected to the source electrode of FIG. 1 illustrates three of these data lines Dj-2, Dj, and Dj + 2.

Further, the pixel matrix PX (i, j) (i = 1 to 1)
m, j = 1 to n), n constituting each row
Gate lines GAi so as to sandwich the pixels from both sides.
(I = 1 to m) and the second gate line GBi (i = 1 to m).
m) are each formed. The n pixels forming each row are separated by the above-mentioned n / 2 data lines, and two pixels are sandwiched between each data line. Each gate line alternately shares these data lines, and supplies a gate voltage to the TFT 1 of two pixels between each data line. The first and second gate lines provided in each row share different data lines between adjacent rows, and supply a gate voltage to the TFT 1 of the pixel between the data lines.

For example, focusing on the i-th row, the data line Dj
-2 and PX (i, j-1), Pj between Dj
A gate voltage is supplied to X (i, j) by the second gate line GBi, and two pixels PX (i, j +) sandwiched between the adjacent data lines Dj and Dj + 2.
1), the first gate line G for PX (i, j + 2)
Ai supplies a gate voltage. On the other hand, in the (i-1) -th row adjacent to the i-th row, the first gate line GAi is provided for two pixels between the data lines Dj-2 and Dj.
The gate voltage is supplied by −1, and the gate voltage is supplied to the two pixels sandwiched between the adjacent data lines Dj and Dj + 2 by the second gate line GBi−1. . The same applies to the (i + 1) th row.

Next, a specific configuration of the TFT in the substrate for an active matrix type liquid crystal display device of the present basic configuration example will be described. 2 and 3 show two pixels PX surrounded by data lines Dj-2 and Dj, a first gate line GAi, and a second gate line GBi in FIG.
It is a top view which shows the TFT part of (i, j-1) and PX (i, j). 2 adopts a so-called large island structure in which the width of the island 4 is larger than the width of the gate line GBi. FIG. 3 shows that the width of the gate line GBi is larger than the width of the island 5. The case where the large gate structure is adopted is shown.

The feature of the planar structure of the TFT 1 of this basic configuration example is common to FIGS. 2 and 3. The gate electrode constituting the TFT 1 is constituted by the gate line GBi itself, and the pixel electrode 6 is formed.
The drain electrode 7 electrically connected to the gate line GBi
At the point where it crosses. Although FIG. 1 is an equivalent circuit diagram, in the above description, "the data line is connected to the source electrode of the TFT 1", but in an actual configuration, as shown in FIG. 2 and FIG. , The data lines Dj-2 and Dj themselves are the source electrodes of the TFT1.

On the other hand, FIGS. 4A and 4B show a structure in which the structure of a conventional general TFT is adopted in the same place as described above. That is, the gate electrode 50 protrudes from the gate line GBi,
The source electrode 51 and the drain electrode 52 extend from both sides toward the center of the gate electrode 50. In this structure, as shown in FIG. 4A, if there is no misalignment between the gate layer and the source / drain layer, the parasitic capacitances Cgd _L3 and Cgd _R3 between the gate and the drain shown by oblique lines in the figure. Is the same for both left and right TFTs. However, as shown in FIG. 4B, when the source / drain layer is shifted to the left with respect to the gate layer, the left TF is
Cgd _L4 of T becomes large, and Cgd _{R4 of} right TFT becomes small. As a result, the right pixel and the left pixel have different feedthrough voltages ΔVp, and flicker and uneven brightness occur on the liquid crystal screen.

On the other hand, the basic configuration shown in FIGS. 2 and 3
In the case of the structure of the example , since the drain electrode 7 connected to the pixel electrode 6 crosses the gate electrode (gate line GBi), even if misalignment occurs, the gate-drain parasitic capacitance between the left and right TFTs Cgd _L1 and Cgd _R1 , Cgd _L2 and Cgd
_{Since R2} is equal to each other and the feedthrough voltage ΔVp is equal to each other, the occurrence of flicker and uneven brightness can be suppressed. FIGS. 2 and 3 show the case where the source / drain layers are shifted to the left with respect to the gate layer. However, even if the source / drain layers are shifted to the right or the angle is shifted (rotated), etc. Cgd _L and Cgd _R become equal, and the same effect can be obtained.

Next, the operation of the basic configuration example will be described. In this basic configuration example , an image of one screen is displayed in a two-field cycle by interlaced scanning in which the first and second gate lines are alternately scanned during each field cycle. That is, for example, in an odd field period, the first gate line GAi (i = 1 to m)
, A gate voltage is sequentially applied for a predetermined time. In addition, during a period in which a gate voltage is applied to each gate line, a signal voltage is output to n / 2 pixels connected to each gate line via n / 2 data lines. That is, in the example shown in FIG. 1, during the period when the gate voltage is applied to the gate line GAi, the pixels PX (i, j-2) connected to the gate line GAi via the data lines Dj-2, Dj, Dj + 2. , PX
Signal voltages are supplied to (i, j + 1) and PX (i, j + 2). As a result, in the odd field period, the gate line GA (i) among the pixels in m rows and n columns
The signal voltage is written to half the pixels connected to (i = 1 to n).

Then, in the next even-numbered field period, a gate voltage is sequentially applied to the second gate line GBi (i = 1 to m) for a predetermined time. In addition, during the period when the gate voltage is applied to each gate line, a signal voltage is applied to n / 2 pixels connected to each gate line via n / 2 data lines. As a result, in the even field period, the signal voltage is written to the other half pixels connected to the gate line GB (i) (i = 1 to n).

As described above, according to the basic configuration example , the signal voltage for one screen is written to all the pixels in m rows and n columns in a period of two fields, so that the image for one screen is completely formed. Is displayed with.

[0029] Having described structure and operation of the basic configuration example is as the follows lists the effects of the present exemplary basic configuration. (1) The number of data lines can be reduced to half of the conventional one. Therefore, the number of data drivers can be reduced, and the price of the entire device can be reduced. For example, when a VGA-compatible liquid crystal display panel having 1920 pixels in the column direction and 480 pixels in the row direction is configured, only 960 data lines are required. Thus, for example, 24
It is only necessary to provide four data drivers having zero output terminals along the column direction, so that the number of data drivers can be reduced by half and the cost of the device can be reduced. In the case of this basic configuration example , two gate lines are used per row, so that in the case of a VGA-compatible liquid crystal display panel, the number of gate lines is 960 and four gate drivers are used (conventionally. Are two). However, since the number of expensive data drivers is halved and the total number of parts is reduced, the overall price of the device is eventually reduced.

(2) Since the number of data lines is half that of the conventional case, even when a liquid crystal display panel having a small display area is constructed, the demand for narrowing the pitch of the data wiring terminal portions is not strict.

(3) In the conventional active matrix type liquid crystal display device described above, n data lines are driven in each field cycle. In the basic configuration example , only n / 2 data lines are driven in each field cycle. do not do. For this reason, in the present basic configuration example , the driving frequency of each data driver can be reduced to half of the conventional one. Further, as described above, the number of data drivers is reduced to half of the conventional one. Therefore, the power consumption of all data drivers is reduced to about 1/4 of the conventional one. In the present basic configuration example , the number of gate lines is twice as large as that of the conventional example , so that the required number of gate drivers increases. However, since the drive frequency of the gate driver is extremely lower than the drive frequency of the data driver, the increase in the total power consumption due to the increase in the number of gate drivers is small, and in the end, the total power consumption of the device is greatly reduced. Will be done.

(4) In the basic configuration example , the first and second gate lines alternately share each section divided by n / 2 data lines, and the gate voltage to the pixels in each section is divided. And between the adjacent rows, the first and second gate lines share different sections. Therefore, regardless of the odd field period or the even field period, Display is performed by n / 2 pixels in all rows, and m /
Display by two pixels is performed. Therefore, there is an advantage that line crawling in which unsightly vertical stripes or horizontal stripes appear on the screen hardly occurs.

(5) In the basic configuration example , the drain electrode connected to the pixel electrode traverses the gate line GBi as the planar structure of the TFT, so that the TFT has a structure between the gate layer and the source / drain layer. Even if misalignment occurs,
The left and right TFTs have the same Cgd, and the feedthrough voltage ΔV
Since p also becomes equal, it is possible to suppress the occurrence of flicker and uneven brightness.

[Second to Fourth Basic Configuration Examples ] FIGS. 5 to 7 show the configurations of the second to fourth basic configuration examples of the present invention, respectively. The specific connection relationship between each gate line and each pixel in each of these basic configuration examples is described in the first embodiment.
This is different from that shown in the basic configuration example . However, in each of the basic configuration examples , the n / 2 data lines share two columns each to supply a signal voltage, and the pixel has n / 2 first and second gate lines for each row. In that the gate voltage is supplied by sharing
There is no difference from the basic configuration example . Examples Each of these basic configurations <br/> is to clarify that the connection relationship between the gate lines and the pixel in the present invention there may be variously modified without being limited to the first basic configuration example above, the This is shown as a specific example. Also in each of these basic configuration examples , the first
Effects similar to the effects (1) to (3) described in the basic configuration example can be obtained. Regarding the effect of preventing line crawling, basic of the first basic configuration example or the third
The configuration example (FIG. 6) is the best, and the second basic configuration example (FIG. 5) and the fourth basic configuration example (FIG. 7) have a drawback that vertical stripes are more likely to appear than the others.

FIGS. 8 and 9 show a specific structure of a TFT corresponding to the equivalent circuit shown in FIGS. 5 and 6, respectively. FIG. 8 is a diagram when the large island structure is adopted, and FIG. 9 is a diagram when the large gate structure is adopted. As shown in these drawings, also in this basic configuration example a first group
As in the present configuration example , the drain electrode 7 connected to the pixel electrode 6
Has a configuration that crosses the gate lines GAi and GBi, respectively, so that even if misalignment occurs between the gate layer and the source / drain layer, the Cgd of the left and right TFTs is equal,
Since the feedthrough voltage ΔVp becomes equal, the occurrence of flicker and uneven brightness can be suppressed. That is, the effect (5) described in the first basic configuration example can be obtained.

The enhanced First Embodiment contrast and to reduce cross-talk, in order to enhance the image quality, it is effective to enhance the ability to hold a signal voltage of each pixel. For this reason, in an active matrix type liquid crystal display device, a configuration in which a storage capacitor is connected to each pixel electrode is often adopted. This embodiment is obtained by improving the configuration shown in the first basic configuration example and connecting a storage capacitor to each pixel electrode.
FIG. 10 shows the configuration of the present embodiment. As shown in this figure, each pixel PX (i, j) (i = 1 to m, j = 1 to n)
, Storage capacitors 3 are formed, and one electrode of the storage capacitors 3 is connected to the pixel electrode of each pixel (that is, one electrode of the liquid crystal capacitor 2). Further, each pixel PX (i, j) (i = 1 to m, j = 1 to n) is n /
Each pixel is divided into two columns by two data lines (three data lines Dj-2, Dj, and Dj + 2 are shown in FIG. 10), but each of these pixels is not formed with these data lines. Cs lines (storage capacitor lines) are formed in the boundary region between the data lines in parallel with the data lines. Storage capacity of each pixel 3
Is connected to a reference power source (not shown) via these Cs lines.

According to the present embodiment, the storage capacity 3 connected to each pixel electrode enhances the signal voltage holding capability of each pixel in this manner, and thus has the effect of increasing contrast and reducing crosstalk. can get. Further, according to the present embodiment, since one Cs line is shared by two pixel columns, the aperture ratio is reduced even if the number of gate lines is doubled as compared with the conventional case. Will not be invited. The inventor of the present application confirmed the effect of applying the structure according to the present embodiment to a conventional active matrix type liquid crystal display device, and designed the layout of the structure according to the present embodiment without changing the design rules. I tried. As a result, the same aperture ratio as the conventional one was obtained.

When the storage capacitor 3 is connected to each pixel electrode as in this embodiment, a write current flows to the Cs line when a signal voltage is written to each pixel. Therefore, when the wiring resistance of the Cs line is high, insufficient writing may occur due to the wiring resistance. This causes a decrease in image quality such as a decrease in contrast and an increase in crosstalk. As a means for preventing such a problem, it is conceivable to increase the width of the Cs line and reduce the wiring resistance, but this is not preferable because the aperture ratio is reduced.

Therefore, in this embodiment, due to its structure,
Taking advantage of the feature of the first embodiment in which a write current for two pixels always flows through each Cs line, a means is provided for canceling these write currents and reducing the voltage drop of each Cs line. More specifically, in the present embodiment, when a data driver (not shown) applies a signal voltage to each of n / 2 data lines, a signal voltage of opposite polarity is always applied to two adjacent data lines. To output each signal voltage.
That is, assuming that a gate voltage is applied to the gate line GBi in a certain field cycle, for example, a positive signal voltage is applied to the data line Dj-2 at this time,
A negative signal voltage is applied to the adjacent data line Dj. As a result of applying the signal voltage of the opposite polarity, the Cs line between the data lines Dj-2 and Dj is
A write current corresponding to each of these signal voltages flows, but these write currents cancel each other. Therefore, only a small current flows through the Cs line, and the problem of insufficient writing does not occur.

The case where the storage capacitance and the Cs line are added to the first basic configuration example (FIG. 1) has been described above. However, the fourth basic configuration example (FIG. 7) shows the case where the storage capacitance and the Cs line are added. An addition may be made. The fourth basic configuration example also, the first basic
Similar to the configuration example, since the same time a configuration in which the write current flows through the two pixels sandwiched between two data lines, each write in the Cs line when taken in the form on purpose similar configuration of the present embodiment This is because the current can be offset.

[ Second Embodiment] FIGS. 11A and 11B show a configuration of an active matrix liquid crystal display device according to a second embodiment of the present invention. FIG. 11A is a plan view of the device. FIG. 11B is FIG. 11A
FIG. 2 is a sectional view taken along line II of FIG. In each of these figures, 1
Reference numeral 0 denotes a TFT substrate, which includes a pixel electrode, a TFT, a storage capacitor,
TFT matrix part 1 composed of data lines and gate lines
1 is formed. Note that this TFT matrix section 1
As for 1, the same configuration as that already described as the first embodiment may be adopted. Therefore,
The duplicate description here is omitted. Reference numeral 20 denotes a counter substrate on which a common electrode facing each pixel electrode is formed. The TFT substrate 10 and the counter substrate 20 face each other with a certain gap therebetween, and a liquid crystal is sealed in the gap. 30 and 30 are gate drivers, 4
Are data drivers, each having 240 output terminals.

This active matrix type liquid crystal display device has 1920 pixels in the column direction and 48 pixels in the row direction.
This is a VGA-compatible liquid crystal display panel which is 0. Therefore, the TFT matrix section 11 has 960 data lines and 9
It has 60 gate lines. In order to drive 960 data lines, four data drivers 40 are externally provided on the TFT substrate 10. On the other hand, since there are 960 gate lines, four gate drivers 30 are originally required, but in the present embodiment, the demultiplexer unit 12 is provided on the TFT substrate 10 so that The number is halved to two. The demultiplexer section 12 is provided on the TFT substrate 10
The TFT and the signal wiring are formed thereon, and are formed simultaneously when the TFT matrix portion 11 is formed on the TFT substrate 10. Therefore, it is not necessary to add a new manufacturing process to form the demultiplexer unit 12 on the TFT substrate 10.

FIG. 12 shows a circuit configuration of the demultiplexer section 12. As shown in FIG. 12, the demultiplexer unit 12 includes an inverter 120 and 480 demultiplexers DMPX1 to DMPX480. Each demultiplexer has four TFTs.
Transfer gates 121 to 124.
A switching signal Vselect is supplied to each of the transfer gates 121 and 124 from a control circuit (not shown). A signal obtained by inverting the switching signal Vselect by the inverter 120 is supplied to each of the transfer gates 122 and 123.

Next, the operation of this embodiment will be described. In each field period, the demultiplexer DMPX1
480 output signals SR1 to SR480 obtained from the two gate drivers 30 in FIGS. 11A and 11B are sequentially supplied to the input terminals of 〜DMPX480. Also,
Each time the field cycle switches, the switching signal Vselect
The level of t is inverted. As a result, the following operation is performed in the demultiplexer unit 12. In the following example, each of the transfer gates 121 to 124 is configured by an n-channel TFT.

First, for example, assuming that the switching signal Vselect goes high in an odd-numbered field cycle, in each of the demultiplexers DMPX1 to DMPX480, the transfer gates 121 and 124 are turned on, and the transfer gates 122 and 123 are turned off. Therefore, output signals SR1 to SR1 sequentially output from the gate driver in the odd field period are set.
SR480 includes demultiplexers DMPX1 to DMPX.
480 via each transfer gate 121 of 480
It is sequentially applied to the first gate lines GA1 to GA480. During this time, the low-level reference voltage Vg-low is applied to the second gate lines GB1 to GB480 via the transfer gates 124 of the demultiplexers DMPX1 to DMPX480. Accordingly, during this time, all TFTs connected to the second gate line in the TFT matrix section 11 are turned off.

Next, assuming that the period is switched to the even-numbered field period and each switching signal Vselect becomes low level, in each of the demultiplexers DMPX1 to DMPX480, the transfer gates 122 and 123 are turned on, and the transfer gates 121 and 124 are turned off. Become. Therefore, output signals SR1 to SR1 sequentially output from the gate driver in this even field period are set.
SR480 includes demultiplexers DMPX1 to DMPX.
480 are sequentially applied to the second gate lines GB1 to GB480 via the transfer gates 123. During this time, the low-level reference voltage V is supplied to the first gate lines GA1 to GA480 via the transfer gates 122 of the demultiplexers DMPX1 to DMPX480.
g-low is applied.

As described above, the interlace for switching the supply destination of the output signal of the gate driver between the respective field periods is performed, such as the first gate line in the odd field period and the second gate line in the even field period. Therefore, the number of gate drivers can be reduced by half.

Third Embodiment FIGS. 13A and 13B show a configuration of an active matrix type liquid crystal display device according to a third embodiment of the present invention. FIG. 13A is a plan view of the device. FIG. 13B is FIG.
FIG. 2A is a sectional view taken along line II-II of FIG. In the above-described second embodiment, the number of the gate drivers 30 is reduced by half by forming the demultiplexer unit 12 on the TFT substrate 10. In the present embodiment, the demultiplexer unit 12
Instead of forming the shift register unit 13 on the TFT substrate 10, the external gate driver 30 is not required at all.

FIG. 14 shows a circuit configuration of the shift register section 13.
Shown in The shift register unit 13 also has a TFT similar to the demultiplexer unit 12 in the second embodiment.
It is formed at the same time when the TFT matrix portion 11 is formed on the substrate 10.

As shown in FIG. 14, the shift register unit 1
Reference numeral 3 denotes a cascade connection of 480 register units REG1 to REG480. These register units each include a first flip-flop including a transfer gate 131A, an inverter 132A, a transfer gate 133A, and an inverter 134A, and a transfer gate 131B, an inverter 132B, a transfer gate 133B, and an inverter 134B.
And a second flip-flop composed of The output terminal of the first flip-flop of each of the register units REG1 to REG480 (that is, the inverter 134A
Are connected to the first gate lines GA1 to GA480 of the TFT matrix unit 11, respectively. On the other hand, the output terminal of the second flip-flop of each of the register units REG1 to REG480 (that is, the output terminal of the inverter 134B) is connected to the second gate line GB of the TFT matrix unit 11.
1 to GB480.

Next, the operation of this embodiment will be described. The shift register unit 13 is supplied with two-phase clocks CK1 and CK2. Of these, the first phase clock CK1 is supplied to the transfer gate 13 of each register section.
1A and 131B and the second phase clock CK
2 is supplied to the transfer gates 133A and 133B of each register section.

In the odd-numbered field period, the start pulse SPA is supplied to the first flip-flop of the first-stage register unit REG1 at the start time.
Therefore, in the odd-numbered field period, the start pulse SPA sequentially shifts between the first flip-flops of the cascade-connected register units. As a result, the gate voltage corresponding to the start pulse SPA is sequentially output from the output terminal of the first flip-flop of each register unit (that is, the output terminal of the inverter 134A of each register unit), and the first gate lines GA1 to GA480 are output. Are sequentially applied. Note that in the odd field period, a shift operation is performed between the second flip-flops of each register unit, but a low-level signal is supplied to the second flip-flop of the first-stage register unit REG1. Therefore, in the odd field period, the second gate lines GB1 to GB1
GB480 is fixed at a low level.

Next, in the even field period, the start pulse SPB is supplied to the second flip-flop of the register unit REG1 of the first stage at the start time.
For this reason, in the even field period, the start pulse SPB is sequentially shifted between the second flip-flops of each register section. As a result, a gate voltage corresponding to the start pulse SPB is sequentially output from the output terminal of the second flip-flop of each register unit (that is, the output terminal of the inverter 134B of each register unit), and the second gate line G
B1 to GB480 are sequentially applied. Note that, in the even-numbered field period, a shift operation is performed between the first flip-flops of the register units, but a low-level signal is supplied to the first flip-flop of the first-stage register unit REG1. First gate lines GA1 to GA48
0 is fixed to a low level.

As described above, according to the present embodiment, TF
By the shift register unit 13 formed on the T substrate 10,
Since the first and second gate lines of the TFT matrix section 11 are interlaced, there is no need to provide an external gate driver, the number of components can be reduced, and the size and cost of the device can be reduced.

It should be noted that instead of providing the shift register section 13 having the above configuration, a 480-stage shift register and the demultiplexer section 12 in the second embodiment are used.
May be formed on the TFT substrate 10.
In this case, the same effect as in the third embodiment can be obtained.

The embodiments of the present invention have been described above. In each of the embodiments, for convenience of explanation, an active matrix liquid crystal display device in which data lines are arranged in a column arrangement direction (screen horizontal direction) and gate lines are arranged in a row arrangement direction (screen vertical direction). However, the relationship between the data lines and gate lines and the direction in which the rows and columns are arranged is not limited to this. The subject matter of the present invention lies in the layout of the data lines and the gate lines.

[0057]

As described above, according to the active matrix type liquid crystal display device of the present invention, the number of data lines is reduced to half that of the conventional one, so that the number of necessary data drivers is reduced and the price of the device is reduced. And the power consumption of the device can be reduced, and the demand for narrowing the pitch of the data wiring terminal portions does not become strict even when the display area is small.

[Brief description of the drawings]

FIG. 1 is a plan view showing a configuration of a substrate for an active matrix type liquid crystal display device which is a first basic configuration example of the present invention.

FIG. 2 is a plan view showing a configuration of a TFT portion (in the case of a large island structure) on the same substrate.

FIG. 3 is a plan view showing a configuration of a TFT portion (in the case of a large gate structure) of the substrate.

FIG. 4 is a plan view showing a configuration when a conventional general structure is applied to a TFT portion of the substrate.

FIG. 5 is a plan view showing a configuration of a substrate for an active matrix type liquid crystal display device which is a second basic configuration example of the present invention.

FIG. 6 is a plan view showing a configuration of a substrate for an active matrix type liquid crystal display device which is a third basic configuration example of the present invention.

FIG. 7 is a plan view showing a configuration of a substrate for an active matrix type liquid crystal display device which is a fourth basic configuration example of the present invention.

FIG. 8 shows a TFT of a substrate according to the second or third basic configuration example.
It is a top view which shows the structure of a part (in the case of a large island structure).

FIG. 9 shows a TFT on a substrate of the second or third basic configuration example.
It is a top view which shows the structure of a part (in the case of a large gate structure).

FIG. 10 is a plan view showing a configuration of an active matrix type liquid crystal display device substrate according to a first embodiment of the present invention.

11A and 11B are diagrams showing a configuration of an active matrix type liquid crystal display device according to a second embodiment of the present invention. FIG. 11A is a plan view of the device, and FIG. 11B is II in FIG. 13A.
FIG.

FIG. 12 is a circuit diagram showing a configuration of a demultiplexer unit according to the embodiment.

FIG. 13 is a diagram showing a configuration of an active matrix type liquid crystal display device according to a third embodiment of the present invention, FIG. 13A is a plan view of the device, and FIG. 13B is II-II in FIG. 13A.
FIG.

FIG. 14 is a circuit diagram illustrating a configuration of a shift register unit according to the embodiment.

FIG. 15 is a plan view showing a configuration of a conventional active matrix liquid crystal display device.

FIG. 16 is a view showing a procedure of scanning a gate line of the active matrix type liquid crystal display device.

[Explanation of symbols]

 PX (i, j) Pixel Dj Data line Gi Gate line 1 TFT 2 Liquid crystal capacitance 3 Storage capacitance 4, 5 Island 6 Pixel electrode 7 Drain electrode Cs Storage capacitance line

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-4-264529 (JP, A) JP-A-2-42420 (JP, A) JP-A-2-253232 (JP, A) JP-A-5-254 173167 (JP, A) JP-A-64-84297 (JP, A) JP-A-1-133124 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/1362 G02F 1 / 1343

Claims (7)

(57) [Claims] 1. A plurality of data lines and a plurality of gate lines are provided in a matrix on a substrate, and a thin film transistor and a pixel electrode connected to the thin film transistor are provided on both sides of each of the data lines on each of the plurality of gate lines. The plurality of gate lines are arranged so that pixel electrodes on both sides of the data line are controlled by a signal from one of the corresponding gate lines disposed between the pixel electrodes. A drain electrode that forms the thin film transistor and is electrically connected to the pixel electrode traverses the gate electrode, and a storage capacitor corresponding to each of the pixel electrodes.
Forming a data line between the adjacent data lines;
Not parallel to the data line in the boundary area between each pixel
A capacitor line is provided, and one storage capacitor line is provided for two pixel columns.
And one electrode of the storage capacitor is connected to the storage capacitor.
Connected to the pixel electrode corresponding to the product capacitance,
The other electrode of the storage capacitor is connected to the storage capacitor line
A substrate for an active matrix type liquid crystal display device, comprising: 2. A plurality of data lines and a plurality of gate lines are provided in a matrix on a substrate, and a thin film transistor and a pixel electrode connected to the thin film transistor are provided on both sides of each of the data lines on each of the plurality of gate lines. The plurality of gate lines are arranged so that pixel electrodes on both sides of the data line are controlled by a signal from one of the corresponding gate lines disposed between the pixel electrodes. A gate electrode forming the thin film transistor is constituted by the gate line itself, and a drain electrode forming the thin film transistor and electrically connected to the pixel electrode traverses the gate electrode and forms a pair with each of the pixel electrodes.
Accordingly, a storage capacitor is provided, and data between the adjacent data lines is provided.
The data is placed in the boundary area between pixels where no data line is formed.
A storage capacitor line is arranged in parallel with the
And the storage capacitor line is shared.
One electrode is connected to the pixel electrode corresponding to the storage capacitor
And the other electrode of the storage capacitor
A substrate for an active matrix liquid crystal display device, which is connected to a capacitance line . 3. An active matrix type liquid crystal display device in which liquid crystal is sandwiched between a pair of substrates arranged opposite to each other, wherein one substrate of the pair of substrates is the substrate according to claim 1 or 2. Active matrix type liquid crystal display device. 4. An adjacent data line having a reverse polarity.
The signal for each data line is applied so that the signal voltage is applied.
4. The actuator according to claim 3, wherein the voltage is output.
Active matrix type liquid crystal display device. 5. An operation for sequentially supplying a gate voltage to one of the gate lines disposed across the pixel each time the field cycle is switched, and an operation of sequentially supplying a gate voltage disposed between the pixel electrodes. 5. The active matrix liquid crystal display device according to claim 3 , further comprising a scanning unit that alternately repeats an operation of sequentially supplying a gate voltage to the other gate line. 6. A gate driver for sequentially outputting a gate voltage from an output terminal in each field period, and a gate voltage sequentially output from an output terminal of the gate driver for each of the field periods. And sequentially supplying the gate voltage sequentially output from the output terminal of the gate driver to the other one of the gate lines disposed across the pixel electrode. 5. An active matrix liquid crystal display device according to claim 3 , further comprising: a demultiplexer that alternately repeats an operation of sequentially supplying the demultiplexer and the pixel, wherein the demultiplexer and the pixel are manufactured by a common manufacturing process. . 7. A method of sequentially shifting a first start pulse,
A first shift register that supplies an output signal of each stage as a gate voltage to one of the gate lines disposed across the pixel electrode, sequentially shifts a second start pulse, and outputs the output of each stage. A second shift register that supplies a signal as a gate voltage to the other of the gate lines disposed across the pixel electrode, wherein the first and second shift registers and the pixel are manufactured in common. 5. The active matrix type liquid crystal display device according to claim 3 , wherein the active matrix type liquid crystal display device is manufactured by a process.