JP3564037B2

JP3564037B2 - Driving method of liquid crystal display panel and liquid crystal display panel

Info

Publication number: JP3564037B2
Application number: JP2000114207A
Authority: JP
Inventors: 尚人井上; 智彦山本; 恵一田中; 晃史藤原; 秀樹市岡; 康邦山根
Original assignee: Sharp Corp
Current assignee: Sharp Corp
Priority date: 2000-04-14
Filing date: 2000-04-14
Publication date: 2004-09-08
Anticipated expiration: 2020-04-14
Also published as: JP2001296518A

Description

【０００１】
【発明が属する技術分野】
本発明は、対向信号線構造の液晶表示パネルおよびその駆動方法に関する。
【０００２】
【従来の技術】
近年、ワードプロセッサ、パーソナルコンピュータ、テレビジョン装置等に備えられる表示素子として、行列状に配置される複数の画素を含む液晶表示パネルが多く用いられるようになってきている。
【０００３】
図８は、第１の従来技術であり、従来一般的に使用されている能動三端子素子であるＴＦＴ（ＴｈｉｎＦｉｌｍＴｒａｎｓｉｓｔｏｒ）６を用いる構造のアクティブマトリクス方式の液晶表示パネル１の構造模式図である。図９は、図８の液晶表示パネル１内の４画素分の部分の等価回路図である。図８と図９とを合わせて説明する。図８および図９に示す液晶表示パネルの構造を、以後「現行構造」と称す。画素２は、画素電極３と対向電極４との間に、液晶材料から形成される液晶層５が介在されて構成される。図８の液晶表示パネル１は、画素２の他に、第１基板、第２基板、画素２の総数と同数のＴＦＴ６、画素２の行数と同数の走査線７、画素２の列数と同数の信号線８、および基準線９を含む。なお図８および図９では第１基板と第２基板との図示が省略され、さらに図８では液晶材料の図示が省略されている。
【０００４】
第１基板上には、全画素２の画素電極３、全ＴＦＴ６、全走査線７、および全信号線８が配置される。各画素電極３は、各ＴＦＴ６のドレイン電極に個別接続される。走査線７は、画素２の行毎に、１行分の画素２の画素電極３にそれぞれ接続されるＴＦＴ６のゲート電極に接続される。信号線８は、画素２の列毎に、１列分の画素２の画素電極３にそれぞれ接続されるＴＦＴ６のソース電極に接続される。第２基板上には、一面ベタ電極１１が配置されている。一面ベタ電極１１は、全画素２の対向電極４と該対向電極４に接続すべき基準線９とが一体化されたものである。全画素２の液晶層５を形成する液晶材料は、第１基板と第２基板との間に封入される。図８の液晶表示パネル１において、走査線７と画素電極３との間に、補助容量が設けられていることもよくある。
【０００５】
図８では、信号線８の本数はＭ本であり、走査線７の本数は２Ｎ本になっている。Ｍ，Ｎは自然数である。実際の液晶表示パネルにおける信号線８の本数および走査線７の本数は、商品によって異なる。以後の説明では、複数備えられる１種類の構成部品のうちの特定の１つを示す場合、該構成部品を示す参照符に、該特定の１つの構成部品の配列順を示す添字を付して示す。なお本明細書では、ｎは１以上Ｎ以下の任意整数であり、ｋは１以上２Ｎ以下の任意整数であり、ｍは１以上Ｍ以下の任意整数である。
【０００６】
液晶表示パネル１を形成するには、まず、ガラス等で実現されて透光性を有する第１基板および第２基板上に金属および半導体等の薄膜がそれぞれ成膜され、該各薄膜がフォトリソグラフィによって各基板上に配置されるべき部品形状にそれぞれパターニングされる。次いで、第１基板および第２基板が互いの部品形成面を向かい合わせかつ所定の間隙を保った状態で貼合わされ、２枚の基板間の間隙に液晶材料が封入される。これによって液晶表示パネル１が完成する。
【０００７】
図８の液晶表示パネル１の駆動方法としては、所謂１Ｈライン反転駆動法が一般的によく使用される。図８の液晶表示パネル１の画素２の液晶層５内の電界制御のために、図１０のチャート図に基づき該液晶表示パネル１が駆動される場合を例として、従来技術の１Ｈライン反転駆動法を以下に説明する。図１０（Ａ）〜図１０（Ｃ）は、上記場合において、走査線７に印加される走査線駆動電圧、信号線８に印加される信号線駆動電圧、および基準線９に印加される基準線駆動電圧の時間変化をそれぞれ示すチャート図である。
【０００８】
各走査線７に個別に印加される走査線駆動電圧は、各走査線７に接続されている能動三端子素子のオン状態とオフ状態との切換えを制御する。走査線駆動電圧は、走査線１本おきに切換えられても良い。仮に、液晶表示パネル１の表示面側から見て画素２が上から下に走査される場合では、まず最上部にある１行目の走査線７〔１〕の走査線駆動電圧が、所定の走査時間である１Ｈ時間だけ、ＴＦＴ６をオン状態にするためのオン電圧に保たれる。１行目の走査線７〔１〕の走査線駆動電圧がＴＦＴ６をオフ状態にするためのオフ電圧に戻されると、次に２行目の走査線７〔２〕の走査線駆動電圧が、１Ｈ時間だけオン電圧に保たれる。このような走査線駆動電圧の印加を走査線７毎に順次繰返し行い、１番下にある２Ｎ行目の走査線７〔２Ｎ〕の走査線駆動電圧がオフ電圧になった段階で、液晶表示パネル１の全画素２に対する１フレーム分の走査が完了する。
【０００９】
任意の１本の走査線７の走査線駆動電圧がオン電圧からオフ電圧に変わる時点において、ＴＦＴ６を介して該走査線７に接続されている画素電極３を含む画素２には、該画素電極３に該ＴＦＴ６を介して接続されている信号線８に印加中の信号線駆動電圧と対向電極４に印加中の基準面電圧との電圧差に応じた電荷が充電される。図８の液晶表示パネル１では、対向電極４に印加されている基準面電圧は、基準線駆動電圧と等しい。充電された電荷を走査線駆動電圧がオフ電圧である間に各画素２が保ち続けることによって、該各画素２の液晶層５内に各画素２の所望の表示状態に応じた電界が保持されるので、液晶表示パネル１に１フレーム分の画像が表示される。
【００１０】
１フレーム目の走査完了後からやがてしばらくすると、１フレーム目の走査と同じ順序で、全ての画素２に対し上から下に向かって２フレーム目の走査が実行される。従来の一般的な液晶表示パネルは、１秒間に約５５フレーム以上８５フレーム以下のフレームを表示するように駆動される。最も一般的な液晶表示パネルは、１秒間に６０フレームを表示する。なお図８の液晶表示パネル１が図１０のチャート図に基づいて駆動されるにあたり、走査線駆動電圧のオフ電圧が２通り設定されていて、走査線駆動電圧がオフ電圧を保つべき期間内に基準面電圧と同期してオフ電圧が変動していることもある。
【００１１】
上記のように走査される各画素２にどのような極性で電圧が印加されるかについて、液晶表示パネル１の全画素２に所定の上限電圧を印加する場合を例として、以下にさらに詳細を説明する。先ず１行目の走査線７〔１〕の走査線駆動電圧だけがオン電圧を維持する間、全ての各信号線８〔１〕〜８〔Ｍ〕の信号線駆動電圧はハイレベルを取り、一面ベタ電極１１の基準面電圧はローレベルを取る。このとき１行目の走査線７〔１〕と各信号線８〔１〕〜８〔２Ｎ〕との交点にある各ＴＦＴ６〔１，１〕〜６〔１，Ｍ〕のスイッチングによって、該各ＴＦＴに接続されている画素電極３〔１，１〕〜３〔１，Ｍ〕を含む画素２に電荷が充電される。１行目の各画素２〔１，ｍ〕に充電される電荷の極性は、対向電極４〔１，ｍ〕から各画素電極３〔１，ｍ〕を見ると、プラスの極性になっている。
【００１２】
次に２行目の走査線７〔２〕の走査線駆動電圧だけがオン電圧を維持する間、各信号線８〔１〕〜８〔Ｍ〕の信号線駆動電圧および一面ベタ電極１１の基準面電圧の両方が、１行目の走査線７〔１〕駆動時の信号線駆動電圧および基準面電圧の逆極性にそれぞれ変化する。ゆえに各信号線８〔１〕〜８〔Ｍ〕の信号線駆動電圧はローレベルを取り、基準面電圧はハイレベルを取る。このとき２行目の走査線７〔２〕と各信号線８〔１〕〜８〔Ｍ〕との交点にあるＴＦＴ６〔２，１〕〜６〔２，Ｍ〕のスイッチングによって、該各ＴＦＴに接続されている画素電極３〔２，１〕〜３〔２，Ｍ〕を含む画素２〔２，１〕〜２〔２，Ｍ〕に電荷が充電される。２行目の画素２〔２，ｍ〕に充電される電荷の極性は、対向電極４〔２，ｍ〕から画素電極３〔２，ｍ〕を見ると、マイナスの極性になっている。
【００１３】
３行目の走査線７〔３〕以後の各走査線の走査時にも、上述の１行目および２行目の走査線７〔１〕，７〔２〕の走査時と同様に、走査線１本おきに交互に逆極性になる信号線駆動電圧および基準面電圧に応じて、画素２へ電荷が充電される。図１１（Ａ）に示す１フレーム目の走査完了時での画素２の充電電荷の極性と、図１１（Ｂ）に示す２フレーム目の走査完了時での画素２の充電電荷の極性とを比較すると、両者は画素毎に相互に逆極性になっている。さらに３フレーム目の走査完了時の画素の電荷充電状態は１フレーム目と同じになり、４フレーム目の走査完了時の画素の電荷充電状態は２フレーム目と同じになる。このように、図８の液晶表示パネル１の任意の１つの特定画素２に着目すると、該特定画素２〔ｋ，ｍ〕の充電電荷の極性がフレーム毎に逆転するように、画素電極３〔ｋ，ｍ〕と対向電極４〔ｋ，ｍ〕との間の電圧が印加されている。かつ任意の１フレームにおいて、前記特定画素２〔ｋ，ｍ〕の充電電荷の極性は、前記特定画素の属す行よりも１行上および１行下の画素２〔ｋ−１，ｍ〕，２〔ｋ＋１，ｍ〕の充電電荷の極性の逆極性になっている。
【００１４】
次に、特開平３−６３６２３公報に示される液晶表示パネルについて説明する。図１２は、特開平３−６３６２３公報記載のアクティブマトリクス方式の液晶表示パネル１３の構造模式図である。図１３は図１２の液晶表示パネル１３内の４画素分の部分の等価回路図である。図１２の液晶表示パネル１３の構成部品のうち、図８の液晶表示パネル１の構成部品と機能が等しい部品には同じ参照符を付し、詳細説明は省略する。
【００１５】
図１２の液晶表示パネル１３の構成のうち、図８の液晶表示パネル１の構成と異なる部分は以下のとおりである。図１２の液晶表示パネル１３では、図８の一面ベタ電極１１に代わって、奇数基準電極１４および偶数基準電極１５が第２基板上に配置されている。奇数基準電極１４および偶数基準電極１５は、１面ベタ電極１１を２系統の略帯状の電極片に分割形成したものである。奇数基準電極１４は、奇数行の走査線７〔２ｎ−１〕にＴＦＴを介して接続されている画素電極に対向する対向電極４〔２ｎ−１〕と該対向電極に接続される基準線９〔２ｎ−１〕とを一体化したものである。偶数基準電極１５は、偶数行の走査線７〔２ｎ〕にＴＦＴを介して接続されている画素電極に対向する対向電極４〔２ｎ〕と該対向電極に接続される基準線９〔２ｎ〕とを一体化したものである。図１３の等価回路図に示すように、奇数基準電極１４と偶数基準電極１５とは相互に全く独立しているので、チャージ電位の歪みを独立して別々に補正させるために、奇数基準電極１４と偶数基準電極１５とそれぞれ異なる電圧を印加することが可能である。
【００１６】
次に、特開昭６１−２１５５９０公報に記載されている対向信号線構造の液晶表示パネルとその駆動方法について説明する。図１４は、能動三端子素子としてＴＦＴを用いる対向信号線構造のアクティブマトリクス方式の液晶表示パネル１７の構造模式図を示す。図１４の液晶表示パネル１７の構成部品のうち、図８の液晶表示パネル１の構成部品と機能が等しい部品には同じ参照符を付し、詳細説明は省略する。図１４の液晶表示パネル１７は、画素２の他に、第１基板、第２基板、画素２の総数と同数のＴＦＴ６、画素２の行数と同数の走査線７、画素２の列数と同数の信号線８、および基準線９を含む。なお図１４では第１基板と第２基板と液晶材料との図示は省略している。
【００１７】
第１基板上には、全画素２の画素電極３と全ＴＦＴ６と全基準線９と全走査線７とが配置される。第２基板上には、画素２の列数と同数の信号電極１８が並行配置されている。ｍ列目の全画素の画素電極３〔１，ｍ〕〜〔２Ｎ，ｍ〕に対向する信号電極１８〔ｍ〕は、ｍ列目の画素列に並行配置されるべき信号線８〔ｍ〕と、ｍ列目の全画素の対向電極４〔１，ｍ〕〜〔２Ｎ，ｍ〕とを一体化したものである。全画素２の液晶層５を形成する液晶材料は、第１基板と第２基板との間に封入される。図１４では信号線８の本数はＭ本であり走査線７の本数は２Ｎ本になっているが、実際の液晶表示パネル１７の各線数は商品によって異なる。
【００１８】
図１４の対向信号線構造の液晶表示パネル１７における１Ｈライン反転駆動法は、図８の現行構造の液晶表示パネル１における１Ｈライン反転駆動法と比較して、画素２への電荷充電機構が逆方向になり、かつ一部フリッカを消すための技術を必要とする点が異なり、各画素２への電圧印加方法等の残余部分は基本的には図８の液晶表示パネルの１Ｈライン反転駆動法とほぼ等しい。図８の液晶表示パネル１の充電機構では、任意の画素２〔ｋ，ｍ〕に充電されるべき電荷は、ｍ行目の信号線８〔ｍ〕からＴＦＴ６〔ｋ，ｍ〕と画素電極３〔ｋ，ｍ〕と液晶層５〔ｋ，ｍ〕とをこの順に経由して基準線９に接続されている対向電極４〔ｋ，ｍ〕に至るのに対して、図１４の液晶表示パネル１７の充電機構では、任意画素２〔ｋ，ｍ〕に充電されるべき電荷は、信号線と対向電極とを兼ねるｍ行目の信号電極１８〔ｍ〕から液晶層５〔ｋ，ｍ〕と画素電極３〔ｋ，ｍ〕とＴＦＴ６〔ｋ，ｍ〕とをこの順に経由して基準線９に至る。
【００１９】
このように回路駆動の観点から見ると、図１４の対向信号線構造の液晶表示パネル１７の１Ｈライン反転駆動法は、図８の現行構造の液晶表示パネル１の１Ｈライン反転駆動法と大まかには同じであり、すなわち図１０のチャート図を用いて説明した駆動方法と等しい。なお図８の液晶表示パネル１の駆動方法と図１４の液晶表示パネル１７の駆動方法とでは、基準面電圧の平均値電圧設定が異なるが、本発明では問題としない。
【００２０】
【発明が解決しようとする課題】
能動三端子素子を用いる液晶表示パネルについて、発明が解決しようとしている課題を説明する。１Ｈライン反転駆動法では、電荷を充電すべき画素が接続されている走査線である走査対象の走査線７が１本次に進むたびに、電荷充電時の基準電圧である基準面電圧の極性が必ず反転される。このために、基準面電圧の時間変化を示す波形は、所定の走査時間である１Ｈ時間毎に電圧が変化する矩形波になっている。基準面電圧を規定する基準線駆動電圧が印加される基準線９には抵抗負荷と容量負荷とが必ず存在するので、矩形波または短形波に近い波形の基準線駆動電圧を基準線９に印加しても、実際に基準線９から実際に取出される基準面電圧の波形は配線遅延を含む鈍った波形になる。このような鈍った波形の基準面電圧を基準として信号線駆動電圧の極性が反転されるならば、極性が反転するたびに電荷充電に係る電流とは逆方向の電流が流れて電力を消費する。しかも基準面電圧は全画素２に対する極性反転の基準電圧になっているので、極性反転時の消費電力が非常に大きくなる。極性反転時の消費電力に関する問題に対しての対策が従来何点か考えられているが、根本解決には至っていない。以下に、従来の対策を説明する。
【００２１】
１つ目の対策としては、１Ｈライン反転駆動法に代わって、液晶表示パネルの他の駆動方法の１つであるドット反転駆動法が採用される。ドット反転駆動法は、図８の液晶表示パネル１のような、ＴＦＴを用いる現行構造の液晶表示パネルにおいて、よく利用されている。ドット反転駆動法では、基準面電圧を一定の直流電圧に保ちつつ、該基準面電圧よりも極性がプラスの電圧と該基準面電圧よりも極性がマイナスの電圧との両方に大きく変動するような信号線駆動電圧を信号線８に印加することによって、画素２内の液晶を交流駆動する。ドット反転駆動法では、基準面電圧が所定値を常に保つために、基準面電圧の変動に起因する電流は殆ど流れず、該基準面電圧が印加される回路部分での消費電力は非常に小さい。ところがドット反転駆動法における信号線駆動電圧の変動幅は１Ｈライン反転駆動法における信号線駆動電圧の変動幅の２倍になるので、ドット反転駆動法の信号線駆動電圧が印加される回路部分での消費電力が、１Ｈライン反転駆動法の信号線駆動電圧が印加される回路部分での消費電力の約２倍に跳上がる。このためにドット反転駆動法が用いられる場合、液晶表示パネル全体の消費電力が総合的に低下されるとは言難い。
【００２２】
２つ目の対策としては、液晶表示パネルの構造は図８の構成のまま保たれ、駆動方法の詳細が変えられる。たとえば１Ｈライン反転駆動法では、走査対象の走査線７が１本進むたびに画素充電の極性が反転するように信号線駆動電圧および基準面電圧の極性が反転されているが、２つ目の対策時には、画素充電の極性の反転回数が減らされる。具体的には、所謂２Ｈライン反転駆動法のように、走査対象の走査線７が２本進むたびに画素充電の極性が反転するように、信号線駆動電圧および基準面電圧が制御される。これによって２Ｈライン反転駆動法使用中の極性反転時に逆極性の電荷を画素に充電しようとして流れる電流は、単位時間あたりには１Ｈライン反転駆動法使用中に極性反転時に流れる電流の半分となる。つまりパルスの発生回数が半分になるので、パルスの変わり目に流れる電流の回数も半分になる。これによって、２Ｈライン反転駆動法使用時に基準面電圧が印加される回路部分での消費電力は、１Ｈライン反転駆動法使用時に基準面電圧が印加される回路部分での消費電力の約半分となる。
【００２３】
ところが２Ｈライン反転駆動法が用いられる状況下では、根本的な表示品位低下が発生する。表示品位の低下は、信号線駆動電圧および基準面電圧の極性反転直後に充電される画素２への充電量が該極性反転時から走査線１本分の走査が進んだ後に充電される画素２への充電量と異なることに起因する。一般的には、たとえば液晶表示パネルの画面に一面の黒ベタ画像が表示される場合、すなわち全画素２に上限電圧が印加されている場合、極性反転直後に走査される走査線７に接続されている画素２から成る行は色の薄い黒となり、極性反転後にさらに１走査線分走査が進んだ後に充電される画素２からなる行は色の濃い黒となる。また充電量の不均一をキャンセルしようとして、次フレームでの走査方向を前フレームと逆にしても、本質的に濃淡を持った画像がフレーム毎に逆方向に描かれるために、フリッカが発生してしまう。２つめの対策に関する問題は、信号線駆動電圧および基準面電圧の極性反転のタイミングを走査線２本おきから走査線４本おきにしても解決されない。さらに１フレーム分の走査時に全画素２に相互に同極性の電荷を描込み、次のフレーム分の走査時には前フレームの電荷書込み時の極性とは逆極性の電荷を書込む場合、面全体のフリッカを発生させるので、問題は解決されない。
【００２４】
３つ目の対策としては、特開平３−６３６２３公報および図１２に示すように、液晶表示パネルの構造自体を変化させる。具体的には、画素電極３に対向する対向電極４が２系統に区分されて各系統に独立して信号を入力可能なように形成され、各系統の対向電極４に系統毎に異なる電圧が印加される。これによって、見かけ上１Ｈライン反転駆動法を維持したまま、基準面電圧波形の周波数が元の１Ｈライン反転駆動方式の基準面電圧波形の周波数の約走査線数分の１まで低くなる。この結果基準面電圧の波形が、図８〜図１０で説明した元の１Ｈライン反転駆動法では１走査時間毎に変化しているが、図１２で説明した駆動方式では１フレーム時間毎に１回変化するようになるので、消費電力が大幅に低減される。
【００２５】
ところが、２系統に区分された対向電極４を有する構造を液晶表示パネルを作成するためには、現行構造の液晶表示パネル１の現行の製造プロセスに、新たなパターニング工程を１回追加する必要がある。図１５は、図８の液晶表示パネル１の概略的な製造プロセスを示す工程図である。図８の液晶表示パネル１の製造工程では、第２基板上の部品形成プロセスは１回のデポ工程だけで済んでいるが、対向電極４を２系統にパターニングするためには、上記のデポ工程に加えて、１回のフォト工程と１回のエッチング工程を必要とするので、結果として液晶表示パネルの製造コストを大きく跳上げてしまう。
【００２６】
本発明の目的は、製造コストを増加させることなくかつ表示品位を確保したまま消費電力を低減させ、しかも能動三端子素子のソース電極が接続される基準線の配線遅延を解消する液晶表示パネルの駆動方法および液晶表示パネルを提供することである。
【００２７】
【課題を解決するための手段】
本発明は、第１基板上の表示領域４２に、液晶層が画素電極と対向電極との間に介在されてそれぞれ構成されていてかつ行列状に配置される複数の画素、
ゲート電極とソース電極と画素電極に接続されるドレイン電極とをそれぞれ有する複数の能動三端子素子３６、
行毎に１行分の画素の画素電極に接続される能動三端子素子のゲート電極が接続される走査線３７、および
行毎に１行分の画素の画素電極に接続される能動三端子素子のソース電極が接続される基準線３９が配置され、
第２基板上に、列毎に１列分の画素の対向電極が接続される信号線３８が配置され、
第１基板と第２基板との間に液晶が介在される液晶表示パネルの駆動方法であって、
全基準線が第１および第２の２系統の配線群に区分され、
第１基板上の表示領域４２外の周辺領域４３には、
第１の配線群の基準線の長手方向一端部が伸延されて第１の接続用幹線４４ odd に接続され、
第２配線群の基準線の長手方向他端部が伸延されて、第２の接続用幹線４４ even に接続され、
第１および第２の各接続用幹線４４ odd, ４４ even は、基準線３９よりも太い線幅を有し、周辺領域４３内の基準線幅方向両端部にも延びる端部分を有し、
前記周辺領域４３には、
前記第１の配線群の基準線の長手方向他端部が伸延された第１伸延部と、第２の接続用幹線４４ even の前記端部分との上に、第１絶縁層を介して、第１の補助幹線４５ odd が設けられ、第１の補助幹線４５ odd は、第１絶縁層に設けられたコンタクトホールを介して、第１伸延部と第１接続用幹線４４ odd の前記端部分とに直接接続され、
前記周辺領域４３にはまた、
前記第２の配線群の基準線の長手方向一端部が伸延された第２伸延部と、第１の接続用幹線４４ odd の前記端部分との上に、第２絶縁層を介して、第２の補助幹線４５ even が設けられ、第２の補助幹線４５ even は、第２絶縁層に設けられたコンタクトホールを介して、第２伸延部と第２接続用幹線４４ even の前記端部分とに直接接続され、
予め定めるフレーム時間毎に予め定める走査時間だけ能動三端子素子をオン状態にさせる走査線駆動電圧が各走査線にそれぞれ印加され、かつ、極性が走査時間と同周期で変化する信号線駆動電圧が各信号線にそれぞれ印加され、
配線群毎に個別に予め定められている基準線駆動電圧が各配線群に属する全基準線にそれぞれ印加され、
各配線群に属する基準線にそれぞれ印加される基準線駆動電圧が相互に異なりかつ１フレーム時間と同周期で極性反転して変化することを特徴とする液晶表示パネルの駆動方法である。
【００２８】
本発明に従えば、所謂対向信号線構造を有する液晶表示パネルの駆動方法において、複数の基準線が２の配線群に分けられており、かつ各配線群に属する基準線に、配線群毎に異なる基準線駆動電圧が印加される。この結果、基準線駆動電圧に対する信号線駆動電圧の極性を走査時間と同周期で変化すべき場合、信号線駆動電圧の極性だけを走査時間周期で変化させるだけで良く、基準線駆動電圧の極性を走査時間周期で変化させる必要がなくなる。これによって、液晶表示パネルの表示品位を損なうことなく、かつ液晶表示パネルの製造プロセス数を増加させることなく、液晶表示パネルの消費電力を大幅に低減させることができる。
【００３０】
本発明に従えば、２系統の各配線群に属す基準線が１本ずつ交互に配置されている構造の液晶表示パネルの駆動方法において、奇数行の基準線に印加される基準線駆動電圧の極性が、偶数行の基準線に印加される基準線駆動電圧の極性の逆極性になっている。この結果、液晶表示パネルは所謂１Ｈライン反転駆動法と等価な方法で駆動されるので、隣合う２行の画素の充電電荷の極性を相互反転すべき場合、信号線駆動電圧の極性だけを走査時間周期で反転させるだけで良く、基準線駆動電圧の極性を走査時間周期で反転させる必要がなくなる。これによって、表示品位の低下および製造プロセス数の増加を防止しつつ液晶表示パネルの消費電力が低減されるだけでなく、液晶表示パネルの駆動回路のコストの低減が可能になる。
【００３２】
本発明に従えば、液晶表示パネルの駆動方法において、各配線群に属する基準線に印加されるべき基準線駆動電圧の極性がフレーム時間と同周期で逆転するので、連続する２つの各フレームにおいて任意の１画素の充電電荷の極性が相互に逆転する。これによって、表示品位の低下および製造プロセス数の増加を防止しつつ液晶表示パネルの消費電力が低減されるだけでなく、液晶表示パネルの表示の信頼性が向上する。
【００３３】
また本発明は、表示領域４２と、この表示領域４２外の周辺領域４３とを有する第１基板と、
この第１基板との間に液晶を介在する第２基板とを含み、
第１基板上の表示領域４２には、
液晶層が画素電極と対向電極との間に介在されてそれぞれ構成されていてかつ行列状に配置される複数の画素、
ゲート電極とソース電極と画素電極に接続されるドレイン電極とをそれぞれ有する複数の能動三端子素子３６、
行毎に１行分の画素の画素電極に接続される能動三端子素子のゲート電極が接続される走査線３７、および
行毎に１行分の画素の画素電極に接続される能動三端子素子のソース電極が接続される基準線３９が配置され、
第２基板上に、列毎に１列分の画素の対向電極が接続される信号線３８が配置され、
全基準線が第１および第２の２系統の配線群に区分され、
第１基板上の表示領域４２外の周辺領域４３には、
第１の配線群の基準線の長手方向一端部が伸延されて第１の接続用幹線４４ odd に接続され、
第２配線群の基準線の長手方向他端部が伸延されて、第２の接続用幹線４４ even に接続され、
第１および第２の各接続用幹線４４ odd, ４４ even は、基準線３９よりも太い線幅を有し、周辺領域４３内の基準線幅方向両端部にも延びる端部分を有し、
前記周辺領域４３には、
前記第１の配線群の基準線の長手方向他端部が伸延された第１伸延部と、第１の接続用幹線４４ odd の前記端部分との上に、第１絶縁層を介して、第１の補助幹線４５ odd が設けられ、第１の補助幹線４５ odd は、第１絶縁層に設けられたコンタクトホールを介して、第１伸延部と第１接続用幹線４４ odd の前記端部分とに直接接続され、
前記周辺領域４３にはまた、
前記第２の配線群の基準線の長手方向一端部が伸延された第２伸延部と、第２の接続用幹線４４ even の前記端部分との上に、第２絶縁層を介して、第２の補助幹線４５ even が設けられ、第２の補助幹線４５ even は、第２絶縁層に設けられたコンタクトホールを介して、第２伸延部と第２接続用幹線４４ even の前記端部分とに直接接続され、
予め定めるフレーム時間毎に予め定める走査時間だけ能動三端子素子をオン状態にさせる走査線駆動電圧が各走査線にそれぞれ印加され、かつ、極性が走査時間と同周期で変化する信号線駆動電圧が各信号線にそれぞれ印加され、
配線群毎に個別に予め定められている基準線駆動電圧が各配線群に属する全基準線にそれぞれ印加され、
各配線群に属する基準線にそれぞれ印加される基準線駆動電圧が相互に異なりかつ１フレーム時間と同周期で極性反転して変化して与えることを特徴とする液晶表示パネルである。
【００３４】
本発明に従えば、所謂対向信号線構造の液晶表示パネルにおいて、各基準線が２の配線群のうちのいずれか１つの配線群に属し、かつ配線群毎に、単一配線群に属す全基準線が相互接続されている。これによって、全基準線が２の系統に分割されるので、配線群毎に異なる基準線駆動電圧を配線群に属す基準線に印加することが容易に可能になる。またこれによって、基準線駆動電圧の配線遅延が防止されるので、液晶表示パネルの大型化および高精細化が容易になる。
【００３６】
本発明に従えば、所謂対向信号線構造の液晶表示パネルにおいて、配線群が２系統ある場合、画素の行と平行に、２つの各配線群に属す基準線が１本ずつ交互に配置されていて、かつ配線群毎に基準線が相互接続されている。これによって、奇数行の画素の能動三端子素子に接続される基準線と、偶数行の画素の能動三端子素子に接続される基準線とに、相互に異なる基準線駆動電圧を印加することが容易に可能になる。
【００３７】
【発明の実施の形態】
図１は、本発明の実施の一形態である液晶表示パネル３１の概略構造を示す模式図である。図２は、図１の液晶表示パネル３１内の４画素分の部分の等価回路図である。図３は、図１の液晶表示パネル３１の詳細構成を示す分解斜視図である。図１〜図３を併せて説明する。図１の液晶表示パネル３１は、いわゆる対向信号線構造のアクティブマトリクス型の液晶表示パネルである。
【００３８】
液晶表示パネル３１は、概略的には、複数の画素３２、画素３２と同数の能動三端子素子３６、画素３２の行数と同数の走査線３７、画素３２の行数と同数の基準線３９、および画素３２の列数と同数の信号線３８を最低減含む。各画素３２は、液晶材料から形成される液晶層３５と、液晶層３５を挟んで対向配置される画素電極３３および対向電極３４とをそれぞれ含む。各能動三端子素子３６は、ゲート電極とソース電極とドレイン電極とをそれぞれ有する。全画素３２は、行列状に平面配置されている。走査線３７および基準線３９は、画素３２の行にそれぞれ個別対応している。信号線３８は画素３２の列に個別対応している。能動三端子素子３６は、画素３２に個別対応している。
【００３９】
本実施の形態では、信号線３８の本数はＭ本であり、走査線３７の本数は２Ｎ本になっている。Ｍ，Ｎは自然数である。実際の液晶表示パネル３１における信号線３８の本数および走査線３７の本数は、商品によって異なる。本実施の形態の以後の説明では、複数備えられる１種類の構成部品のうちの特定の１つを示す場合、該構成部品を総称する参照符に該特定の１つの構成部品の配列順を示す添字を付して示す。なお本明細書では、ｎは１以上Ｎ以下の任意整数であり、ｋは１以上２Ｎ以下の任意整数であり、ｍは１以上Ｍ以下の任意整数である。
【００４０】
画素３２〔ｋ，ｍ〕の画素電極３３〔ｋ，ｍ〕は、該画素に対応する能動三端子素子３６〔ｋ，ｍ〕のドレイン電極に個別接続される。第ｋ行に属す画素に個別対応する能動三端子素子３６〔ｋ，１〕〜３６〔ｋ，Ｍ〕のゲート電極は、第ｋ行に対応する走査線３７〔ｋ〕に接続される。第ｋ行に属す全画素に個別対応する能動三端子素子３６〔ｋ，１〕〜３６〔ｋ，Ｍ〕のソース電極は、第ｋ行に対応する基準線３９〔ｋ〕に接続される。第ｍ列に属す全画素の対向電極３４〔１，ｍ〕〜３４〔２Ｎ，ｍ〕は、第ｍ列に対応する信号線３８〔ｍ〕に接続される。なお図１〜図３の例では、能動三端子素子３６としてＴＦＴが用いられており、かつ列毎に、１列分の全画素の対向電極３４〔１，ｍ〕〜３４〔２Ｎ，ｍ〕と該列に対応する信号線３８〔ｍ〕とが一体化されて、略帯状の信号電極４０〔ｍ〕になっている。
【００４１】
図１の液晶表示パネル３１において、全基準線３９〔１〕〜３９〔２Ｎ〕は２系統の配線群に区分されており、かつ配線群毎に、配線群に属する全基準線３９同士が相互接続されている。これによって全基準線３９〔１〕〜３９〔２Ｎ〕が２の系統に分割されるので、配線群毎に異なる基準線駆動電圧を配線群に属す基準線３９に印加することが容易に可能になる。またこれによって基準線駆動電圧の配線遅延が防止されるので、液晶表示パネル３１の大型化および高精細化が容易になる。
【００４２】
図１〜図３の例では、全基準線３９〔１〕〜３９〔２Ｎ〕は２系統の配線群に区分され、２つの各配線群に属す基準線３９が画素３２の行と平行に１本ずつ交互に配置される。すなわち全基準線３９は、奇数行の画素３２〔２ｎ−１，ｍ〕に対応する能動三端子素子３６〔２ｎ−１，ｍ〕に接続される基準線３９〔２ｎ−１〕から成る配線群と、偶数行の画素３２〔２ｎ，ｍ〕の能動三端子素子３６〔２ｎ，ｍ〕に接続される基準線３９〔２ｎ〕から成る配線群とに区分されるので、基準線３９が１本おきに相互接続される。これによって、奇数行目の基準線３９〔２ｎ−１〕と偶数行目の基準線３９〔２ｎ〕とに、相互に異なる基準線駆動電圧を印加することが容易になる。
【００４３】
能動三端子素子３６としてＴＦＴを用いる本実施の形態の液晶表示パネル３１の詳細構成を、図１〜図３に基づいて説明する。液晶表示パネル３１は、画素３２と能動三端子素子３６と走査線３７と基準線３９と信号線３８の他に、図示しない第１基板および第２基板をさらに含む。全画素３２の画素電極３３は、第１基板上に行列配置される。ｋ行目の基準線３９〔ｋ〕は、第１基板上において、ｋ行目の全画素の画素電極３３〔ｋ，１〕〜３３〔ｋ，Ｍ〕の近傍に、該任意行に平行に配置される。ｋ行目の走査線３７〔ｋ〕は、第１基板上において、第ｋ行の画素の画素電極３３〔ｋ，１〕〜３３〔ｋ，Ｍ〕とｋ行目の基準線３９〔ｋ〕との間に配置される。全画素３２の液晶層３５をそれぞれ構成する液晶材料は、第１基板と第２基板との間に封入される。各信号電極４０〔ｍ〕は、第２基板上に配置され、かつ基板間の液晶材料層を介して各列の全画素電極３３〔１，ｍ〕〜〔２Ｎ，ｍ〕と対向する。
【００４４】
各画素３２〔ｋ，ｍ〕の画素電極３３〔ｋ，ｍ〕は、各画素に個別対応する能動三端子素子３６〔ｋ，ｍ〕のドレイン電極に、個別接続される。第ｋ行の各画素に対応する能動三端子素子３６〔ｋ，１〕〜３６〔ｋ，Ｍ〕のゲート電極は、ｋ行目の走査線３７〔ｋ〕に接続される。第ｋ行の各画素に対応する能動三端子素子３６〔ｋ，１〕〜３６〔ｋ，Ｍ〕のソース電極は、ｋ行目の基準線３９〔ｋ〕に接続される。全基準線３９〔１〕〜３９〔２Ｎ〕のうちの奇数行目の基準線３９〔１〕，３９〔３〕，…，３９〔２Ｎ−１〕から成る奇数行配線群と、全基準線３９〔１〕〜３９〔２Ｎ〕のうちの偶数行目の基準線３９〔２〕，３９〔４〕，…，３９〔２Ｎ〕から成る偶数行配線群とが、配線群毎にそれぞれ別々に束ねられる。配線群毎にそれぞれ束ねられた基準線３９は、配線群毎に別々に独立して電圧が印加可能になるように、第１基板の表面上の画素電極３３が配列されている表示領域４２の外部に引出される。
【００４５】
図４は、図１〜図３の液晶表示パネル３１内の基準線３９の具体的構成の１例を示す平面図である。全基準線３９〔１〕〜３９〔２Ｎ〕は、第１基板の表面上の表示領域４２内に、相互に平行に配置されている。第１基板の表面上の表示領域４２外の周辺領域４３には、配線群毎に、配線群に属する全基準線３９を相互接続するための接続用幹線４４が設けられている。任意の配線群に属する全基準線３９の長手方向（すなわち行方向、図４の左右方向）の一方端部が表示領域４２の外部まで伸延されており、伸延された一方端部が該配線群用の接続用幹線４４に接続されている。図４の例では、基準線３９よりも接続用幹線４４のほうが線幅が太い。また図４の例では、各配線群の接続用幹線４４の両端部分は、周辺領域４３内の基準線幅方向（すなわち列方向、図４の上下方向）両端部にも延びている。このように配線群毎に配線群に属する全基準線３９をそれぞれ束ねることによって、配線群毎にそれぞれに独立して別々の基準線駆動電圧を基準線３９に与えることが容易になる。これによって、表示品位を損なわずかつ製造コストの増加を抑えた液晶表示パネル３１が提供可能になる。
【００４６】
また配線群毎に、接続用幹線４４だけでなく補助幹線４５が設けられる。補助幹線４５は、単一配線群に属する全基準線３９の接続用幹線４４に接続されている一方端部とは逆の端部に図示しない絶縁層を介して重畳され、かつ該絶縁層に設けられたコンタクトホールを介して該配線群に属する基準線に接続される。また図４の例では、各配線群の接続用幹線４４の両端は、周辺領域４３内の基準線３９幅方向両端部にも延びており、該基準線幅方向両端部にある接続用幹線４４の前記端部分と該配線群に属する基準線３９の他方端部である伸延部とを補助幹線４５が、前述のようにコンタクトホールを介して、直接接続している。図５は、補助幹線４５がさらに用いられる場合の基準線３９の電気的構成の１例を示す等価回路図である。補助幹線４５がさらに設けられる場合、基準線３９の配線遅延がより確実に解消される。
【００４７】
奇数行配線群および偶数行配線群の２系統の配線群がある場合、第１基板表面の周辺領域４３内であって基準線３９の長手方向一方端部側に奇数行配線群の接続用幹線４４ｏｄｄが配置され、該周辺領域４３内であって基準線３９の長手方向他方端部側に偶数行配線群の接続用幹線４４ｅｖｅｎが配置されている。この結果、単一配線群に属す全基準線３９と該配線群の接続用幹線４４から形成される基準電極の平面形状が櫛状になる。これによって、奇数行配線群に属す基準線を含む基準電極４７と、偶数行配線群に属す基準線を含む基準電極４８とを、単一平面上に配置してかつ相互に離反して絶縁することが可能なので、両基準電極４７，４８を単一の導電性材料の薄膜から形成することが可能になる。
【００４８】
図６は、図１の液晶表示パネル３１の製造工程を説明するための工程図である。第１レイヤ形成工程において、全走査線３７と全基準線３９と全接続用幹線４４とが、第１基板上に同時に形成される。走査線３７の一部分が、能動三端子素子３６のゲート電極を兼ねている。次いで第２レイヤ形成工程において、全能動三端子素子３６の部品である層間絶縁膜および半導体層が、第１基板上に形成される。続いて第３レイヤ形成工程において、全画素電極３３と全能動三端子素子３６のソース電極およびドレイン電極とが、第１基板上に形成される。第３レイヤ形成工程では、前述した補助幹線４５が、画素電極３３と同材料を用いて該画素電極３３と同時にさらに形成されてもよい。この場合、第２レイヤ形成工程において、層間絶縁膜と同材料を用いて、補助幹線４５と貴準線３９との間の絶縁層が形成される。第１〜第３レイヤ形成工程と前後してまたは並行して、第４レイヤ形成工程において、対向電極３４と信号線３８とを兼ねる全信号電極４０が、第２基板上に形成される。最後に、部品形成後の第１基板と信号電極４０形成後の第２基板とが間隔を開けて貼合わされ、かつ両方基板間の空間に液晶材料が封入され、液晶表示パネル３１が完成する。
【００４９】
以上説明したように、基準線３９を束ねるための接続用幹線４４および補助幹線４５は、液晶表示パネル３１に従来から含まれる部品と同時に形成される。これによって、図１の液晶表示パネル３１の製造工程を従来の製造工程よりも増加させることなく、基準線３９を配線群毎に束ねることができる。したがって、配線群毎に異なる基準線駆動電圧を基準線３９に印加することが容易になり、かつ表示品位を損なわずに、かつ製造コストの増加を招くことなく、消費電力を低減させることができる。
【００５０】
図１〜図６で説明した構成の液晶表示パネル３１の駆動方法を、以下に説明する。本実施の形態の液晶表示パネル３１の駆動方法は、所謂１Ｈライン反転駆動法に準拠している。
【００５１】
概略的な液晶表示パネル３１の駆動方法は以下の通りである。配線群毎に、配線群に属する全基準線３９には、配線群毎に個別に予め定められている基準線駆動電圧がそれぞれ印加される。各配線群の基準線３９にそれぞれ印加される基準線駆動電圧は、配線群毎に相互に異なる。各走査線３７〔ｋ〕には、予め定めるフレーム時間毎に予め定める走査時間だけ能動三端子素子３６をオン状態にさせる走査線駆動電圧Ｇ〔ｋ〕が、それぞれ印加される。具体的には、走査線駆動電圧Ｇ〔ｋ〕の波形は、走査時間幅の矩形パルスが１フレーム時間毎に１回立上がる周期信号波形になっており、かつ各走査線〔ｋ〕に印加される走査線駆動電圧Ｇ〔ｋ〕の矩形パルス立上がりが相互にずれている。
各信号線３８〔ｍ〕には、各画素３２の液晶層３５内の電界を規定するための信号線駆動電圧Ｓ〔ｍ〕がそれぞれ印加される。基準線駆動電圧に対する信号線駆動電圧Ｓ〔ｍ〕の極性は、走査時間と同周期で変化している。この結果、基準線駆動電圧に対する信号線駆動電圧Ｓ〔ｍ〕の極性が走査時間と同周期で変化すべき場合、信号線駆動電圧の極性だけが走査時間周期で変化していれば良く、基準線駆動電圧の極性を走査時間周期で変化させる必要がなくなる。このような本実施の形態の駆動方法が用いられる場合、液晶表示パネル３１の表示品位を損なうことなく、かつ液晶表示パネル３１の製造プロセス数を増加させることなく、液晶表示パネル３１の消費電力を大幅に低減させることができる。
【００５２】
図１〜図６の具体例では、基準線３９が属すべき配線群が２系統あり、かつ画素３２の行と平行に配置されている全基準線３９が１本おきに相互接続されている。この場合、好ましくは、奇数行および偶数行偶数群の基準線駆動電圧Ｃｏｍ１，Ｃｏｍ２が相互に逆極性になっている。この結果、隣合う２行内の画素の充電電荷を相互に逆極性にすべき場合、信号線駆動電圧Ｓ〔ｍ〕の極性だけを走査時間周期で反転させるだけで良く、各基準線駆動電圧Ｃｏｍ１，Ｃｏｍ２の極性を走査時間周期で反転させる必要がなくなる。これによって液晶表示パネル３１は、所謂１Ｈライン反転駆動法で駆動されつつ、表示品位を損なうことなく、かつ液晶表示パネル３１の製造プロセス数を増加させることなく、消費電力を大幅に低減させることができる。
【００５３】
また好ましくは、各配線群の基準線駆動電圧Ｃｏｍ１，Ｃｏｍ２の極性は、前記フレーム時間だけ維持され、全走査線３７の走査が完了するたびに該基準線駆動電圧Ｃｏｍ１，Ｃｏｍ２の極性が逆転される。この結果、任意の１画素３２〔ｋ，ｍ〕の液晶層３５内の電界制御時の基準線駆動電圧に対する信号線駆動電圧Ｓ〔ｍ〕の極性が、連続する２つの各フレームにおいて相互に逆転するので、該連続する２フレームにおける該画素３２〔ｋ，ｍ〕の充電電荷が相互に逆極性になる。これによって、液晶表示パネル３１は、表示品位の低下および製造プロセス数の増加を防止しつつ消費電力を大幅に低減させるだけでなく、液晶表示パネル３１の表示の信頼性を向上させることができる。
【００５４】
図７は、本実施の形態の駆動方法が用いられる場合、図１の液晶表示パネル３１に対して印加される各種駆動電圧の２フレーム分の時間変化を示す波形図である。図７（Ａ）は、全奇数行のうちの任意の２ｎ−１行目の走査線３７〔２ｎ−１〕に印加される走査線駆動電圧Ｇ〔２ｎ−１〕の波形図、および全偶数行のうちの任意の２ｎ行目の走査線３７〔２ｎ〕に印加される走査線駆動電圧Ｇ〔２ｎ〕の波形図である。２ｎ行目の走査線の走査線駆動電圧Ｇ〔２ｎ〕の波形は、２ｎ−１行目の走査線の走査線駆動電圧Ｇ〔２ｎ−１〕の波形を時間経過方向に走査時間分だけずらした波形と等しい。図７（Ｂ）は、任意のｍ列目の信号線３８〔ｍ〕に印加される信号線駆動電圧Ｓ〔ｍ〕の波形図である。図７（Ｃ）は、奇数行配線群に属す全基準線３９〔１〕，３９〔３〕，…，３９〔２Ｎ−１〕に印加される奇数行用基準線駆動電圧Ｃｏｍ１の波形図である。図７（Ｄ）は、偶数行配線群に属す全基準線３９〔２〕，３９〔４〕，…，３９〔２Ｎ〕に印加される偶数行用基準線印加電圧Ｃｏｍ２の波形図である。なお図７では、液晶表示パネル３１の全ての各画素３２〔ｋ，ｍ〕に、表示に係る上限電圧を印加する場合を例として示す。
【００５５】
最初に、連続する２フレームのうちの１フレーム目における２ｎ−１行目の画素３２〔２ｎ−１，ｍ〕に対する電荷充電機構を、図７に基づいて説明する。１フレーム目において２ｎ−１行目の走査線の走査線駆動電圧Ｇ〔２ｎ−１〕がハイレベルを保つ期間内だけ、２ｎ−１行目の走査線に接続される全能動三端子素子３６〔２ｎ−１，ｍ〕がＯＮ状態になる。この結果、上記期間内に、図２の等価回路図に示す第１の経路５１を流れる電気信号によって、２ｎ−１行目の走査線３７〔２ｎ−１〕とｍ列目の信号線３８〔ｍ〕との交点にあたる２ｎ−１行ｍ列目の画素３２〔２ｎ−１，ｍ〕が充電される。第１の経路は、ｍ列目の信号線３８〔ｍ〕から、２ｎ−１行ｍ列の画素の対向電極３４〔２ｎ−１，ｍ〕と液晶層３５〔２ｎ−１，ｍ〕と画素電極３３〔２ｎ−１，ｍ〕とを経由し、かつ該画素に接続される能動三端子素子３６〔２ｎ−１，ｍ〕を経て、奇数行目の基準線３９〔２ｎ−１〕に至る。これによって、ｍ列目の信号線の信号線駆動電圧Ｓ〔ｍ〕から奇数行用基準線駆動電圧Ｃｏｍ１を減算した電位差分に相当する電荷が、２ｎ−１行ｍ列の画素３２〔２ｎ−１，ｍ〕に貯えられる。
【００５６】
図７（Ｃ）に示すように、１フレーム目における奇数行用基準線駆動電圧Ｃｏｍ１がローレベルであるならば、矢符５３で示すように、２ｎ−１行ｍ列の画素３２〔２ｎ−１，ｍ〕内の画素電極および対向電極間の印加電圧の極性はプラスである。２ｎ−１行目の走査線の走査線駆動電圧Ｇ〔２ｎ−１〕がハイレベルを保つ期間、該走査線と各信号線との交点画素３２〔２ｎ−１，１〕〜〔２ｎ−１，Ｍ〕それぞれにおいて、上記の手順の画素充電が並行実行される。
【００５７】
１フレーム目において、２ｎ−１行目の走査線の走査線駆動電圧Ｇ〔２ｎ−１〕に続き、２ｎ行目の走査線の走査線駆動電圧Ｇ〔２ｎ〕が走査時間だけハイレベルを保つので、図４の等価回路図に示す第２経路５２を流れる電気信号によって、２ｎ行目の各画素３２〔２ｎ，１〕〜〔２ｎ，Ｍ〕が充電される。第２経路５２は、ｍ列目の信号線３８〔ｍ〕から、２ｎ行目の走査線とｍ列目の信号線との交点にあたる画素の対向電極３４〔２ｎ，ｍ〕と液晶層３５〔２ｎ，ｍ〕と画素電極３３〔２ｎ，ｍ〕とを経由し、かつ該画素に接続される能動三端子素子３６〔２ｎ，ｍ〕とを経て、偶数行目の基準線３９〔２ｎ〕に至る。これによって２ｎ行ｍ列の画素３２〔２ｎ，ｍ〕には、ｍ列目の信号線の信号線駆動電圧Ｓ〔ｍ〕から偶数行用基準線駆動電圧Ｃｏｍ２を減算した電位差分に相当する電荷が貯えられる。
【００５８】
図７（Ｄ）に示すように、１フレーム目における偶数行用基準線駆動電圧Ｃｏｍ２がハイレベルであるならば、矢符５４で示すように、２ｎ行ｍ列の画素３２〔２ｎ，ｍ〕内の画素電極３３および対向電極３４間の印加電圧の極性はマイナスである。２ｎ行目の走査線の走査線駆動電圧Ｇ〔２ｎ〕がハイレベルを保つ期間、該走査線と各信号線との交点画素３２〔２ｎ，１〕〜〔２ｎ，Ｍ〕それぞれにおいて、上記手順の画素充電が並行実行される。
【００５９】
１フレーム目の走査中に、上記手順での奇数行の画素３２〔２ｎ−１，ｍ〕への充電と、上記手順での偶数行の画素３２〔２ｎ，ｍ〕への充電とは、走査線駆動電圧Ｇ〔ｋ〕によって制御されるタイミングで、交互に行われる。全ての走査線３７について画素充電が行われると、１フレーム目の走査が完了する。以上説明したように、１フレーム目の走査中において、奇数行に属す画素３２〔２ｎ−１，ｍ〕は奇数行用基準線駆動電圧Ｃｏｍ１から見てプラス側に充電され、偶数行に属す画素３２〔２ｎ，ｍ〕は偶数行用基準線駆動電圧Ｃｏｍ２から見てマイナス側に充電される。結果的に、奇数行および偶数行の基準線駆動電圧Ｃｏｍ１，Ｃｏｍ２は１フレーム目の走査中に所定レベルをそれぞれ保つが、液晶表示パネル３１全体では走査時間おきにプラスとマイナスの交互の極性で画素３２が充電される。これによって図７に示す液晶表示パネル３１の駆動方法では、図１１に示すように、行毎に、プラス極性とマイナス極性とで交互に画素３２が充電される。
【００６０】
以上説明したように、従来技術の１Ｈライン反転駆動法では基準線駆動電圧が走査期間と同周期で変化しているが、図７の駆動方法では基準線駆動電圧が１フレーム時間と同周期で変化している。これによって、原理的には、図１の液晶表示パネル３１を図７の駆動方法で駆動する場合の消費電力は、従来技術の液晶表示パネルを従来技術の１Ｈライン反転駆動法で駆動する場合の消費電力の全走査線数分の１になる。したがって図１の液晶表示パネル３１を図７の駆動方法で駆動する場合、全対向電極３４および全信号線３８における消費電力が、すなわち全信号電極４０における消費電力が、従来よりも大きく低減される。
【００６１】
画素３２の信頼性を高めるために、好ましくは、２フレーム目の走査時には、１フレーム目の走査時とは逆の極性で画素３２〔ｋ，ｍ〕が充電される。このために、２フレーム目の走査時の奇数行および偶数行用基準線駆動電圧Ｃｏｍ１，Ｃｏｍ２の極性が、１フレーム目の走査時の極性とそれぞれ逆転される。これによって２フレーム目の走査中において、奇数行に属す画素３２〔２ｎ−１，ｍ〕は、奇数行用基準線駆動電圧Ｃｏｍ１から見てマイナス側に充電され、偶数行に属す画素３２〔２ｎ，ｍ〕は、偶数行用基準線駆動電圧Ｃｏｍ２から見てプラス側に充電される。
【００６２】
以上図７を用いて説明したように、本実施の形態の液晶表示パネル３１の駆動方法においては、１本の走査線３７〔ｋ〕が走査されるたびに各信号線駆動電圧Ｓ〔ｍ〕の極性を反転させつつ、２系統の配線群に区分されている基準線３９に配線群毎に異なる極性の基準線駆動電圧Ｃｏｍ１，Ｃｏｍ２を印加して１フレーム時間維持させ、全走査線３７の走査が終了するたびに、基準線駆動電圧Ｃｏｍ１，Ｃｏｍ２の極性を逆転させる。これによって、１Ｈライン反転駆動法と等価な方法で液晶表示パネル３１が駆動されつつ、基準線駆動電圧Ｃｏｍ１，Ｃｏｍ２を走査時間おきに反転させる必要がなくなるために、液晶表示パネル３１の消費電力の大幅な低下が可能となり、かつ表示品位を損なわずかつ製造コストの増加を抑制可能な液晶表示パネル３１が提供可能となる。
【００６３】
図１〜図６の液晶表示パネル３１を上記の駆動方法で駆動する構成の液晶表示装置は、該液晶表示パネル３１の他に、各走査線３７〔ｋ〕に走査線駆動電圧Ｇ〔ｋ〕をそれぞれ印加するゲートドライバと、各配線群に属す基準線３９に配線群毎の基準線駆動電圧Ｃｏｍ１，Ｃｏｍ２をそれぞれ印加するコモンドライバと、各信号電極４０〔ｍ〕に信号線駆動電圧Ｓ〔ｍ〕をそれぞれ印加するソースドライバとを含む。本実施の形態の液晶表示パネル３１の駆動方法において、走査線駆動電圧Ｇ〔ｋ〕および信号線駆動電圧Ｓ〔ｍ〕は、従来技術の１Ｈライン反転駆動法における走査線駆動電圧および信号線駆動電圧とそれぞれ等しい。この結果、本実施の形態の駆動方法のほうが従来技術のドット反転駆動法よりも信号線駆動電圧Ｓ〔ｍ〕の変動幅が狭いので、本実施の形態の駆動方法のほうが従来技術のドット反転駆動法よりもソースドライバのコストを低減可能である。これによって、ソースドライバのコストを低減可能な１Ｈライン反転駆動法と等価な駆動方法によって駆動される本実施の形態の液晶表示パネル３１は、表示品位を損なうことなく、かつ製造工程数を増やすことなく、大幅な低消費電力化が可能となり、さらに大型高精細時に問題になりやすい基準線３９の配線遅延の問題を解決することが可能となる。
【００６４】
本実施の形態の液晶表示パネル３１およびその駆動方法は、本発明の液晶表示パネルおよびその駆動方法の例示であり、主要な構成および動作が等しければ、他の様々な形で実現することができる。特に液晶表示パネルの詳細構成ならびに液晶表示パネルの駆動方法の詳細手順は、同じ効果が得られるならば、上述の構成および手順に限らず、他の構成および手順によって実現されてもよい。
【００６５】
則ち本発明の対向信号線構造の液晶表示パネルの駆動方法は、基準線３９が２の配線群に区分されていてかつ配線群毎に異なる基準線駆動電圧が配線群に属す基準線３９にそれぞれ印加されればよい。さらに本発明の対向信号線構造の液晶表示パネルは、基準線３９が２以上の配線群に区分されていてかつ配線群毎に基準線３９が相互接続されていればよく、その他の構成は適宜変更されても良い。また基準線３９の束ね方は、全基準線３９をそれぞれ１本おきに２系統の配線群に束ねる。
【００６６】
【発明の効果】
以上のように本発明によれば、所謂対向信号線構造を有する液晶表示パネルの駆動方法において、複数の各基準線が２の配線群のうちのいずれかにそれぞれ属し、走査時間周期で極性が変化する信号線駆動電圧が信号線に印加され、かつ極性が配線群毎に異なる基準線駆動電圧が基準線に印加される。これによって、液晶表示パネルの表示品位を損なうことなく、かつ液晶表示パネルの製造プロセス数を増加させることなく、液晶表示パネルの消費電力を大幅に低減させることができる。
また本発明によれば、２系統の各配線群に属す基準線が１本ずつ交互に配置されている場合、奇数行の基準線に印加される基準線駆動電圧の極性が偶数行の基準線に印加される基準線駆動電圧の極性の逆極性になっている。これによって、液晶表示パネルの駆動回路のコストの低減を図ることがさらに可能になる。
さらにまた本発明によれば、各配線群に属する基準線に印加される基準線駆動電圧の極性が、フレーム時間と同周期で逆転する。これによって、液晶表示パネルの表示の信頼性を向上させることがさらに可能になる。
【００６７】
また以上のように本発明によれば、対向信号線構造の液晶表示パネルにおいて、複数本の各基準線が２の配線群のうちのいずれか１群に属し、かつ配線群毎に単一配線群に属す全基準線が相互接続されている。これによって、配線群毎に異なる基準線駆動電圧を基準線に印加することが容易になり、かつ液晶表示パネルの大型化および高精細化が容易になる。
さらにまた本発明によれば、配線群が２系統ある場合、画素の行と平行に配置される全基準線が１本おきに相互接続されている。これによって、奇数行の基準線と偶数行の基準線とに相互に異なる基準線駆動電圧を印加することが容易になる。
特に本発明によれば、基準線３９が有する抵抗および容量に起因した鈍った波形を形成する配線遅延を解消することができるようになる。
【図面の簡単な説明】
【図１】本発明の実施の一形態である液晶表示パネル３１の概略構成を示す模式図である。
【図２】図１の液晶表示パネル３１の４画素分の部分の等価回路図である。
【図３】図１の液晶表示パネル３１の構成を示す分解斜視図である。
【図４】図１の液晶表示パネル３１内の基準線３９の配置を示す平面図である。
【図５】図１の液晶表示パネル３１において、接続用幹線４４だけでなく補助幹線４５を用いて基準線３９が相互接続されている場合の基準電極の等価回路図である。
【図６】図１の液晶表示パネル３１の製造工程を示す工程図である。
【図７】図１の液晶表示パネル３１の駆動方法を説明するための波形図である。
【図８】第１の従来技術の液晶表示パネル３１の概略構成を示す模式図である。
【図９】図８の液晶表示パネル１の４画素分の部分の等価回路図である。
【図１０】図８の液晶表示パネル１の駆動方法の１つである１Ｈライン反転駆動法を説明
するための波形図である。
【図１１】図１０の１Ｈライン反転駆動法によって駆動される図８の液晶表示パネル１に
おける各画素の充電状態を示す図である。
【図１２】第２の従来技術の液晶表示パネルの概略構成を示す模式図である。
【図１３】図１２の液晶表示パネル１３の４画素分の部分の等価回路図である。
【図１４】第３の従来技術の液晶表示パネル１７の概略構成を示す模式図である。
【図１５】図８の液晶表示パネル１の製造工程を示す工程図である。
【符号の説明】
３１液晶表示パネル
３２画素
３３画素電極
３４対向電極
３５液晶層
３６能動三端子素子
３７走査線
３８信号線
３９基準線[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a liquid crystal display panel having a counter signal line structure and a driving method thereof.
[0002]
[Prior art]
2. Description of the Related Art In recent years, liquid crystal display panels including a plurality of pixels arranged in rows and columns have been increasingly used as display elements included in word processors, personal computers, television devices, and the like.
[0003]
FIG. 8 is a schematic structural view of an active matrix type liquid crystal display panel 1 which is a first prior art and has a structure using a TFT (Thin Film Transistor) 6 which is an active three-terminal element generally used conventionally. is there. FIG. 9 is an equivalent circuit diagram of a portion corresponding to four pixels in the liquid crystal display panel 1 of FIG. 8 and 9 will be described together. The structure of the liquid crystal display panel shown in FIGS. 8 and 9 is hereinafter referred to as “current structure”. The pixel 2 is configured such that a liquid crystal layer 5 formed of a liquid crystal material is interposed between the pixel electrode 3 and the counter electrode 4. The liquid crystal display panel 1 of FIG. 8 includes, in addition to the pixels 2, a first substrate, a second substrate, the same number of TFTs 6 as the total number of pixels 2, the same number of scanning lines 7 as the number of rows of pixels 2, and the number of columns of pixels 2. It includes the same number of signal lines 8 and reference lines 9. 8 and 9, the illustration of the first substrate and the second substrate is omitted, and in FIG. 8, the illustration of the liquid crystal material is omitted.
[0004]
On the first substrate, the pixel electrodes 3 of all the pixels 2, all the TFTs 6, all the scanning lines 7, and all the signal lines 8 are arranged. Each pixel electrode 3 is individually connected to a drain electrode of each TFT 6. The scanning line 7 is connected to the gate electrode of the TFT 6 connected to the pixel electrode 3 of each row of the pixels 2 for each row of the pixels 2. The signal line 8 is connected to the source electrode of the TFT 6 connected to the pixel electrode 3 of the pixel 2 for one column for each column of the pixel 2. On the second substrate, a one-sided solid electrode 11 is arranged. The one-surface solid electrode 11 is formed by integrating the opposing electrodes 4 of all the pixels 2 and the reference line 9 to be connected to the opposing electrodes 4. The liquid crystal material forming the liquid crystal layer 5 of all the pixels 2 is sealed between the first substrate and the second substrate. In the liquid crystal display panel 1 of FIG. 8, an auxiliary capacitance is often provided between the scanning line 7 and the pixel electrode 3.
[0005]
In FIG. 8, the number of the signal lines 8 is M, and the number of the scanning lines 7 is 2N. M and N are natural numbers. The number of signal lines 8 and the number of scanning lines 7 in an actual liquid crystal display panel differ depending on the product. In the following description, when a specific one of a plurality of one type of component is indicated, a reference numeral indicating the component is attached with a suffix indicating an arrangement order of the specific one component. Show. In this specification, n is an arbitrary integer of 1 or more and N or less, k is an arbitrary integer of 1 or more and 2N or less, and m is 1 or more.MIt is the following arbitrary integer.
[0006]
In order to form the liquid crystal display panel 1, first, thin films of a metal, a semiconductor, and the like are formed on a first substrate and a second substrate which are realized by glass or the like and have a light-transmitting property. Is patterned into a component shape to be arranged on each substrate. Next, the first substrate and the second substrate are bonded to each other with the component forming surfaces facing each other and with a predetermined gap therebetween, and a liquid crystal material is sealed in the gap between the two substrates. Thus, the liquid crystal display panel 1 is completed.
[0007]
As a driving method of the liquid crystal display panel 1 of FIG. 8, a so-called 1H line inversion driving method is generally and often used. In order to control the electric field in the liquid crystal layer 5 of the pixel 2 of the liquid crystal display panel 1 of FIG. 8, the liquid crystal display panel 1 is driven based on the chart of FIG. The method is described below. FIGS. 10A to 10C show the scanning line driving voltage applied to the scanning line 7, the signal line driving voltage applied to the signal line 8, and the reference applied to the reference line 9 in the above case. FIG. 4 is a chart showing a time change of a line drive voltage.
[0008]
The scanning line drive voltage individually applied to each scanning line 7 controls switching of an active three-terminal element connected to each scanning line 7 between an on state and an off state. The scanning line driving voltage may be switched every other scanning line. If the pixels 2 are scanned from top to bottom as viewed from the display surface side of the liquid crystal display panel 1, first, the scanning line driving voltage of the scanning line 7 [1] in the topmost row is set to a predetermined value. The ON voltage for keeping the TFT 6 in the ON state is maintained for the scanning time of 1H. When the scan line drive voltage of the first scan line 7 [1] is returned to the off voltage for turning off the TFT 6, the scan line drive voltage of the second scan line 7 [2] is changed to It is maintained at the ON voltage for only 1H. Such application of the scanning line driving voltage is sequentially repeated for each scanning line 7, and when the scanning line driving voltage of the scanning line 7 [2N] of the 2Nth row at the bottom becomes the OFF voltage, the liquid crystal display The scanning for one frame for all the pixels 2 of the panel 1 is completed.
[0009]
At the point in time when the scanning line driving voltage of any one scanning line 7 changes from the ON voltage to the OFF voltage, the pixel 2 including the pixel electrode 3 connected to the scanning line 7 via the TFT 6 includes the pixel electrode Charge corresponding to a voltage difference between a signal line driving voltage applied to the signal line 8 connected to the TFT 3 via the TFT 6 and a reference plane voltage applied to the counter electrode 4 is charged. In the liquid crystal display panel 1 of FIG. 8, the reference plane voltage applied to the counter electrode 4 is equal to the reference line drive voltage. Each pixel 2 keeps maintaining the charged electric charge while the scanning line driving voltage is the off voltage, so that an electric field corresponding to a desired display state of each pixel 2 is held in the liquid crystal layer 5 of each pixel 2. Therefore, an image for one frame is displayed on the liquid crystal display panel 1.
[0010]
After a while after the completion of the scanning of the first frame, the scanning of the second frame is performed on all the pixels 2 from the top to the bottom in the same order as the scanning of the first frame. A conventional general liquid crystal display panel is driven to display about 55 to 85 frames per second. The most common liquid crystal display panel displays 60 frames per second. When the liquid crystal display panel 1 of FIG. 8 is driven based on the chart of FIG. 10, two off-voltages of the scanning line driving voltage are set, and within a period in which the scanning line driving voltage should maintain the off-voltage. The off-state voltage may fluctuate in synchronization with the reference plane voltage.
[0011]
The polarity of the voltage applied to each pixel 2 scanned as described above will be described in further detail below, taking a case where a predetermined upper limit voltage is applied to all the pixels 2 of the liquid crystal display panel 1 as an example. explain. First, while only the scanning line driving voltage of the scanning line 7 [1] of the first row maintains the ON voltage, the signal line driving voltages of all the signal lines 8 [1] to 8 [M] take a high level, The reference plane voltage of the solid electrode 11 takes a low level. At this time, the switching of each TFT 6 [1, 1] to 6 [1, M] at the intersection of the first scanning line 7 [1] and each signal line 8 [1] to 8 [2N] causes The pixel 2 including the pixel electrodes 3 [1, 1] to 3 [1, M] connected to the TFT is charged with electric charge. The polarity of the electric charge charged to each pixel 2 [1, m] in the first row is positive when looking at each pixel electrode 3 [1, m] from the counter electrode 4 [1, m]. .
[0012]
Next, while only the scanning line driving voltage of the second scanning line 7 [2] maintains the ON voltage, the signal line driving voltages of the signal lines 8 [1] to 8 [M] and the reference of the one-sided solid electrode 11 are set. Both of the surface voltages change to the opposite polarities of the signal line driving voltage and the reference surface voltage when driving the first-row scanning line 7 [1]. Therefore, the signal line drive voltage of each of the signal lines 8 [1] to 8 [M] takes a low level, and the reference plane voltage takes a high level. At this time, the switching of the TFTs 6 [2, 1] to 6 [2, M] at the intersections of the second scanning line 7 [2] and the signal lines 8 [1] to 8 [M] causes the respective TFTs to be switched. Are charged to the pixels 2 [2,1] to 2 [2, M] including the pixel electrodes 3 [2,1] to 3 [2, M] connected to. The polarity of the electric charge charged to the pixel 2 [2, m] in the second row is negative when the pixel electrode 3 [2, m] is viewed from the counter electrode 4 [2, m].
[0013]
Similarly to the scanning of the first and second scanning lines 7 [1] and 7 [2], the scanning lines of the third and subsequent scanning lines 7 [3] and thereafter are also scanned. The pixels 2 are charged with electric charges according to the signal line driving voltage and the reference plane voltage, which alternately have the opposite polarity every other line. The polarity of the charge of pixel 2 at the time of completion of scanning of the first frame shown in FIG. 11A and the polarity of the charge of pixel 2 at the time of completion of scanning of the second frame shown in FIG. In comparison, both have opposite polarities for each pixel. Further, the charge state of the pixel at the completion of the scan of the third frame is the same as that of the first frame, and the charge state of the pixel at the completion of the scan of the fourth frame is the same as that of the second frame. As described above, focusing on any one specific pixel 2 of the liquid crystal display panel 1 of FIG. 8, the pixel electrode 3 [so that the polarity of the charge of the specific pixel 2 [k, m] is reversed for each frame. k, m] and a voltage between the opposing electrode 4 [k, m]. In one arbitrary frame, the polarity of the charge of the specific pixel 2 [k, m] is one pixel above and below the row to which the specific pixel belongs [pixels 2 [k−1, m], 2]. The polarity of the charge of [k + 1, m] is opposite to the polarity of the charge.
[0014]
Next, a liquid crystal display panel disclosed in JP-A-3-63623 will be described. FIG. 12 is a schematic structural view of an active matrix type liquid crystal display panel 13 described in JP-A-3-63623. FIG. 13 is an equivalent circuit diagram of a portion corresponding to four pixels in the liquid crystal display panel 13 of FIG. Among components of the liquid crystal display panel 13 of FIG. 12, components having the same functions as those of the components of the liquid crystal display panel 1 of FIG. 8 are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0015]
The differences between the configuration of the liquid crystal display panel 13 of FIG. 12 and the configuration of the liquid crystal display panel 1 of FIG. 8 are as follows. In the liquid crystal display panel 13 of FIG. 12, an odd-numbered reference electrode 14 and an even-numbered reference electrode 15 are arranged on a second substrate instead of the one-surface solid electrode 11 of FIG. The odd-numbered reference electrode 14 and the even-numbered reference electrode 15 are formed by dividing the solid electrode 11 on one surface into two substantially strip-shaped electrode pieces. The odd-numbered reference electrode 14 includes a counter electrode 4 [2n-1] facing the pixel electrode connected to the odd-numbered scanning line 7 [2n-1] via the TFT, and a reference line 9 connected to the counter electrode. [2n-1]. The even-numbered reference electrode 15 includes a counter electrode 4 [2n] facing a pixel electrode connected to the even-numbered scanning line 7 [2n] via a TFT, and a reference line 9 [2n] connected to the counter electrode. Are integrated. As shown in the equivalent circuit diagram of FIG. 13, the odd-numbered reference electrode 14 and the even-numbered reference electrode 15 are completely independent of each other. It is possible to apply different voltages to the reference voltage and the even reference electrode 15, respectively.
[0016]
Next, a liquid crystal display panel having a counter signal line structure and a driving method thereof described in JP-A-61-215590 will be described. FIG. 14 is a schematic structural view of an active matrix type liquid crystal display panel 17 having a facing signal line structure using TFTs as active three-terminal elements. Among the components of the liquid crystal display panel 17 of FIG. 14, components having the same functions as those of the components of the liquid crystal display panel 1 of FIG. 8 are denoted by the same reference numerals, and detailed description thereof will be omitted. The liquid crystal display panel 17 of FIG. 14 includes, in addition to the pixel 2, a first substrate, a second substrate, the same number of TFTs 6 as the total number of pixels 2, the same number of scanning lines 7 as the number of rows of pixels 2, and the number of columns of pixels 2. It includes the same number of signal lines 8 and reference lines 9. In FIG. 14, the illustration of the first substrate, the second substrate, and the liquid crystal material is omitted.
[0017]
On the first substrate, the pixel electrodes 3 of all the pixels 2, all the TFTs 6, all the reference lines 9, and all the scanning lines 7 are arranged. On the second substrate, the same number of signal electrodes 18 as the number of columns of the pixels 2 are arranged in parallel. The signal electrode 18 [m] facing the pixel electrodes 3 [1, m] to [2N, m] of all the pixels in the m-th column is a signal line 8 [m] to be arranged in parallel with the pixel column in the m-th column. And the counter electrodes 4 [1, m] to [2N, m] of all the pixels in the m-th column. The liquid crystal material forming the liquid crystal layer 5 of all the pixels 2 is sealed between the first substrate and the second substrate. In FIG. 14, the number of signal lines 8 is M and the number of scanning lines 7 is 2N, but the actual number of lines of the liquid crystal display panel 17 differs depending on the product.
[0018]
The 1H line inversion driving method in the liquid crystal display panel 17 having the opposed signal line structure shown in FIG. 14 is different from the 1H line inversion driving method in the liquid crystal display panel 1 having the current structure shown in FIG. The difference is that the technique for eliminating the flicker is partly required, and the remaining part such as the voltage application method to each pixel 2 is basically the 1H line inversion driving method of the liquid crystal display panel of FIG. Is almost equal to In the charging mechanism of the liquid crystal display panel 1 shown in FIG. 8, electric charges to be charged in an arbitrary pixel 2 [k, m] are transferred from the m-th signal line 8 [m] to the TFT 6 [k, m] and the pixel electrode 3. [K, m] and the liquid crystal layer 5 [k, m], in this order, to the counter electrode 4 [k, m] connected to the reference line 9, whereas the liquid crystal display panel of FIG. In the charging mechanism 17, the electric charge to be charged in the arbitrary pixel 2 [k, m] is transferred from the signal electrode 18 [m] in the m-th row, which also serves as a signal line and a counter electrode, to the liquid crystal layer 5 [k, m]. The pixel electrode 3 [k, m] and the TFT 6 [k, m] pass in this order to the reference line 9.
[0019]
Thus, from the viewpoint of circuit driving, the 1H line inversion driving method of the liquid crystal display panel 17 having the opposed signal line structure in FIG. 14 is roughly the same as the 1H line inversion driving method of the liquid crystal display panel 1 having the current structure in FIG. Are the same, that is, equivalent to the driving method described with reference to the chart of FIG. Although the method of driving the liquid crystal display panel 1 in FIG. 8 and the method of driving the liquid crystal display panel 17 in FIG. 14 differ in the average voltage setting of the reference plane voltage, this does not matter in the present invention.
[0020]
[Problems to be solved by the invention]
Problems to be solved by the present invention will be described for a liquid crystal display panel using an active three-terminal element. In the 1H line inversion driving method, each time the scanning line 7 to be scanned, which is a scanning line to which a pixel to be charged is connected, advances one by one, the polarity of the reference plane voltage, which is the reference voltage at the time of charge charging. Is always inverted. For this reason, the waveform indicating the time change of the reference plane voltage is a rectangular wave whose voltage changes every 1H which is a predetermined scanning time. Since there is always a resistive load and a capacitive load in the reference line 9 to which the reference line drive voltage for defining the reference plane voltage is applied, a reference line drive voltage having a waveform close to a rectangular wave or a short wave is applied to the reference line 9. Even if the voltage is applied, the waveform of the reference plane voltage actually extracted from the reference line 9 becomes a dull waveform including a wiring delay. If the polarity of the signal line driving voltage is inverted with reference to the reference surface voltage having such a dull waveform, a current in a direction opposite to the current related to charge charging flows every time the polarity is inverted, and power is consumed. . Moreover, since the reference plane voltage is a reference voltage for polarity inversion for all the pixels 2, the power consumption at the time of polarity inversion becomes extremely large. There have been some measures against power consumption at the time of polarity reversal, but they have not been solved. Hereinafter, conventional measures will be described.
[0021]
As a first measure, a dot inversion driving method, which is one of the other driving methods of the liquid crystal display panel, is adopted instead of the 1H line inversion driving method. The dot inversion driving method is often used in a liquid crystal display panel having a current structure using a TFT, such as the liquid crystal display panel 1 in FIG. In the dot inversion driving method, while maintaining the reference plane voltage at a constant DC voltage, such a polarity that the polarity largely fluctuates to both a voltage having a positive polarity than the reference plane voltage and a voltage having a negative polarity than the reference plane voltage is greatly changed. By applying a signal line driving voltage to the signal line 8, the liquid crystal in the pixel 2 is AC driven. In the dot inversion driving method, since the reference plane voltage always keeps a predetermined value, almost no current due to the fluctuation of the reference plane voltage flows, and the power consumption in the circuit portion to which the reference plane voltage is applied is very small. . However, the fluctuation width of the signal line driving voltage in the dot inversion driving method is twice as large as the fluctuation width of the signal line driving voltage in the 1H line inversion driving method. In the circuit portion to which the signal line drive voltage of the 1H line inversion driving method is applied jumps up to about twice as much. For this reason, when the dot inversion driving method is used, it is hard to say that the power consumption of the entire liquid crystal display panel is totally reduced.
[0022]
As a second countermeasure, the structure of the liquid crystal display panel is kept the same as that shown in FIG. 8, and the details of the driving method can be changed. For example, in the 1H line inversion driving method, the polarity of the signal line driving voltage and the reference plane voltage is inverted so that the polarity of the pixel charge is inverted each time the scanning line 7 to be scanned advances by one line. At the time of countermeasures, the number of reversals of the polarity of pixel charging is reduced. Specifically, as in the so-called 2H line inversion driving method, the signal line driving voltage and the reference plane voltage are controlled so that the polarity of the pixel charge is inverted every time two scanning lines 7 to be scanned advance. As a result, the current flowing to charge the pixel with a charge of the opposite polarity during the polarity inversion during the use of the 2H line inversion driving method is half the current flowing per unit time during the polarity inversion during the use of the 1H line inversion driving method. That is, since the number of times of generation of the pulse is halved, the number of times of the current flowing at the pulse transition is also halved. Thus, the power consumption in the circuit portion to which the reference plane voltage is applied when using the 2H line inversion driving method is about half of the power consumption in the circuit portion to which the reference plane voltage is applied when using the 1H line inversion driving method. .
[0023]
However, under the situation where the 2H line inversion driving method is used, a fundamental deterioration in display quality occurs. The deterioration of the display quality is caused by the fact that the amount of charge to the pixel 2 charged immediately after the polarity inversion of the signal line drive voltage and the reference plane voltage is increased after the scanning of one scanning line has progressed from the time of the polarity inversion. Due to the different charge amount. Generally, for example, when a solid black image is displayed on a screen of a liquid crystal display panel, that is, when an upper limit voltage is applied to all pixels 2, it is connected to a scanning line 7 that is scanned immediately after polarity inversion. The row composed of the pixels 2 is light black, and the row composed of the pixels 2 charged after the scanning is further advanced by one scanning line after the polarity inversion is dark black. Also, even if the scanning direction in the next frame is reversed from the previous frame in an attempt to cancel the non-uniform charging amount, flickering occurs because an image having shading is essentially drawn in the opposite direction for each frame. Would. The second problem cannot be solved by changing the polarity inversion timing of the signal line drive voltage and the reference plane voltage from every other scanning line to every four scanning lines. Furthermore, when charges of the same polarity are drawn on all the pixels 2 during scanning for one frame, and charges of a polarity opposite to the polarity at the time of writing charges of the previous frame are written during scanning for the next frame, The problem is not solved because it causes flicker.
[0024]
As a third measure, as shown in JP-A-3-63623 and FIG. 12, the structure itself of the liquid crystal display panel is changed. More specifically, a counter electrode 4 facing the pixel electrode 3 is divided into two systems so that signals can be input to each system independently, and a different voltage is applied to the counter electrode 4 of each system for each system. Applied. As a result, the frequency of the reference plane voltage waveform is reduced to about one-half the number of scanning lines of the frequency of the original reference plane voltage waveform of the 1H line inversion drive system, while maintaining the apparent 1H line inversion driving method. As a result, the waveform of the reference plane voltage changes every scanning time in the original 1H line inversion driving method described with reference to FIGS. 8 to 10, but in the driving method described in FIG. Power consumption, power consumption is greatly reduced.
[0025]
However, in order to create a liquid crystal display panel having a structure having the counter electrode 4 divided into two systems, it is necessary to add a new patterning step once to the current manufacturing process of the liquid crystal display panel 1 having the current structure. is there. FIG. 15 is a process diagram showing a schematic manufacturing process of the liquid crystal display panel 1 of FIG. In the manufacturing process of the liquid crystal display panel 1 shown in FIG. 8, the component formation process on the second substrate requires only one deposition step. However, in order to pattern the counter electrode 4 into two systems, the above-described deposition step is required. In addition, since one photo step and one etching step are required, the manufacturing cost of the liquid crystal display panel is greatly increased as a result.
[0026]
An object of the present invention is to reduce power consumption without increasing manufacturing costs and maintaining display quality.Moreover, the wiring delay of the reference line to which the source electrode of the active three-terminal element is connected is eliminated.The present invention provides a method of driving a liquid crystal display panel and a liquid crystal display panel.
[0027]
[Means for Solving the Problems]
The present inventionIn the display area 42 on the first substrate,A plurality of pixels each having a liquid crystal layer interposed between the pixel electrode and the counter electrode and arranged in a matrix,
GetPlural active three-terminal devices each having a gate electrode, a source electrode, and a drain electrode connected to the pixel electrode36,
lineA scanning line to which a gate electrode of an active three-terminal element connected to a pixel electrode of one row of pixels is connected every time37,and
lineA reference line to which a source electrode of an active three-terminal element connected to a pixel electrode of a pixel of one row is connected every time39 is arranged,
On the second substrate,A signal line to which the counter electrode of one column of pixels is connected for each column38 are arranged,
Liquid crystal is interposed between the first substrate and the second substrateA method of driving a liquid crystal display panel,
All the reference lines are divided into first and second two wiring groups,
In the peripheral area 43 outside the display area 42 on the first substrate,
One end of the reference line of the first wiring group in the longitudinal direction is extended to form a first connecting trunk line 44. odd Connected to
The other end in the longitudinal direction of the reference line of the second wiring group is extended, and the second connecting trunk line 44 is extended. even Connected to
First and second connecting trunks 44 odd, 44 even Has an end portion having a line width larger than the reference line 39 and extending to both ends in the reference line width direction in the peripheral region 43,
In the peripheral area 43,
A first extension part in which the other end in the longitudinal direction of the reference line of the first wiring group is extended, and a second connecting trunk 44 even A first auxiliary trunk line 45 via a first insulating layer odd Is provided, and the first auxiliary trunk line 45 is provided. odd Are connected to the first extension portion and the first connecting trunk line 44 through a contact hole provided in the first insulating layer. odd Directly connected to said end portion of
The peripheral area 43 also includes
A second extension part in which one end in the longitudinal direction of the reference line of the second wiring group is extended; odd A second auxiliary main line 45 via a second insulating layer even Is provided, and the second auxiliary trunk line 45 is provided. even Are connected to the second extension portion and the second connecting trunk line 44 through a contact hole provided in the second insulating layer. even Directly connected to said end portion of
A scanning line driving voltage for turning on the active three-terminal element for a predetermined scanning time for each predetermined frame time is applied to each scanning line, and a signal line driving voltage whose polarity changes in the same cycle as the scanning time is applied. Applied to each signal line,
DistributionA reference line drive voltage individually predetermined for each line group is applied to all the reference lines belonging to each wiring group,
Belongs to each wiring groupToThe reference line drive voltages applied to the reference lines are different from each other.And the polarity is inverted in the same cycle as one frame timeA method for driving a liquid crystal display panel.
[0028]
According to the present invention, in a method for driving a liquid crystal display panel having a so-called opposed signal line structure, a plurality of reference lines are provided.TwoDivided into wiring groups and belong to each wiring groupToA different reference line drive voltage is applied to the reference line for each wiring group. As a result, when the polarity of the signal line drive voltage with respect to the reference line drive voltage should be changed in the same cycle as the scanning time, only the polarity of the signal line drive voltage need only be changed in the scan time cycle. Need not be changed in the scanning time cycle. Thereby, the power consumption of the liquid crystal display panel can be significantly reduced without deteriorating the display quality of the liquid crystal display panel and without increasing the number of manufacturing processes of the liquid crystal display panel.
[0030]
According to the present invention, in a method of driving a liquid crystal display panel having a structure in which reference lines belonging to two wiring groups are alternately arranged one by one, a reference line driving voltage applied to odd-numbered reference lines is provided. The polarity is opposite to the polarity of the reference line drive voltage applied to the even-numbered reference lines. As a result, the liquid crystal display panel is driven by a method equivalent to the so-called 1H line inversion driving method. Therefore, when the polarities of the charge charges of the two adjacent rows of pixels should be inverted, only the polarity of the signal line driving voltage is scanned. It is sufficient that the polarity of the reference line drive voltage is inverted only in the time period, and there is no need to invert the polarity of the reference line drive voltage in the scanning time period. This not only reduces the power consumption of the liquid crystal display panel while preventing a decrease in display quality and an increase in the number of manufacturing processes, but also makes it possible to reduce the cost of the driving circuit of the liquid crystal display panel.
[0032]
According to the present invention, in the method of driving the liquid crystal display panel, the polarity of the reference line driving voltage to be applied to the reference line belonging to each wiring group is reversed in the same cycle as the frame time, so that in each of two consecutive frames, The polarity of the charge of any one pixel is reversed. This not only reduces the power consumption of the liquid crystal display panel while preventing a decrease in display quality and an increase in the number of manufacturing processes, but also improves the display reliability of the liquid crystal display panel.
[0033]
Also, the present inventionA first substrate having a display area 42 and a peripheral area 43 outside the display area 42;
A second substrate having liquid crystal interposed between the first substrate and the first substrate;
In the display area 42 on the first substrate,
A plurality of pixels each having a liquid crystal layer interposed between the pixel electrode and the counter electrode and arranged in a matrix,
A plurality of active three-terminal elements 36 each having a gate electrode, a source electrode, and a drain electrode connected to the pixel electrode,
A scanning line 37 to which a gate electrode of an active three-terminal element connected to pixel electrodes of pixels of one row for each row is connected;
A reference line 39 to which a source electrode of an active three-terminal element connected to a pixel electrode of a pixel for one row is arranged for each row,
On the second substrate, a signal line 38 to which a counter electrode of a pixel for one column is connected for each column is arranged,
All the reference lines are divided into first and second two wiring groups,
In the peripheral area 43 outside the display area 42 on the first substrate,
One end of the reference line of the first wiring group in the longitudinal direction is extended to form a first connecting trunk line 44. odd Connected to
The other end in the longitudinal direction of the reference line of the second wiring group is extended, and the second connecting trunk line 44 is extended. even Connected to
First and second connecting trunks 44 odd, 44 even Has an end portion having a line width larger than the reference line 39 and extending to both ends in the reference line width direction in the peripheral region 43,
In the peripheral area 43,
A first extension part in which the other end in the longitudinal direction of the reference line of the first wiring group is extended; odd A first auxiliary trunk line 45 via a first insulating layer odd Is provided, and the first auxiliary trunk line 45 is provided. odd Are connected to the first extension portion and the first connecting trunk line 44 through a contact hole provided in the first insulating layer. odd Directly connected to said end portion of
The peripheral area 43 also includes
A second extension part in which one end in the longitudinal direction of the reference line of the second wiring group is extended, and a second connecting trunk line 44; even A second auxiliary main line 45 via a second insulating layer even Is provided, and the second auxiliary trunk line 45 is provided. even Are connected to the second extension portion and the second connecting trunk line 44 through a contact hole provided in the second insulating layer. even Directly connected to said end portion of
A scanning line driving voltage for turning on the active three-terminal element for a predetermined scanning time for each predetermined frame time is applied to each scanning line, and a signal line driving voltage whose polarity changes in the same cycle as the scanning time is applied. Applied to each signal line,
A reference line drive voltage that is individually predetermined for each wiring group is applied to all the reference lines belonging to each wiring group,
The reference line driving voltages applied to the reference lines belonging to the respective wiring groups are different from each other, and are changed in polarity and applied in the same cycle as one frame time.Characterized byLCD panelIt is.
[0034]
According to the present invention, in a liquid crystal display panel having a so-called opposed signal line structure, each reference line isTwoAll the reference lines belonging to any one of the wiring groups and belonging to a single wiring group are interconnected for each wiring group. This ensures that all reference linesTwoSince the system is divided into systems, it is possible to easily apply a different reference line driving voltage for each wiring group to a reference line belonging to the wiring group. This also prevents the wiring delay of the reference line driving voltage, thereby facilitating the enlargement and high definition of the liquid crystal display panel.
[0036]
According to the present invention, in a liquid crystal display panel having a so-called opposed signal line structure, when there are two wiring groups, reference lines belonging to each of the two wiring groups are alternately arranged one by one in parallel with a row of pixels. In addition, reference lines are interconnected for each wiring group. This makes it possible to apply different reference line driving voltages to the reference line connected to the active three-terminal elements of the pixels in the odd-numbered rows and the reference line connected to the active three-terminal elements of the pixels in the even-numbered rows. It is easily possible.
[0037]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a schematic diagram showing a schematic structure of a liquid crystal display panel 31 according to one embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of a portion corresponding to four pixels in the liquid crystal display panel 31 of FIG. FIG. 3 is an exploded perspective view showing a detailed configuration of the liquid crystal display panel 31 of FIG. 1 to 3 will be described together. The liquid crystal display panel 31 of FIG. 1 is an active matrix type liquid crystal display panel having a so-called opposed signal line structure.
[0038]
The liquid crystal display panel 31 includes a plurality of pixels 32, the same number of active three-terminal elements 36 as the pixels 32, the same number of scanning lines 37 as the number of rows of the pixels 32, and the same number of reference lines 39 as the number of rows of the pixels 32. , And the same number of signal lines 38 as the number of columns of the pixels 32. Each pixel 32 includes a liquid crystal layer 35 formed of a liquid crystal material, and a pixel electrode 33 and a counter electrode 34 that are arranged to face each other with the liquid crystal layer 35 interposed therebetween. Each active three-terminal element 36 has a gate electrode, a source electrode, and a drain electrode. All the pixels 32 are arranged in a matrix in a plane. The scanning line 37 and the reference line 39 individually correspond to the rows of the pixels 32, respectively. The signal lines 38 individually correspond to the columns of the pixels 32. The active three-terminal elements 36 individually correspond to the pixels 32.
[0039]
In the present embodiment, the number of the signal lines 38 is M, and the number of the scanning lines 37 is 2N. M and N are natural numbers. The actual number of signal lines 38 and the number of scanning lines 37 in the liquid crystal display panel 31 differ depending on the product. In the following description of the present embodiment, when a specific one of a plurality of one type of component is indicated, a reference numeral generically indicating the component indicates the arrangement order of the specific one component. Indicated with a subscript. In this specification, n is an arbitrary integer of 1 or more and N or less, k is an arbitrary integer of 1 or more and 2N or less, and m is 1 or more.MIt is the following arbitrary integer.
[0040]
The pixel electrode 33 [k, m] of the pixel 32 [k, m] is individually connected to the drain electrode of the active three-terminal element 36 [k, m] corresponding to the pixel. The gate electrodes of the active three-terminal elements 36 [k, 1] to 36 [k, M] individually corresponding to the pixels belonging to the k-th row are connected to the scanning lines 37 [k] corresponding to the k-th row. Source electrodes of the active three-terminal elements 36 [k, 1] to 36 [k, M] individually corresponding to all pixels belonging to the k-th row are connected to a reference line 39 [k] corresponding to the k-th row. The counter electrodes 34 [1, m] to 34 [2N, m] of all the pixels belonging to the m-th column are connected to the signal line 38 [m] corresponding to the m-th column. 1 to 3, a TFT is used as the active three-terminal element 36, and the counter electrodes 34 [1, m] to 34 [2N, m] of all the pixels for one column are provided for each column. And the signal line 38 [m] corresponding to the column are integrated to form a substantially strip-shaped signal electrode 40 [m].
[0041]
In the liquid crystal display panel 31 of FIG. 1, all the reference lines 39 [1] to 39 [2N] correspond to two systems.TraditionalAll the reference lines 39 belonging to the wiring group are interconnected for each wiring group. As a result, all the reference lines 39 [1] to 39 [2N]TwoSince the system is divided into systems, it is possible to easily apply a different reference line drive voltage for each wiring group to the reference line 39 belonging to the wiring group. This also prevents the wiring delay of the reference line driving voltage, so that the size and definition of the liquid crystal display panel 31 can be easily increased.
[0042]
In the example of FIGS. 1 to 3, all the reference lines 39 [1] to 39 [2N] are divided into two wiring groups, and the reference lines 39 belonging to each of the two wiring groups are parallel to the row of the pixel 32 by one. The books are arranged alternately. That is, the entire reference line 39 is a wiring group including the reference line 39 [2n-1] connected to the active three-terminal element 36 [2n-1, m] corresponding to the pixel 32 [2n-1, m] in the odd-numbered row. And a wiring group consisting of a reference line 39 [2n] connected to the active three-terminal element 36 [2n, m] of the pixel 32 [2n, m] in the even-numbered row. Every other interconnect. This makes it easy to apply different reference line drive voltages to the odd-numbered reference line 39 [2n-1] and the even-numbered reference line 39 [2n].
[0043]
The detailed configuration of the liquid crystal display panel 31 of the present embodiment using a TFT as the active three-terminal element 36 will be described with reference to FIGS. The liquid crystal display panel 31 further includes a first substrate and a second substrate (not shown) in addition to the pixel 32, the active three-terminal element 36, the scanning line 37, the reference line 39, and the signal line 38. The pixel electrodes 33 of all the pixels 32 are arranged in a matrix on the first substrate. The reference line 39 [k] of the k-th row is located near the pixel electrodes 33 [k, 1] to 33 [k, M] of all the pixels of the k-th row on the first substrate in parallel with the arbitrary row. Be placed. The k-th scanning line 37 [k] is formed on the first substrate by the pixel electrodes 33 [k, 1] to 33 [k, M] of the k-th row pixel and the k-th reference line 39 [k]. And placed between. The liquid crystal material constituting each of the liquid crystal layers 35 of all the pixels 32 is sealed between the first substrate and the second substrate. Each signal electrode 40 [m] is disposed on the second substrate, and faces all the pixel electrodes 33 [1, m] to [2N, m] in each column via a liquid crystal material layer between the substrates.
[0044]
A pixel electrode 33 [k, m] of each pixel 32 [k, m] is individually connected to a drain electrode of an active three-terminal element 36 [k, m] individually corresponding to each pixel. The gate electrodes of the active three-terminal elements 36 [k, 1] to 36 [k, M] corresponding to the respective pixels in the k-th row are connected to the k-th scanning line 37 [k]. The source electrodes of the active three-terminal elements 36 [k, 1] to 36 [k, M] corresponding to the respective pixels in the k-th row are connected to the k-th row reference line 39 [k]. .., 39 [2N-1] of odd-numbered reference lines 39 [1] to 39 [2N] among all reference lines 39 [1] to 39 [2N]; An even-numbered line group consisting of even-numbered reference lines 39 [2], 39 [4],..., 39 [2N] among 39 [1] to 39 [2N] is separately provided for each line group. Be bundled. The reference lines 39 bundled for each wiring group are formed on the display area 42 on the surface of the first substrate where the pixel electrodes 33 are arranged so that a voltage can be applied separately and independently for each wiring group. Pulled out.
[0045]
FIG. 4 is a plan view showing an example of a specific configuration of the reference line 39 in the liquid crystal display panel 31 of FIGS. All the reference lines 39 [1] to 39 [2N] are arranged parallel to each other in the display area 42 on the surface of the first substrate. In a peripheral area 43 outside the display area 42 on the surface of the first substrate, a connecting trunk line 44 for interconnecting all the reference lines 39 belonging to the wiring group is provided for each wiring group. Belongs to any wiring groupToLongitudinal direction of all reference lines 39(Ie, row direction, left-right direction in FIG. 4)Is extended to the outside of the display area 42, and the extended one end is connected to the connecting trunk 44 for the wiring group. In the example of FIG. 4, the connecting trunk line 44 has a wider line width than the reference line 39. In the example of FIG. 4, both ends of the connecting trunk line 44 of each wiring group are provided.partIs the reference line width direction in the peripheral region 43(That is, the column direction, the vertical direction in FIG. 4)It extends to both ends. Thus, each wiring group belongs to a wiring group.ToBy bundling all the reference lines 39, it becomes easy to apply different reference line drive voltages to the reference lines 39 independently for each wiring group. Thus, it is possible to provide the liquid crystal display panel 31 which has a small display quality and a small increase in manufacturing cost.
[0046]
In addition, an auxiliary trunk 45 as well as a connecting trunk 44 is provided for each wiring group.To. The auxiliary trunk 45 is overlapped with an end opposite to one end connected to the connection trunk 44 of all the reference lines 39 belonging to the single wiring group via an insulating layer (not shown), and is connected to the insulating layer. Belongs to the wiring group through the provided contact holeGroupConnected to the alignment line. In the example of FIG. 4, both ends of the connecting trunk 44 of each wiring group also extend to both ends in the width direction of the reference line 39 in the peripheral region 43, and the connecting trunks 44 at both ends of the reference line width direction are provided.The end portion ofAnd belongs to the wiring groupToThe other end of the reference line 39Is the distractionAnd the auxiliary trunk line 45,As described above, via the contact hole,Connected directly. FIG. 5 is an equivalent circuit diagram illustrating an example of an electrical configuration of the reference line 39 when the auxiliary trunk line 45 is further used. When the auxiliary trunk 45 is further provided, the wiring delay of the reference line 39 is more reliably eliminated.
[0047]
When there are two types of wiring groups, an odd-numbered wiring group and an even-numbered wiring group, the connecting trunk line of the odd-numbered wiring group is located on one end side of the reference line 39 in the peripheral region 43 on the first substrate surface in the longitudinal direction. 44odd is arranged, and a connecting trunk line 44even of an even-numbered wiring group is arranged in the peripheral region 43 and on the other end side in the longitudinal direction of the reference line 39. As a result, the planar shape of the reference electrode formed from all the reference lines 39 belonging to the single wiring group and the connecting trunk 44 of the wiring group becomes comb-like. Thus, the reference electrode 47 including the reference line belonging to the odd-numbered wiring group and the reference electrode 48 including the reference line belonging to the even-numbered wiring group are arranged on a single plane and separated from each other and insulated. Therefore, the reference electrodes 47 and 48 can be formed from a single thin film of a conductive material.
[0048]
FIG. 6 is a process chart for explaining a manufacturing process of the liquid crystal display panel 31 of FIG. In the first layer forming step, all the scanning lines 37, all the reference lines 39, and all the connecting trunk lines 44 are simultaneously formed on the first substrate. A part of the scanning line 37 also serves as a gate electrode of the active three-terminal element 36. Next, in a second layer forming step, an interlayer insulating film and a semiconductor layer which are components of all the active three-terminal elements 36 are formed on the first substrate. Subsequently, in a third layer forming step, all the pixel electrodes 33 and the source and drain electrodes of all the active three-terminal elements 36 are formed on the first substrate. In the third layer forming step, the auxiliary trunk 45 described above may be further formed simultaneously with the pixel electrode 33 using the same material as the pixel electrode 33. In this case, in the second layer forming step, an insulating layer between the auxiliary main line 45 and the noble line 39 is formed using the same material as the interlayer insulating film. In the fourth layer forming step, before or after or in parallel with the first to third layer forming steps, all the signal electrodes 40 serving as the counter electrode 34 and the signal line 38 are formed on the second substrate. Finally, the first substrate after the components are formed and the second substrate after the signal electrodes 40 are formed are adhered at an interval, and a liquid crystal material is sealed in a space between both substrates, thereby completing the liquid crystal display panel 31.
[0049]
As described above, the connecting trunk 44 and the auxiliary trunk 45 for bundling the reference line 39 are formed simultaneously with the components conventionally included in the liquid crystal display panel 31. Thus, the reference lines 39 can be bundled for each wiring group without increasing the number of manufacturing steps of the liquid crystal display panel 31 of FIG. 1 as compared with the conventional manufacturing steps. Therefore, it is easy to apply a different reference line driving voltage to the reference line 39 for each wiring group, and it is possible to reduce the power consumption without deteriorating the display quality and without increasing the manufacturing cost. .
[0050]
A method of driving the liquid crystal display panel 31 having the configuration described with reference to FIGS. 1 to 6 will be described below. The driving method of the liquid crystal display panel 31 of the present embodiment is based on the so-called 1H line inversion driving method.
[0051]
A schematic driving method of the liquid crystal display panel 31 is as follows. For each wiring group, a reference line driving voltage which is individually predetermined for each wiring group is applied to all the reference lines 39 belonging to the wiring group. The reference line drive voltage applied to the reference line 39 of each wiring group differs from one wiring group to another. To each scanning line 37 [k], a scanning line driving voltage G [k] for turning on the active three-terminal element 36 for a predetermined scanning time for each predetermined frame time is applied. Specifically, the waveform of the scanning line driving voltage G [k] is a periodic signal waveform in which a rectangular pulse having a scanning time width rises once every frame time, and is applied to each scanning line [k]. The rising of the rectangular pulse of the scanning line driving voltage G [k] is shifted from each other.
eachA signal line driving voltage S [m] for defining an electric field in the liquid crystal layer 35 of each pixel 32 is applied to the signal line 38 [m].BaseThe polarity of the signal line driving voltage S [m] with respect to the quasi line driving voltage changes in the same cycle as the scanning time. As a result, if the polarity of the signal line driving voltage S [m] with respect to the reference line driving voltage should change in the same cycle as the scanning time, only the polarity of the signal line driving voltage needs to change in the scanning time cycle. It is not necessary to change the polarity of the line drive voltage in the scanning time cycle. When such a driving method according to the present embodiment is used, the power consumption of the liquid crystal display panel 31 can be reduced without deteriorating the display quality of the liquid crystal display panel 31 and without increasing the number of manufacturing processes of the liquid crystal display panel 31. It can be greatly reduced.
[0052]
In the specific examples of FIGS. 1 to 6, there are two systems to which the reference lines 39 belong, and every other reference line 39 arranged in parallel with the row of the pixels 32 is interconnected. In this case, preferably, the reference line drive voltages Com1 and Com2 of the odd-numbered rows and the even-numbered and even-numbered groups have mutually opposite polarities. As a result, when the charges of the pixels in the two adjacent rows are to have the opposite polarities, only the polarity of the signal line drive voltage S [m] needs to be inverted only in the scanning time period, and each reference line drive voltage Com1 , Com2 need not be inverted in the scanning time period. As a result, the liquid crystal display panel 31 is driven by the so-called 1H line inversion driving method, and can significantly reduce power consumption without deteriorating display quality and without increasing the number of manufacturing processes of the liquid crystal display panel 31. it can.
[0053]
Preferably, the polarity of the reference line drive voltages Com1 and Com2 of each wiring group is maintained for the frame time, and the polarity of the reference line drive voltages Com1 and Com2 is reversed each time scanning of all the scanning lines 37 is completed. You. As a result, the polarity of the signal line driving voltage S [m] with respect to the reference line driving voltage at the time of electric field control in the liquid crystal layer 35 of an arbitrary pixel 32 [k, m] is reversed mutually in two consecutive frames. Therefore, the charged charges of the pixel 32 [k, m] in the two consecutive frames have opposite polarities. As a result, the liquid crystal display panel 31 can not only significantly reduce power consumption while preventing a decrease in display quality and an increase in the number of manufacturing processes, but also improve the reliability of display of the liquid crystal display panel 31.
[0054]
FIG. 7 is a waveform diagram showing a temporal change of two frames of various driving voltages applied to the liquid crystal display panel 31 of FIG. 1 when the driving method of the present embodiment is used. FIG. 7A is a waveform diagram of a scanning line driving voltage G [2n-1] applied to a scanning line 37 [2n-1] of an arbitrary 2n-1th row among all odd-numbered rows, and FIG. FIG. 9 is a waveform diagram of a scanning line driving voltage G [2n] applied to an arbitrary 2nth scanning line 37 [2n] of the rows. The waveform of the scanning line driving voltage G [2n] of the 2n-th scanning line is shifted by the scanning time in the time lapse direction from the waveform of the scanning line driving voltage G [2n-1] of the 2n-1-th scanning line. Waveform. FIG. 7B is a waveform diagram of the signal line drive voltage S [m] applied to the signal line 38 [m] of an arbitrary m-th column. FIG. 7C is a waveform diagram of the odd-numbered reference line drive voltage Com1 applied to all the reference lines 39 [1], 39 [3],..., 39 [2N-1] belonging to the odd-numbered line wiring group. is there. FIG. 7D is a waveform diagram of the even-line reference line applied voltage Com2 applied to all the reference lines 39 [2], 39 [4],..., 39 [2N] belonging to the even-numbered wiring group. FIG. 7 shows a case where an upper limit voltage for display is applied to all the pixels 32 [k, m] of the liquid crystal display panel 31 as an example.
[0055]
First, a charge mechanism for the pixels 32 [2n-1, m] in the 2n-1th row in the first frame of the two consecutive frames will be described with reference to FIG. In the first frame, all the active three-terminal elements 36 connected to the 2n-1st scan line only during the period in which the scan line drive voltage G [2n-1] of the 2n-1th scan line remains at the high level. [2n-1, m] is turned on. As a result, during the above-mentioned period, the electric signal flowing through the first path 51 shown in the equivalent circuit diagram of FIG. 2 causes the scanning line 37 [2n-1] in the 2n−1th row and the signal line 38 in the mth column [ m], and the pixel 32 [2n-1, m] at the 2n−1th row and the mth column, which corresponds to the intersection with [m], is charged. The first path is from the m-th signal line 38 [m] to the counter electrode 34 [2n-1, m] and the liquid crystal layer 35 [2n-1, m] of the pixel in the 2n-1 row and m column. An odd-numbered reference line 39 [2n-1] is passed through the electrode 33 [2n-1, m] and the active three-terminal element 36 [2n-1, m] connected to the pixel. . As a result, the electric charge corresponding to the potential difference obtained by subtracting the odd-numbered row reference line driving voltage Com1 from the signal line driving voltage S [m] of the m-th column signal line becomes the pixel 32 [2n− 1, m].
[0056]
As shown in FIG. 7C, if the odd-line reference line drive voltage Com1 in the first frame is at a low level, the pixel 32 [2n- [M] is positive in the applied voltage between the pixel electrode and the counter electrode. While the scanning line driving voltage G [2n-1] of the scanning line in the 2n-1th row is maintained at the high level, pixels 32 [2n-1,1] to [2n-1] at the intersection of the scanning line and each signal line. , M], the pixel charging in the above procedure is executed in parallel.
[0057]
In the first frame, the scanning line driving voltage G [2n] of the 2n-th scanning line is maintained at the high level for the scanning time following the scanning line driving voltage G [2n-1] of the 2n-1-th scanning line. Therefore, each of the pixels 32 [2n, 1] to [2n, M] in the 2nth row is charged by the electric signal flowing through the second path 52 shown in the equivalent circuit diagram of FIG. The second path 52 extends from the signal line 38 [m] in the m-th column to the counter electrode 34 [2n, m] of the pixel at the intersection of the scanning line in the 2n-th row and the signal line in the m-th column, and the liquid crystal layer 35 [ 2n, m] and the pixel electrode 33 [2n, m], and via the active three-terminal element 36 [2n, m] connected to the pixel, to an even-numbered reference line 39 [2n]. Reach. As a result, a charge corresponding to a potential difference obtained by subtracting the reference line driving voltage Com2 for the even-numbered row from the signal line driving voltage S [m] of the signal line in the m-th column is applied to the pixel 32 [2n, m] in the 2n row and m column. Is stored.
[0058]
As shown in FIG. 7D, if the even-line reference line drive voltage Com2 in the first frame is at the high level, the pixel 32 [2n, m] in the 2n row and m column is indicated by the arrow 54. The polarity of the voltage applied between the pixel electrode 33 and the counter electrode 34 is negative. While the scanning line driving voltage G [2n] of the scanning line of the 2nth row is maintained at the high level, the above procedure is performed at each of the intersection pixels 32 [2n, 1] to [2n, M] of the scanning line and each signal line. Are executed in parallel.
[0059]
During the scanning of the first frame, the charging of the pixels 32 [2n−1, m] in the odd-numbered rows in the above procedure and the charging of the pixels 32 [2n, m] in the even-numbered rows in the above procedure are performed by scanning. It is performed alternately at a timing controlled by the line drive voltage G [k]. When the pixel charging is performed for all the scanning lines 37, the scanning of the first frame is completed. As described above, during the scanning of the first frame, the pixels 32 [2n−1, m] belonging to the odd-numbered rows are charged to the plus side when viewed from the odd-numbered reference line drive voltage Com1, and the pixels belonging to the even-numbered rows. 32 [2n, m] is charged to the minus side when viewed from the even-numbered reference line drive voltage Com2. As a result, the reference line drive voltages Com1 and Com2 of the odd-numbered rows and the even-numbered rows each maintain a predetermined level during the scanning of the first frame, but the entire liquid crystal display panel 31 has positive and negative alternating polarities every scanning time. The pixel 32 is charged. Accordingly, in the driving method of the liquid crystal display panel 31 shown in FIG. 7, as shown in FIG. 11, the pixels 32 are alternately charged with a positive polarity and a negative polarity for each row.
[0060]
As described above, in the conventional 1H line inversion driving method, the reference line driving voltage changes in the same cycle as the scanning period. However, in the driving method in FIG. 7, the reference line driving voltage changes in the same cycle as one frame time. Is changing. Thereby, in principle, the power consumption when the liquid crystal display panel 31 of FIG. 1 is driven by the driving method of FIG. 7 is less than the power consumption when the conventional liquid crystal display panel is driven by the conventional 1H line inversion driving method. The power consumption becomes 1 / the number of all scanning lines. Therefore, when the liquid crystal display panel 31 of FIG. 1 is driven by the driving method of FIG. 7, the power consumption of all the counter electrodes 34 and all the signal lines 38, that is, the power consumption of all the signal electrodes 40 is greatly reduced as compared with the related art. .
[0061]
In order to enhance the reliability of the pixel 32, it is preferable that the pixel 32 [k, m] be charged at the time of scanning the second frame with a polarity opposite to that at the time of scanning the first frame. For this reason, the polarities of the odd-line and even-line reference line drive voltages Com1 and Com2 during the scanning of the second frame are respectively reversed from the polarities of the scanning during the scanning of the first frame. As a result, during the scanning of the second frame, the pixels 32 [2n-1, m] belonging to the odd-numbered rows are charged to the negative side when viewed from the odd-numbered reference line drive voltage Com1, and the pixels 32 [2n , M] are charged to the plus side when viewed from the even-line reference line drive voltage Com2.
[0062]
As described above with reference to FIG. 7, in the method of driving the liquid crystal display panel 31 according to the present embodiment, each signal line driving voltage S [m] is applied every time one scanning line 37 [k] is scanned. Are applied, the reference line driving voltages Com1 and Com2 having different polarities for each wiring group are applied to the reference lines 39 divided into the two wiring groups, and maintained for one frame time. Each time the scanning is completed, the polarities of the reference line driving voltages Com1 and Com2 are reversed. As a result, while the liquid crystal display panel 31 is driven by a method equivalent to the 1H line inversion driving method, it is not necessary to invert the reference line driving voltages Com1 and Com2 every scanning time, so that the power consumption of the liquid crystal display panel 31 is reduced. It is possible to provide a liquid crystal display panel 31 that can greatly reduce the display quality and can suppress a slight increase in the manufacturing cost while deteriorating the display quality.
[0063]
The liquid crystal display device having the configuration in which the liquid crystal display panel 31 of FIGS. 1 to 6 is driven by the above-described driving method has a scanning line driving voltage G [k] on each scanning line 37 [k] in addition to the liquid crystal display panel 31. , A common driver for applying the reference line driving voltages Com1 and Com2 for each wiring group to the reference line 39 belonging to each wiring group, and a signal line driving voltage S [for each signal electrode 40 [m]. m], respectively. In the method of driving the liquid crystal display panel 31 of the present embodiment, the scanning line driving voltage G [k] and the signal line driving voltage S [m] are the same as those of the conventional 1H line inversion driving method. Equal to the voltage. As a result, the driving method according to the present embodiment has a smaller fluctuation width of the signal line driving voltage S [m] than the dot inversion driving method according to the prior art, and therefore, the driving method according to the present embodiment uses the dot inversion according to the prior art. The cost of the source driver can be reduced as compared with the driving method. Accordingly, the liquid crystal display panel 31 of the present embodiment driven by a driving method equivalent to the 1H line inversion driving method capable of reducing the cost of the source driver can increase the number of manufacturing steps without deteriorating the display quality. Therefore, the power consumption can be significantly reduced, and the problem of the wiring delay of the reference line 39, which tends to be a problem in large-size and high-definition, can be solved.
[0064]
The liquid crystal display panel 31 of the present embodiment and the method of driving the liquid crystal display panel are examples of the liquid crystal display panel of the present invention and the method of driving the liquid crystal display panel, and can be realized in other various forms as long as the main configurations and operations are the same. . In particular, the detailed configuration of the liquid crystal display panel and the detailed procedure of the driving method of the liquid crystal display panel are not limited to the above-described configuration and procedure as long as the same effect is obtained, and may be realized by other configurations and procedures.
[0065]
That is, in the method of driving the liquid crystal display panel having the opposed signal line structure according to the present invention, the reference line 39TwoA reference line driving voltage that is divided into wiring groups and is different for each wiring group is applied to each of the reference lines 39 belonging to the wiring group.BayoI. SaIn addition, the liquid crystal display panel having the opposed signal line structure of the present invention may be configured such that the reference line 39 is divided into two or more wiring groups and the reference lines 39 are interconnected for each wiring group. May be changed as appropriate. MaThe reference lines 39 are bundled in such a manner that every other reference line 39 is bundled into two wiring groups every other line.To.
[0066]
【The invention's effect】
As described above, according to the present invention, in a method for driving a liquid crystal display panel having a so-called opposed signal line structure, a plurality of reference lines are provided.TwoA signal line drive voltage that belongs to one of the wiring groups and changes polarity in the scanning time period is applied to the signal lines, and a reference line drive voltage having a different polarity for each wire group is applied to the reference line. Thereby, the power consumption of the liquid crystal display panel can be significantly reduced without deteriorating the display quality of the liquid crystal display panel and without increasing the number of manufacturing processes of the liquid crystal display panel.
MaAccording to the present invention, when the reference lines belonging to the two wiring groups are alternately arranged one by one, the polarity of the reference line drive voltage applied to the odd-numbered reference lines is equal to that of the even-numbered reference lines. Are opposite in polarity to the polarity of the reference line driving voltage applied to. As a result, it is possible to further reduce the cost of the driving circuit of the liquid crystal display panel.
SaFurthermore, according to the present invention, the polarity of the reference line drive voltage applied to the reference line belonging to each wiring group is reversed in the same cycle as the frame time. This further improves the reliability of the display of the liquid crystal display panel.
[0067]
Further, as described above, according to the present invention, in the liquid crystal display panel having the opposed signal line structure, a plurality of reference lines are provided.TwoAll the reference lines belonging to any one of the wiring groups and belonging to a single wiring group are interconnected for each wiring group. This makes it easy to apply a different reference line driving voltage to the reference line for each wiring group, and also facilitates the enlargement and high definition of the liquid crystal display panel.
SaFurthermore, according to the present invention, when there are two wiring groups, every other reference line arranged in parallel with the row of pixels is interconnected. This makes it easy to apply different reference line drive voltages to the odd-numbered reference lines and the even-numbered reference lines.
In particular, according to the present invention, it is possible to eliminate a wiring delay that forms a dull waveform due to the resistance and capacitance of the reference line 39.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a schematic configuration of a liquid crystal display panel 31 according to an embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram of a portion corresponding to four pixels of the liquid crystal display panel 31 of FIG.
FIG. 3 is an exploded perspective view showing a configuration of the liquid crystal display panel 31 of FIG.
FIG. 4 is a plan view showing an arrangement of a reference line 39 in the liquid crystal display panel 31 of FIG.
FIG. 5 is an equivalent circuit diagram of a reference electrode in a case where reference lines 39 are interconnected by using auxiliary trunk lines 45 as well as connection trunk lines 44 in the liquid crystal display panel 31 of FIG.
FIG. 6 is a process chart showing a manufacturing process of the liquid crystal display panel 31 of FIG.
FIG. 7 is a waveform chart for explaining a method of driving the liquid crystal display panel 31 of FIG.
FIG. 8 is a schematic diagram showing a schematic configuration of a liquid crystal display panel 31 of the first related art.
9 is an equivalent circuit diagram of a portion corresponding to four pixels of the liquid crystal display panel 1 of FIG.
FIG. 10 illustrates a 1H line inversion driving method which is one of driving methods of the liquid crystal display panel 1 of FIG.
FIG.
11 shows the liquid crystal display panel 1 of FIG. 8 driven by the 1H line inversion driving method of FIG.
FIG. 3 is a diagram showing a state of charge of each pixel in the embodiment.
FIG. 12 is a schematic diagram illustrating a schematic configuration of a liquid crystal display panel according to a second related art.
13 is an equivalent circuit diagram of a portion corresponding to four pixels of the liquid crystal display panel 13 of FIG.
FIG. 14 is a schematic diagram showing a schematic configuration of a liquid crystal display panel 17 of a third conventional technique.
FIG. 15 is a process chart showing a manufacturing process of the liquid crystal display panel 1 of FIG.
[Explanation of symbols]
31 LCD panel
32 pixels
33 pixel electrode
34 Counter electrode
35 liquid crystal layer
36 Active three-terminal element
37 scanning lines
38 signal line
39 Reference line

Claims

A plurality of pixels in which a liquid crystal layer is interposed between a pixel electrode and a counter electrode, each of which is arranged in a matrix , in a display area on the first substrate;
A plurality of active three terminal element 36 having Gate electrode and the source electrode and the drain electrode connected to the pixel electrode, respectively,
Scanning line gate electrodes of the active three-terminal element connected to the pixel electrode of the pixel of one row for each row are connected 37 and,
Reference line 39 which the source electrode of the active three-terminal element connected to the pixel electrode of the pixel of one row for each row is connected is arranged,
On the second substrate, a signal line 38 to which a counter electrode of a pixel for one column is connected for each column is arranged,
A method for driving a liquid crystal display panel in which liquid crystal is interposed between a first substrate and a second substrate ,
All the reference lines are divided into first and second two wiring groups,
In the peripheral area 43 outside the display area 42 on the first substrate,
One end of the reference line of the first wiring group in the longitudinal direction is extended and connected to the first connecting trunk line 44 odd ,
The other end in the longitudinal direction of the reference line of the second wiring group is extended and connected to the second connecting trunk 44 even ,
Each of the first and second connecting trunks 44 odd, 44 even has a line width larger than the reference line 39, and has end portions that also extend to both ends in the reference line width direction in the peripheral region 43,
In the peripheral area 43,
On a first extension part where the other end in the longitudinal direction of the reference line of the first wiring group is extended and the end part of the second connecting trunk 44 even via a first insulating layer, A first auxiliary trunk line 45 odd is provided, and the first auxiliary trunk line 45 odd is connected to the end portion of the first extension portion and the first connection trunk line 44 odd via a contact hole provided in the first insulating layer. Connected directly to
The peripheral area 43 also includes
A second insulating layer is interposed on a second extension part where one end in the longitudinal direction of the reference line of the second wiring group is extended and the end part of the first connection trunk line 44 odd via a second insulating layer. The second auxiliary trunk 45 even is provided, and the second auxiliary trunk 45 even is connected to the second extension portion and the end portion of the second connection trunk 44 even via a contact hole provided in the second insulating layer. Connected directly to
A scanning line driving voltage for turning on the active three-terminal element for a predetermined scanning time for each predetermined frame time is applied to each scanning line, and a signal line driving voltage whose polarity changes in the same cycle as the scanning time is applied. Applied to each signal line,
Reference line drive voltages are predetermined individually for each distribution line group are respectively applied to all the reference lines belonging to each wiring group,
The driving method of the liquid crystal display panel reference line drive voltage applied to each of the reference lines belonging to the respective wiring groups characterized that you change in polarity inversion by Li Kui 1 frame time in the same period differ from one another.

A first substrate having a display area 42 and a peripheral area 43 outside the display area 42;
A second substrate having liquid crystal interposed between the first substrate and the first substrate;
In the display area 42 on the first substrate,
A plurality of pixels each having a liquid crystal layer interposed between the pixel electrode and the counter electrode and arranged in a matrix,
A plurality of active three-terminal elements 36 each having a gate electrode, a source electrode, and a drain electrode connected to the pixel electrode,
A scanning line 37 to which a gate electrode of an active three-terminal element connected to pixel electrodes of pixels of one row for each row is connected;
A reference line 39 to which a source electrode of an active three-terminal element connected to a pixel electrode of a pixel for one row is arranged for each row,
On the second substrate, a signal line 38 to which a counter electrode of a pixel for one column is connected for each column is arranged,
All the reference lines are divided into first and second two wiring groups,
In the peripheral area 43 outside the display area 42 on the first substrate,
One end of the reference line of the first wiring group in the longitudinal direction is extended and connected to the first connecting trunk line 44 odd ,
The other end in the longitudinal direction of the reference line of the second wiring group is extended and connected to the second connecting trunk 44 even ,
Each of the first and second connecting trunks 44 odd, 44 even has a line width larger than the reference line 39, and has end portions extending also at both ends in the reference line width direction in the peripheral region 43,
In the peripheral area 43,
On a first extension part where the other end in the longitudinal direction of the reference line of the first wiring group is extended and the end part of the first connecting trunk 44 odd via a first insulating layer, A first auxiliary trunk line 45 odd is provided, and the first auxiliary trunk line 45 odd is connected to the end portion of the first extension portion and the first connection trunk line 44 odd via a contact hole provided in the first insulating layer. Connected directly to
The peripheral area 43 also includes
A second insulating layer is formed on a second extension portion at which one end in the longitudinal direction of the reference line of the second wiring group is extended and the end portion of the second connecting trunk wire 44 even via a second insulating layer. The second auxiliary trunk 45 even is provided, and the second auxiliary trunk 45 even is connected to the second extension portion and the end portion of the second connection trunk 44 even via a contact hole provided in the second insulating layer. Connected directly to
A scanning line driving voltage for turning on the active three-terminal element for a predetermined scanning time for each predetermined frame time is applied to each scanning line, and a signal line driving voltage whose polarity changes in the same cycle as the scanning time is applied. Applied to each signal line,
A reference line drive voltage that is individually predetermined for each wiring group is applied to all the reference lines belonging to each wiring group,
A liquid crystal display panel characterized in that reference line driving voltages applied to reference lines belonging to each wiring group are different from each other and are given by changing the polarity in reverse with the same cycle as one frame time .