JPH0635417A - Method for driving active matrix type thin film transisitor liquid crystal panel - Google Patents

Abstract

PURPOSE:To make the mean effective voltage of a liquid crystal cell uniform and to lower the dielectric strength of switching drivers for gate bus lines and drain bus lines. CONSTITUTION:The group of pixel electrodes 14 which are connected via thin film transistors(TR) 13 is arranged zigzag alternately in the direction of gate bus lines 11 to constitute the group of pixel electrodes 14 in the direction of two adjacent gate bus lines 11, one counter electrode 15 and a switching circuit are provided on the group of pixel electrodes 14 and the respective drain bus lines 12 are supplied with voltage signals inverted in polarity at the intervals of one scanning line period. Each counter electrode 15 is supplied with polarity data on the group of pixel electrodes 14 corresponding to the counter electrode 15, which vary in synchronism with the write timing of the selected gate bus line 11 and a voltage signal including an offset voltage and an effective voltage correction voltage corresponding to the threshold voltage of liquid crystal and voltage writing to each pixel electrode 14 is performed with the selective signal of the gate bus lines 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving an active matrix type thin film transistor liquid crystal panel.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, Journal of Television Society Vol. 42, No.
1, P. 10-16 and P.I. 23-29. Conventionally, an active matrix type liquid crystal panel, especially one using a thin film transistor (TFT-L
As a driving method of (CD), several kinds of different methods are used depending on the method of alternating current, but the concept of the voltage supply method is the same. Therefore, as a typical example, a driving method (hereinafter, referred to as a frame mode) for performing alternating current for each scanning cycle will be described.

FIG. 13 is a block diagram of such a conventional active matrix type thin film transistor liquid crystal panel, and FIG. 14 is a drive timing chart thereof. As shown in the figure, the active matrix thin film transistor liquid crystal panel is
Generally, a gate bus line 51 and a drain bus line 52 are arranged orthogonally on a rear substrate, and a thin film transistor (TFT) 53 is provided as a switching element corresponding to each pixel electrode at an intersection thereof, and a transparent counter electrode is provided on a front substrate. 54 is provided, an alignment film that has been subjected to an alignment treatment in an appropriate direction is provided on the surfaces of both substrates, the alignment films of both substrates are opposed to each other with a liquid crystal layer in between, and are bonded together, and on the back surfaces of the front substrate and the back substrate, A structure in which polarizing films are attached so that their polarization axes are parallel or perpendicular to each other, and a portion sandwiched between both electrodes due to a potential difference between the voltage of the pixel electrode supplied through the TFT 53 and the voltage of the counter electrode 54. The liquid crystal 55 is switched.

Also, as a switching means of the TFT 53
Then, the scanning circuit 60 is connected to the gate bus line 51.
The data circuit 70 is connected to the bus line 52.
O from the scanning circuit 60 as a gate selection signal of the TFT 53
N voltage V_{G (+)}, OFF voltage V _{G (-)}But the drain of TFT53
The data circuit 70 is used as an in-selection and brightness data signal.
Write voltage V of positive polarity_{D (+)}, Negative write voltage
V_{D (-)}Is supplied.

Further, as shown in FIG. 14, the voltage V _S of the pixel electrode written by the TFT 53 causes a voltage fluctuation twice in the voltage holding state. First, TFT
When the gate selection signal of 53 changes from the ON state to the OFF state, the voltage V _{S of the} pixel electrode connected to the TFT 53 to which the selection signal is supplied changes by ΔV ₁ due to the parasitic capacitance C _gS of the _TFT 53. To do.

Secondly, when the data signal changes to a polarity opposite to the polarity at the time of writing, it changes by ΔV ₂ due to the electric field effect between the pixel electrode and the drain bus line 52.
For this reason, the potential difference between the pixel electrode and the counter electrode is equalized to the counter electrode so that the positive polarity writing and the negative polarity writing are even with respect to the fluctuation of the voltage V _S of the pixel electrode. The voltage V _COM is supplied.

FIG. 15 shows the electro-optical characteristics of the TN liquid crystal cell in the case where the two polarizing films are attached so that their polarization axes are parallel to each other. The TN liquid crystal cell used in the active matrix thin film transistor liquid crystal panel is
With respect to the potential difference between the pixel electrode and the counter electrode, there is a threshold voltage V _{TH at} which the light transmittance sharply increases and a saturation voltage V _{SAT at} which the fluctuation of the light transmittance disappears, and a voltage range ΔV of V _{TH to} V _SAT.
In, the voltage fluctuation indicates a change in light transmittance. Therefore, in order to achieve a complete ON state, V _SAT <V _S −V _{COM in} the positive polarity and V _SAT <V in the negative polarity.
_To set a voltage condition of _COM- V _S and achieve a complete OFF state, a voltage condition of V _TH > V _S −V _{COM in} the positive polarity and V _TH > V _COM −V _{S in} the negative polarity is set. By setting, the liquid crystal cell can be switched.

[0008]

However, in the above-mentioned conventional driving method of the active matrix type liquid crystal panel, the time from the writing of the data signal to the pixel electrode to the reversal of the voltage polarity of the drain bus line. Are different from each other, for example, in the first gate bus line and the Nth gate bus line selected by the scanning circuit,
The voltage V _{S of the} pixel electrode connected through each TFT
Comparing with each other, the electric field effect between the pixel electrode and the drain bus line changes the period in which the voltage changes by ΔV ₂ , so that the average effective voltage applied to the liquid crystal layer for each scanning period differs, and the difference in light transmittance varies. Occur.

Further, for the switching of the liquid crystal layer, it is sufficient to generate a voltage fluctuation of ΔV between the pixel electrode and the counter electrode, but the voltage of the counter electrode is fixed and the voltage of the pixel electrode is positive. In order to change to a negative polarity, the driver of the drain bus line requires a switching voltage of V _SAT × 2 [corresponding to (V _TH + ΔV) × 2], and ΔV + V _TH ×
2 extra switching voltage is needed,
This has been an obstacle to lowering the breakdown voltage of the driver.

The object of the present invention is to disperse the average effective voltage applied to the liquid crystal layer for each scanning period and the extra switching voltage V _TH × 2 + Δ applied to the drain bus line.
In order to reduce or eliminate V, pixel electrode groups connected to one gate bus line via TFTs are alternately arranged in a staggered pattern in the gate bus line direction, and two pixel electrode groups arranged in the gate bus line direction are arranged. The counter electrodes are arranged corresponding to each pixel electrode group arranged in the gate bus line direction, and adjacent drain bus lines exhibit different polarities, and each counter electrode is arranged in each scanning line cycle. By the alternating method that reverses the polarity of
The average effective voltage is eliminated from variations, and the positive and negative polarity data supplied to each drain bus line is supplied as voltage information that is inverted from each other, and each counter electrode has an equal voltage amplitude. However, it is another object of the present invention to provide a driving method of an active matrix type thin film transistor liquid crystal panel, which is capable of compensating a writing voltage by the voltage amplitude and achieving a low breakdown voltage of a switching driver of a drain bus line and a gate bus line.

Another object of the present invention is to disperse the average effective voltage applied to the liquid crystal layer in each scanning cycle as described above.
Extra switching voltage V on drain bus line
_In order to reduce or eliminate _TH × 2 + ΔV, a pixel electrode group connected to one gate bus line via a TFT is arranged in the line direction, and connected to two adjacent gate bus lines via a TFT. In the pixel electrode group, one wavy counter electrode is provided for the pixel electrode group selected from the two gate bus lines alternately in the gate bus line direction, and the adjacent drain bus lines are By the alternating method that shows different polarities and the polarities are inverted every scanning line cycle, the variation of the average effective voltage is eliminated, and the positive polarity data and the negative polarity data supplied to each drain bus line are mutually inverted. The data structure that is supplied as the voltage information is set so that each counter electrode has the same voltage amplitude, and the write voltage is compensated by the voltage amplitude, It is an object of the present invention to provide a method for driving an active matrix type thin film transistor liquid crystal panel, which achieves a low breakdown voltage of the in and gate bus lines.

[0012]

In order to achieve the above object, the present invention provides a gate bus line and a drain bus line which are arranged orthogonally on a back substrate, and which is provided at the intersection of the gate bus line and the drain bus line. A thin film transistor is provided corresponding to each pixel electrode, a transparent counter electrode is provided on the front substrate, alignment films that are oriented in appropriate directions are provided on the surfaces of the back substrate and the front substrate, and the alignment films of both substrates are provided. In a method for driving an active matrix type thin film transistor liquid crystal panel, in which the two are opposed to each other with a liquid crystal layer interposed therebetween, and a polarizing film is attached to the back surface of the back substrate and the front substrate, a thin film transistor is provided to one gate bus line. Pixel electrode groups connected to each other are alternately arranged in a zigzag pattern in the gate bus line direction to correspond to two adjacent gate bus lines. Partial pixel electrodes form a pixel electrode group in the gate bus line direction, one counter electrode is provided for the pixel electrode group arranged in the gate bus line direction, a circuit for switching each counter electrode is provided, and an adjacent drain bus is provided. Each drain bus line outputs a voltage signal indicating a voltage in which the polarities of the voltage data of the lines are different and the polarities of the voltage data are inverted every scanning line cycle, and the positive and negative polarities of the voltage data are inverted from each other. Of the two adjacent gate bus lines connected to the pixel electrodes corresponding to the respective counter electrodes via the thin film transistors, the gate bus lines fluctuate in synchronization with the write timing of the gate bus line selected first, and A voltage signal including polarity data of the pixel electrode group corresponding to the counter electrode, an offset voltage corresponding to the threshold voltage of liquid crystal, and an effective voltage correction voltage. It is supplied to the counter electrodes, in which to perform the voltage written to each pixel electrode by supplying a selection signal to the gate bus line.

Pixel electrode groups connected to one gate bus line via thin film transistors are arranged in the gate bus line direction, and pixel electrode groups connected to two adjacent gate bus lines via thin film transistors. In, in the zigzag pattern alternately in the gate bus line direction, one corrugated counter electrode is provided for the pixel electrode group selected from two gate bus lines, and a circuit for switching each corrugated counter electrode is provided. The polarity of the electrode data of the adjacent drain bus lines is different, the polarity of the voltage data is inverted every scanning line period, and the voltage signal indicating the voltage in which the voltage data of positive polarity and the voltage data of negative polarity are inverted from each other is generated. It is supplied to the drain bus line and is connected to the pixel electrode corresponding to each counter electrode through two thin film transistors, which are adjacent to each other. , A voltage including an offset voltage and an effective voltage correction voltage that vary in synchronization with the write timing of the previously selected gate bus line and that corresponds to the polarity data of the pixel electrode group corresponding to each counter electrode and the threshold voltage of the liquid crystal. A signal is supplied to each counter electrode and a selection signal is supplied to the gate bus line to write a voltage in each pixel electrode.

[0014]

According to the present invention, as described above, the pixel electrode groups connected to one gate bus line via the TFT are alternately arranged in the gate bus line direction in a zigzag pattern, and the pixel electrode groups are arranged in the gate bus line direction. The pixel electrode group arranged side by side is configured to be controlled by two gate bus lines, and each counter electrode is provided corresponding to each pixel electrode group arranged in the gate bus line direction,
Adjacent drain bus lines show different polarities,
The alternating method in which the polarities are inverted every scanning line cycle eliminates the variation in the average effective voltage applied to the liquid crystal layer, and the positive and negative data supplied to each drain bus line are mutually inverted. It is possible to eliminate an extra switching voltage applied to the drain bus line by adopting a data structure which is supplied as voltage information and having the same voltage amplitude on each counter electrode and compensating the write voltage by the voltage amplitude.

Alternatively, one gate bus line may be provided with TF.
Pixels in which pixel electrode groups connected via Ts are arranged in the line direction, and the pixel electrode groups connected to two adjacent gate bus lines via TFTs are alternately selected in a staggered pattern in the gate bus line direction. A structure is provided in which one corrugated counter electrode is provided for the electrode group, and adjacent drain bus lines have different polarities, and the polarity is inverted in each scanning line cycle, and applied to the liquid crystal layer by an alternating method. Eliminating the variation in the average effective voltage, and adopting a data structure in which the positive and negative polarity data supplied to each drain bus line are supplied as voltage information that is inverted from each other, and have the same voltage amplitude on each counter electrode. However, by supplementing the write voltage with the voltage amplitude, an extra switching voltage applied to the drain bus line can be eliminated.

Therefore, it is possible to make the average applied voltage to the liquid crystal cell uniform and to reduce the withstand voltage of the switching driver of the gate bus line and the drain bus line. Further, this driving method can obtain the same effect even when an analog voltage is input to the drain bus line, and thus can be sufficiently applied to the grayscale driving of the active matrix thin film transistor liquid crystal panel.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a schematic perspective view of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention. As shown in this figure, a gate bus line 11 and a drain bus line 12 are formed on a transparent rear substrate.
And are orthogonally arranged, and the TFT 13 is provided at the intersection of
It connects to the transparent pixel electrode 14 corresponding to an individual display cell. Pixel electrode groups connected to one gate bus line 11 via the TFT 13 are alternately arranged in a zigzag pattern in the gate bus line direction, and two adjacent gate bus lines 11 form a line in the gate bus line direction. The pixel electrode groups arranged in a line are configured to be switched. Further, an alignment film that has been subjected to an alignment treatment in an appropriate direction is provided on the back substrate.

On the other hand, the transparent counter electrode 1 is divided into the same number of lines as the pixel electrode group on the transparent front substrate.
5 is provided to provide an alignment film that has been subjected to an alignment treatment in an appropriate direction. The alignment films of the back substrate and the front substrate are opposed to each other, the pixel electrode group arranged in a line and one counter electrode are aligned so as to face each other, and an appropriate gap is provided between both substrates. After injecting liquid crystal, it is sealed and a polarizing film is attached to the exposed surfaces of both substrates so that their polarization axes are parallel or perpendicular to each other. Reference numeral 15a is a portion facing the pixel electrode.

FIG. 2 is a schematic configuration diagram of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention,
FIG. 3 is a schematic block diagram of a data circuit of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention, and FIG. 4 shows voltage data supplied to a drain bus of the active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention. FIG. 4 is a diagram showing timing, and FIG.
(A) is a voltage waveform diagram of the odd drain bus, FIG.
(B) is a voltage waveform diagram of the even drain bus. FIG. 5 is a schematic block diagram of a common variation circuit of an active matrix thin film transistor liquid crystal panel showing an embodiment of the present invention.

As shown in these figures, the gate line 1
When the number of 1s is N + 1 and the number of drain bus lines 12 is M, the scanning circuit 20 is connected to N + 1 gate bus lines 11.
And the ON voltage V _{G (+)} ′ is sequentially supplied from the first gate bus line 11 for a time t _on corresponding to one scanning time, and the data generator 3 is supplied to the M drain bus lines 12.
1. A data circuit 30 including a data inversion unit A32, a data inversion unit B33, a data output unit A34, and a data output unit B35 is connected to supply voltage data including brightness data and polarity data, and N counter electrodes. There are two groups of shift register units A41, shift register unit B44, voltage amplification units 42 and 45, driver unit A43, and driver unit B46.
Is connected to the common variable circuit 40, and a voltage signal including polarity data corresponding to the voltage data supplied to the drain bus line 12 and an offset voltage corresponding to the threshold voltage of the liquid crystal 16 and an effective voltage correction voltage is supplied. .

As shown in FIG. 4, in this embodiment, one gate bus line 11 switches the pixel electrodes 14 alternately arranged in a zigzag pattern in the gate bus line direction. In the line 11 and the (N + 1) th gate bus line 11, T connected to the even-numbered pixel electrodes in the gate bus line direction, respectively.
Only the TFTs connected to the FT and the odd-numbered pixel electrodes are switched. Therefore, when writing one frame of image data, the odd-numbered pixel electrode groups in the gate bus line direction are written from the second gate bus line to the (N + 1) th gate bus line at the write timing.
Further, voltage data must be supplied from the drain bus lines to the even-numbered pixel electrode groups in the gate bus line direction at the write timing of the first gate bus line to the Nth gate bus line.

Therefore, the data generator 3 of the data circuit 30
1, the luminance data of one line is divided into the data of the odd-numbered display cells and the data of the even-numbered display cells in the gate bus line direction, and the first gate is used as the data of the odd-numbered display cells in the gate bus line direction. As the data corresponding to the bus line, the dummy data d _D , the data d ₁ of the first line as the data corresponding to the second gate bus line, and the data d ₂ of the second line as the data corresponding to the third gate bus line Is the data 1 that sequentially supplies the data d _N of the Nth line as the data corresponding to the (N + 1) th gate bus.

As the data of the even-numbered display cells in the gate bus line direction, the data d ₁ of the first line as the data corresponding to the first gate bus line and the two lines of the data as the data corresponding to the second gate bus line. The data d ₂ of the eye, the data d _N of the Nth line as the data corresponding to the Nth gate bus line, and the data 2 that sequentially supplies the dummy data d _D as the data corresponding to the (N + 1) th gate bus line. create.

In the data generator 31, the odd-numbered drain buses and the even-numbered drain buses have different write polarities and correspond to the odd-numbered drain buses as an AC signal whose polarity is inverted for each scanning line. An alternating signal 1 and an alternating signal 2 corresponding to an even-numbered drain bus are created. The data 1 and the alternating signal 1 are calculated by the data inverting unit A32 to create voltage data and data 3 including the brightness data and the polarity data, and the data output unit A3.
4, the odd-numbered drain buses D ₁ , D ₃ , ...,
Output to D _M-1 . Similarly, data 2 and AC signal 2 are
Calculated by the data inversion unit B33, creates voltage data comprising luminance data and polarity data, the data 4, the data output unit B35, an even-numbered drain bus D _2,
Output to D ₄ , ..., D _M.

The voltage data setting conditions for each drain bus output from the data circuit 30 are as follows: ON voltage V _{D (+)} ', OFF voltage V _{D (-)} ' in negative polarity, and negative polarity in positive polarity writing. ON voltage V in writing
_{Since D (-)} 'and OFF voltage V _{D (+)} ' are set, the voltage amplitude can be set to be equal to ΔV shown in FIG. 15, and V _{D (+)} '-V
_Since it is given under the condition of _{D (-)} '= V _SAT -V _TH = ΔV,
Compared with the conventional example of FIG. 14, the amplitude of the drain voltage is V _TH
It can be reduced by × 2 + ΔV.

FIG. 6 shows an operation timing chart 1 of the common variation circuit of the active matrix type thin film transistor liquid crystal panel showing the embodiment of the present invention, and FIG. 7 shows an operation timing chart 2 of the common variation circuit. In the present invention, instead of setting the amplitude of the drain voltage to be equal to ΔV, a voltage such as an offset voltage of the liquid crystal is supplied by the voltage signal of the counter electrode. Therefore, an offset voltage of the write polarity of the even drain bus line is written to the first counter electrode at the write timing of the first gate bus line, and an offset voltage of the odd drain bus line is written at the write timing of the second gate bus line. A voltage signal for supplementing the offset voltage of the write polarity, etc., and the offset voltage of the write polarity of the even drain bus is supplied to the second counter electrode at the write timing of the second gate bus line. At the write timing of the third gate bus line, a voltage signal for supplementing the offset voltage or the like of the write polarity of the odd drain bus is supplied, and the voltage signal is similarly supplied to the Nth counter electrode.

Since the polarities of the odd-numbered drain bus and the even-numbered drain bus are different at the same write timing, and the polarities thereof are inverted at the next write timing, the corresponding pixel electrodes correspond to the respective pixel electrodes. Among them, a voltage signal that changes in synchronization with the writing timing of the pixel electrode connected to the even drain bus via the TFT is supplied.

Therefore, in the circuit configuration of the two systems, in the shift register section A41, as shown in FIG. 6, the voltage fluctuates immediately before the ON voltage of the first gate bus line is applied and the shift voltage of the first gate bus line is changed. The signal DF1 having the polarity data of the even-numbered pixel electrodes in the line direction and the clock Φ _C synchronized with the rising of the ON voltage application of each gate bus line and having a period of t _on time corresponding to one scanning time are provided. Waveform D supplied and sequentially delayed by two clocks from D _C1
C3 , D _C5 , ..., D _CN-1 are created, this is supplied to the voltage amplifying section, and R ₂ / R _{1 is set} by the operational amplifier and the resistors R ₁ and R _2.
Double inversion amplification is performed to create a voltage signal having a predetermined voltage amplitude including the offset voltage and the polarity correction voltage when the gate bus is selected, and the first counter signal is provided via the protection resistor R ₃ and the driver unit A43. The voltage signal V _COM1 is supplied to the electrodes, the voltage signal V _COM3 is supplied to the third counter electrode, and the voltage signal V _COMN-1 is supplied to the (N-1) th counter electrode.

Further, as shown in FIG. 7, the shift register B44 changes immediately before the ON voltage is applied to the first gate bus line, and the even-numbered pixel in the line direction of the second gate bus line. The signal DF2 having the polarity data of the electrodes and the clock Φ _C synchronized with the rising of the ON voltage application to each gate bus line and having the synchronization of the _on time are supplied, and are delayed by one clock from D _C1 in FIG. create a waveform D _C2 was further D _C2 than sequentially delayed waveform by two clocks min D _C4, D _C6 ..., create a D _CN, which was supplied to the voltage amplifier, an operational amplifier and resistors R _1, R ₂ By R ₂
/ R ₁ times inverting amplification is performed to create a voltage signal having a predetermined voltage amplitude including the offset voltage and the polarity correction voltage when the gate bus is selected, and the protection resistor R ₃ and the driver unit B46.
Through, a voltage signal V _COM1 to the second counter electrode, a voltage signal V _{CO M4} in the fourth counter electrode, respectively supply voltage signal V _COMN to the N-th counter electrode.

The V _COM1 , V _COM2 ,
, V _COMN may supply a voltage signal having an equivalent voltage amplitude, so that a binary output drain driver can be applied to the common variation circuit. FIG. 8 is an equivalent circuit diagram of a liquid crystal cell showing an embodiment of the present invention. In the case of the driving method described above, the fluctuation of the effective voltage in the charge holding state of the liquid crystal cell occurs under at least three conditions.

First, immediately after writing to the TFT connected to the pixel electrode, the parasitic capacitance C _gs of the TFT causes ΔV ₁ ′ =
[C _gs / (C _gs + C _LC )] × (V _{G (+)} ′ −
V _{G (−)} ′), and then the two drain bus lines 12 sandwiching the pixel electrode are ΔV _D1 ′ and Δ from the voltage at the time of writing.
When it changes by V _D2 ′, Δ due to the capacitances C _DP1 and C _DP2 between the pixel electrode and the two drain bus lines 12.
V ₂ ′ = (C _DP1 / C _LC ) × ΔV _D1 ′ − (C _DP2 /
C _LC ) × ΔV _D2 ′, and when the voltage of the counter electrode for accumulating charges with the pixel electrode changes by ΔV _COM ,
Due to the parasitic capacitance C _gs of the TFT 13, ΔV ₃ ′ = [C _gs /
(C _gs + C _LC )] × ΔV _COM .

Further, the potential variation ΔV ₁ ′ is of the same polarity and the same potential regardless of the write voltage and the write timing if the same TFT is formed in all the pixel electrodes, and therefore the potential variation ΔV ₁ ′ is supplied to the counter electrode. In setting the voltage to be set, the same effective voltage can be maintained in all the liquid crystal cells by shifting the setting by ΔV ₁ ′.

Further, the potential fluctuations ΔV ₂ ′ and ΔV ₃ ′ have different polarities of the effective voltage fluctuation depending on the polarities at the time of writing, and the fluctuation amount depends on the polarities of the two drain buses sandwiching the pixel electrode and the counter electrode. The largest voltage fluctuation is shown at the time of writing and when changing. Therefore, in each pixel electrode, if there is a short period and a long period during which the polarities of the two are changed with respect to the polarities at the time of writing, the average effective voltage is different, and display unevenness occurs.

FIG. 10 is a timing chart showing changes in driving voltage and pixel voltage of the TFT connected to the odd drain bus line showing the embodiment of the present invention, and FIG. 11 is connected to the even drain bus showing the embodiment of the present invention. 6 is a timing chart showing a drive voltage of a TFT and a pixel voltage change. Therefore, in this embodiment, the voltage signals V _COM1 , V _COM2 , ..., V _COMN supplied to the counter electrodes are set by _shifting the voltage variation amount ΔV ₁ ′, and the polarity of each drain bus line is 1. Since AC drive is performed to invert the polarity in the line cycle, the period during which the polarities of the two drain buses sandwiching the pixel electrode are the same as that during writing is the same for all pixel electrodes, and the average effective voltage is the same. Is uniform.

The polarity of the counter electrode with respect to each pixel electrode is different from that at the time of writing with respect to the pixel electrode connected to the odd drain bus line through the TFT.
It occurs only for a time of T × (1 / N + 1) and does not occur for the pixel electrode connected to the even drain bus line via the TFT. Therefore, the fluctuation of the average effective voltage due to the influence of ΔV ₃ ′ is ignored. It will be good enough.

Further, in consideration of the above, the voltage signals of V _COM1 , V _COM2 , ..., V _COMN supplied to the counter electrodes are _expressed by Δ in all pixel electrodes calculated from the display data.
The voltage waveform of V _COM1 , V _COM2 , ..., V _COMN is of a positive polarity in order to additionally supply the average voltage fluctuation amount of V ₂ ′ -ΔV ₂ ′ as the effective voltage loss caused by the voltage fluctuation of ΔV ₂ ′. At the time of writing, V _{D (+)} '-ΔV-V _TH -Δ
At the voltage level of V ₁ ′ − (− ΔV ₂ ′), at the time of writing with negative polarity, V _{D (−)} ′ + ΔV + V _TH −ΔV ₁ ′ + (−
ΔV + 2V _TH +2 set to the voltage level of ΔV ₂ ′)
By supplying a voltage signal having a fluctuation amplitude of × (−ΔV ₂ ′), even when the amplitude of the voltage data output from the data circuit is set to ΔV, the average effective voltage of all pixels is ΔV + V _TH . It can be the same level. Similarly, the amplitude of the gate voltage can be reduced to the same extent as the amplitude of the drain voltage is reduced.

FIG. 9 shows an equivalent circuit diagram of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention. As shown in FIGS. 1 and 2, the active matrix type thin film transistor liquid crystal panel is provided with a large number of electrical wirings. Therefore, there is a wiring capacitance as a constituent condition of the liquid crystal panel, and a liquid crystal capacitance C of each display cell is present. _A loss current is generated when writing to _LC . The capacitance C _GD created by the intersection of the drain bus line 12 and the gate bus line 11 is the voltage variation amount of the drain bus line 12 between the gate bus line 11 and the drain bus line 12 each time the voltage of the drain bus line varies. And a capacitance C _DC generated between the drain bus line 12 and the counter electrode 15 via the liquid crystal layer.
Similarly, each time the voltage of the drain bus line 12 changes, a loss current proportional to the amount of voltage change of the drain bus 12 is generated in the drain bus line 12 and the counter electrode 15.

C shown in each display cell unit shown here
Without large so much amount of current generated by _GD and C _DC, for considering the whole wire is fairly large current, short duration loss current, in order to release, for example, in line periods outside the panel, the drain bus It is necessary to reduce the resistance of the line 12, the gate bus line 11, and the counter electrode 15, and increase the current capacity of the external driver connected to each wiring.

In the embodiment of the present invention, when the polarities of the adjacent drain buses are different and the polarities are changed, the voltage fluctuations of the adjacent drain buses are always different polarities, for example,
When one changes from the positive polarity to the negative polarity, the other changes from the negative polarity to the positive polarity. Therefore, the loss currents generated by the adjacent capacitances C _GD or by the capacitances C _DC adjacent to each other on one counter electrode divided for each line are currents flowing in opposite directions. Tend to cancel out.

Therefore, the loss current flowing through one gate bus line and drain bus line and the counter electrode divided for each line becomes very small, and the resistance of each wiring is reduced and each wiring is connected to each wiring. It is possible to provide a liquid crystal panel that does not need to increase the capacity of an external driver, and is suitable for increasing the capacity and definition of the liquid crystal panel. Figure 1
2 is a schematic configuration diagram of an active matrix thin film transistor liquid crystal panel showing a modified embodiment of the present invention. The same parts as those in the above-mentioned embodiment are designated by the same reference numerals, and the description thereof will be omitted.

In this embodiment, the liquid crystal capacitance C _LC between each pixel electrode and the counter electrode of the active matrix type thin film transistor liquid crystal panel having the configuration described in detail with reference to FIGS. Auxiliary capacitance C _s 17 in parallel
Is provided and connected to the common fluctuation circuit 40 by the auxiliary capacitance line 18, the fluctuation amount of the effective voltage in the charge holding state of the liquid crystal cell is ΔV ₁ ″ = [C _gs / (C _gs
+ C _LC + C _s )] × (VG ₍₊₎ '-VG _(-) '), ΔV
₂ ″ = (C _DP1 / C _LC + C _s ) × ΔV _D1 ′ − (C _DP2 /
C _LC + C _s ) × ΔV _D2 ′, ΔV ₃ ″ = [C _gs / (C _gs +
C _LC C _s )] × ΔV _COM .
By this effect, V _COM1 , which is supplied to the counter electrode,
By reducing the correction voltage and the voltage amplitude of V _COM2 , ..., V _COMN , the voltage amplitude supplied to the gate bus line can be easily reduced.

FIG. 16 is a schematic perspective view of an active matrix type thin film transistor liquid crystal panel showing another embodiment of the present invention. As shown in this figure, a gate bus line 11 and a drain bus line 12 are arranged orthogonal to each other on a transparent rear substrate, and TFTs 13 are provided at the intersections of the gate bus lines 11 and the drain bus lines 12 to form transparent pixel electrodes corresponding to individual display cells. Connect to 14,
A group of pixel electrodes connected to one gate bus line via the TFT 13 is arranged in the line direction, and an alignment film subjected to an alignment treatment in an appropriate direction is provided. In addition, 19 is a gap.

On the other hand, from the pixel electrode groups connected via the TFT 13 to the two adjacent gate bus lines on the transparent front substrate, the pixel electrode groups selected alternately in the gate bus line direction in a zigzag manner. One transparent corrugated counter electrode 15 is provided, a plurality of corrugated counter electrodes are provided, and an alignment film that has been subjected to an alignment treatment in an appropriate direction is provided. The alignment films of the back substrate and the front substrate are faced to each other and aligned, an appropriate gap is provided between both substrates, liquid crystal is injected and sealed, and the polarization axes are parallel to each other on the exposed surfaces of both substrates. A polarizing film is attached so as to be vertical. FIG. 17 is a view showing the structure of the counter electrode of the active matrix thin film transistor liquid crystal panel showing the embodiment of the present invention.

As shown in the figure, the corrugated counter electrodes are pixel electrodes selected in a zigzag pattern alternately in the gate bus line direction from a pixel electrode group connected to two adjacent gate bus lines via the TFT 13. In order to provide one transparent counter electrode for the group, the pattern configuration 1 of FIG.
As shown in FIG. 3, the gate bus lines are formed so as to straddle two adjacent gate bus lines. For this reason, in the pattern configuration 1, when the pixel pitch is made finer, the junction extending over the two gate bus lines becomes thin, the electrical resistance value increases, and a potential difference is generated to the extent that display unevenness can be recognized. there's a possibility that. In the pattern configuration 2 of FIG. 17B, the counter electrode bonding portion 15b is made of aluminum or the like having a low electric resistance value, so that the pixel pitch can be miniaturized. Here, 15a is a portion facing the pixel electrode.

FIG. 18 is a schematic configuration diagram of an active matrix type thin film transistor liquid crystal panel of another embodiment of the present invention. The data circuit of the active matrix type thin film transistor liquid crystal panel is similar to that shown in FIG. 3 and is not shown here. FIG. 19 is a diagram showing the timing of the voltage data supplied to the drain bus of the active matrix type thin film transistor liquid crystal panel of another embodiment of the present invention, and FIG. 19 (a) is a voltage data waveform diagram of the odd drain bus line. 19B is a voltage data waveform diagram of the even drain bus line. FIG. 20 is a diagram showing a common variation circuit of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention.

As shown in these figures, the gate line 1
When the number of 1s is N and the number of drain bus lines 12 is M, the scanning circuits 20 are connected to the N gate bus lines 11, and the first gate bus lines 11 are turned on sequentially in time.
The voltage V _{G (+)} ′ is supplied for a time t _on corresponding to one scanning time,
A data circuit 30 including a data generation unit 31, a data inversion unit A32, a data inversion unit B33, a data output unit A34, and a data output unit B35 is connected to the M drain bus lines 12 and includes brightness data and polarity data. Voltage data is supplied, and two systems of shift register unit A41 and shift register unit B44 are provided to the counter electrode group divided into N + 1 pieces.
And a common variation circuit 40 composed of a voltage amplification section 42, 45, a driver section A43, and a driver section B46,
A voltage signal including polarity data corresponding to the voltage data supplied to the drain bus line 12 and an offset voltage corresponding to the threshold voltage of the liquid crystal 16 and an effective voltage correction voltage is supplied.

As shown in FIG. 19, in this embodiment, in the data generation section 31 of the data circuit 30, the luminance data of one line of the drain bus is line-wise directed to the data of the odd-numbered display cells and the even-numbered display cells. The data is divided into display cell data, data 1 and data 2 are created, and the polarity of writing on the odd drain bus line and the even drain bus line is different, and the polarity is inverted for each line of the drain bus. An alternating signal 1 corresponding to the odd-numbered drain buses and an alternating signal 2 corresponding to the even-numbered drain buses are created.

The data 1 and the alternating signal 1 are transferred to the data inversion unit A.
32, voltage data including brightness data and polarity data, and data 3 are created, and are output to the odd-numbered drain buses D ₁ , D _3, ..., D _M-1 by the data output unit A34. Similarly, the data 2 and the AC signal 2 are calculated by the data inversion unit B33 to create voltage data and data 4 including the brightness data and the polarity data, and the data output unit B35 outputs even-numbered drain buses D ₂ , D. ₄ ..., Output to D _M.

The voltage data setting conditions for each drain bus output from the data circuit 30 are as follows: ON voltage V _{D (+)} ', OFF voltage V _{D (-)} ' in negative polarity, and negative polarity in positive polarity writing. In writing, since the ON voltage V _{D (-)} 'and the OFF voltage V _{D (+)} ' are set, the voltage amplitude can be set to be equal to ΔV shown in FIG. 15, and V _{D (+)} '-V
_Since it is given under the condition of _{D (-)} '= V _SAT -V _TH = ΔV,
Compared with the conventional example of FIG. 14, the amplitude of the drain voltage is V _TH ×
It can be reduced by 2 + ΔV.

FIG. 21 is a first timing chart of a common variation circuit of an active matrix type thin film transistor liquid crystal panel showing another embodiment of the present invention, and FIG. 22 is an active matrix type thin film transistor showing another embodiment of the present invention. The 2nd timing chart of the common variation circuit of a liquid crystal panel is shown. In this embodiment, instead of setting the amplitude of the drain voltage to be equal to ΔV, a voltage such as an offset voltage of the liquid crystal is supplied by the voltage signal of the counter electrode. Since each counter electrode is arranged as described in detail with reference to FIGS. 16, 17, and 18, at the write timing of the first gate bus line, the offset of the write polarity of the odd drain bus is provided to the first counter electrode. A voltage signal such as a voltage is supplied, and a voltage signal such as an offset voltage of the write polarity of the even drain bus is supplied to the second counter electrode.

At the write timing of the second gate bus line, a voltage signal such as an offset voltage of the write polarity of the odd drain bus is supplied to the second counter electrode and the even drain bus is supplied to the third counter electrode. The voltage signal such as the offset voltage of the write polarity is supplied. Similarly, a voltage signal is supplied to the Nth counter electrode at the write timing of the Nth gate bus line, and a voltage signal such as an offset voltage of the write polarity of the odd drain bus is supplied to the N + 1th counter electrode. Writing of one screen is completed by supplying a voltage signal such as an offset voltage of the write polarity of the even drain bus.

At this time, the polarities of the odd drain bus and the even drain bus are different at the write timing of the same gate bus line, and the polarities are inverted at the write timing of the next gate bus line. Therefore, a voltage signal that changes in synchronization with the write timing of the pixel electrode connected to the even-numbered drain bus through the TFT is excluded from the corresponding pixel electrode except the first counter electrode. Will be supplied.

Therefore, in the circuit configuration of the two systems, the shift register section A41 has a first circuit as shown in FIG.
Fluctuate ON voltage application just before the gate bus line, and a signal DF with odd polarity data in the line direction of the first line in synchronization with the rising of the ON voltage application of each of the gate bus lines, and the t _on time A clock Φ _C having a period is supplied to generate D _C1, and a waveform D _C3 delayed by one clock from D _C1 indicating even-numbered polarity data of the second gate bus line is generated, and a fourth gate is also generated. A waveform D _C3 delayed by one clock from D _C1 indicating even-numbered polarity data of the bus line is created, and a waveform D _C5 delayed by 2 clocks from D _C3 indicating even-numbered polarity data of the fourth line is generated. , And the like, the waveform D _C7 delayed by two clocks, ...
D _{CN + 1} is created, and this is supplied to the voltage amplification unit, and is inverted / amplified by R ₂ / R ₁ times by the operational amplifier and the resistors R ₁ and R ₂ .
A voltage signal having a predetermined voltage amplitude including an offset voltage of the liquid crystal and a polarity correction voltage when the gate bus is selected is created, and the voltage signal is applied to the first counter electrode via the protection resistor R ₃ and the driver unit A43. V _COM1 , the voltage signal V _COM3 is supplied to the third counter electrode, and the voltage signal V _{COMN + 1} is supplied to the (N + 1) th counter electrode.

Further, the shift register section B44 has a structure shown in FIG.
2, the signal -DF2 and the clock Φ _C that fluctuate immediately before the ON voltage of the first gate bus line is applied and that has even-numbered polarity data in the line direction of the first gate bus line are supplied, D _C2 is created, a waveform D _C4 delayed by 2 clocks from D _C2 indicating even-numbered polarity data of the third gate bus line is created, and thereafter, waveforms D _C6 , ..., D delayed by 2 clocks each in the same manner. create a _CN, which was supplied to the voltage amplifier, R ₂ an operational amplifier and resistors R _1, R ₂
/ R ₁ times inverting amplification is performed to create a voltage signal having a predetermined voltage amplitude including an offset voltage component and a polarity correction voltage component when the gate bus is selected, and a second voltage signal is generated via the protection resistor R ₃ and the driver unit B46. The voltage signal V _COM2 is applied to the fourth counter electrode by the fourth
The voltage signal V _COM4 and the voltage signal V _COMN are supplied to the Nth counter electrode and the Nth counter electrode, respectively. Since V _COM1 , V _COM2 , ..., V _{COMN + 1} output here may supply voltage signals having the same voltage amplitude, a binary output drain driver should be applied to the common variation circuit. You can also

The equivalent circuit of the liquid crystal cell is similar to that of FIG.
In the case of the driving method described above, the fluctuation of the effective voltage in the charge holding state of the liquid crystal cell occurs under at least three conditions. First, [Delta] V ₁ immediately after writing TFT connected to the pixel electrode, the parasitic capacitance C _gs of the TFT '= [C
_gs / (C _gs + C _LC )] × (VG ₍₊₎ '-VG _(-) '),
Next, when the two drain buses sandwiching the pixel electrode change from the voltage during writing by ΔV _D1 ′ and ΔV _D2 ′, the capacitances C _{DP 1} and C between the pixel electrode and the two drain buses are _{generated.
According to DP2} , ΔV ₂ ′ = (C _DP1 / C _LC ) × ΔV _D1 ′ −
_{(C DP2 / C LC) ×} ΔV D2 ', further, when the voltage of the common electrode to perform charge accumulation between the pixel electrode is varied only [Delta] V _{CO M,} by the parasitic capacitance C _gs of the TFT, [Delta] V _3' = [ C
_gs / (C _gs + C _LC )] × ΔV _COM .

If the same TFT is formed in all the pixel electrodes, the potential fluctuation ΔV ₁ ′ has the same polarity and the same potential regardless of the write voltage and the write timing, and therefore the voltage supplied to the counter electrode. In the setting of, Δ
By setting the shift by V ₁ ′, the same effective voltage can be maintained in all liquid crystal cells.

The potential fluctuations ΔV ₂ ′ and ΔV ₃ ′ have different polarities of the effective voltage fluctuation depending on the polarities at the time of writing, and the fluctuation amount is the polarities of the two drain bus lines and the counter electrode sandwiching the pixel electrode at the time of writing. Shows the largest voltage fluctuation. Therefore, in each pixel electrode, if there is a short period and a long period in which the polarities of the two are changed with respect to the polarities at the time of writing, the average effective voltage is different, and display unevenness occurs.

FIG. 23 is a timing chart showing a driving voltage and a pixel voltage of a TFT connected to an odd drain bus of another embodiment of the present invention, and FIG. 24 is an even drain bus of another embodiment of the present invention. 7 is a timing chart showing a drive voltage and a pixel voltage change of a TFT connected to. Therefore, in this embodiment, the voltage signals V _COM1 , V _COM2 , ..., V _{COMN + 1} supplied to the counter electrodes are set by _{shifting the} voltage variation ΔV ₁ ′, and the polarity of each drain bus line is set. Since AC drive is performed in which the polarity is inverted in one line cycle of the drain bus, the period during which the polarities of the two drain bus lines sandwiching the pixel electrode are the same as that during writing is the same for all pixel electrodes. And the average effective voltage becomes uniform.

Further, the polarity of the counter electrode with respect to each pixel electrode is limited only to the pixel electrodes arranged in the second to Nth drain bus lines connected to the odd drain bus lines via TFTs during the period changing from the time of writing. Exists and its duration is
Since T × 1 / N = t _on , which is an extremely short period as compared with the charge holding period T of each pixel electrode, the fluctuation of the average effective voltage due to the influence of ΔV ₃ ′ described above is negligible. Become.

Further, in consideration of the above, the voltage signals of V _COM1 , V _COM2 , ... V _{COMN + 1} supplied to the counter electrodes are _expressed by Δ in all pixel electrodes calculated from the display data.
In order to additionally supply the average voltage fluctuation amount of V ₂ ′ -ΔV ₂ ′ as the effective voltage loss caused by the voltage fluctuation of ΔV ₂ ′, the voltage of V _COM1 , V _COM2 , ..., V _{COMN + 1} When writing a waveform of positive polarity, V _{D (+)} '-ΔV-V
_At the voltage level of _TH −ΔV ₁ ′ − (− ΔV ₂ ′), when writing the negative polarity, V _{D (−)} ′ + ΔV + V _TH −ΔV ₁ ′
ΔV + 2V _TH +2 set to + -ΔV ₂ ′ voltage level
When supplied with a voltage signal having a fluctuation amplitude of × (−ΔV ₂ ′), the amplitude of the voltage data output from the data circuit is Δ.
Even when set to V, the average effective voltage of all the pixels can be made approximately equal to ΔV + V _TH . Similarly, the amplitude of the gate voltage can be reduced to the same extent as the amplitude of the drain voltage is reduced.

The equivalent circuit of the liquid crystal panel is the same as that of FIG. 9, and as shown in FIGS. 16, 17 and 18, the active matrix type thin film transistor liquid crystal panel is provided with a large number of electrical wirings. The wiring capacitance exists as a constitution condition of the liquid crystal panel, and the liquid crystal capacitance C _{LC of} each display cell
A loss current is generated when writing to. The capacitance C _GD created by the intersection of the drain bus and the gate bus causes a loss current proportional to the amount of voltage change of the drain bus to the gate bus and the drain bus every time the voltage of the drain bus changes, and the liquid crystal The capacitance C _DC created between the drain bus and the counter electrode via the layer is the loss current proportional to the voltage variation of the drain bus in the drain bus and the counter electrode every time the voltage of the drain bus also varies. Generate.

C present in each display cell unit shown here
Without large so much amount of current generated by _GD and C _DC, for considering the whole wire is fairly large current, short duration loss current, in order to release, for example, in line periods outside the panel, the drain bus In addition to lowering the resistance of the gate bus and the counter electrode, it is necessary to increase the current capacity of the external driver connected to each wiring.

In this embodiment, when the polarities of adjacent drain buses are different, and when the polarities are changed, the voltage fluctuations of the adjacent drain buses are always different polarities, for example, when one of them changes from positive polarity to negative polarity, The other will change from negative polarity to positive polarity. Therefore, the loss currents generated by the adjacent capacitors C _GD on one gate bus line or by the adjacent capacitors C _DC on one divided counter electrode are currents flowing in opposite directions. , The loss currents tend to cancel each other out.

Therefore, the loss current flowing through one gate line and drain bus line and each counter electrode becomes very small, and the resistance of each wiring and the capacity of the external driver connected to each wiring are increased. It is possible to provide a liquid crystal panel that does not need to be measured, and is suitable for large capacity and high definition of the liquid crystal panel. The present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0065]

INDUSTRIAL APPLICABILITY As described in detail above, the present invention
According to this, a thin film transistor is connected to one gate bus line.
The pixel electrode group connected via the gate bus line direction
Are alternately arranged in a zigzag pattern, and each counter electrode is
A gate is provided corresponding to each pixel electrode group arranged in the in direction.
The pixel electrode group arranged in the bus line direction is connected to two gate bars.
Each line is controlled by a spline and one counter electrode.
V supplied to the counter electrode _COMTime to switch voltage
Voltage data provided to the drain bus line
The polarity is different between adjacent drain bus lines.
The polarity is reversed every inspection line cycle, and the positive and negative polarities are
The voltage data is supplied as voltage information that is inverted from each other.
The voltage signal supplied to each counter electrode to each counter electrode.
Two gates connected to the corresponding pixel electrode via TFT.
Gate bus line selected first among the bus lines
Fluctuates in synchronization with the writing timing of the
Equivalent to the polarity data of the corresponding pixel electrode group and the liquid crystal threshold
Offset voltage and effective voltage correction voltage
The average effective voltage of the liquid crystal cell is averaged by supplying
Unification and switching of gate and drain bus lines
It is possible to achieve lower withstand voltage of the
It

This driving method is also suitable for a large-capacity, high-definition display because it can reduce the generation of loss current caused by the wiring capacitance in the liquid crystal panel. Furthermore,
Since this driving method has the same effect even when an analog voltage is input to the drain bus line, it can be sufficiently applied to gradation driving of an active matrix thin film transistor liquid crystal panel.

According to the present invention, the pixel electrode group connected to one gate bus line via the thin film transistor is arranged in the gate bus line direction, and the two adjacent gate bus lines are connected via the TFT. In the pixel electrode group connected by the
One corrugated counter electrode is provided for the pixel electrode group selected from the two gate bus lines, a circuit for switching the V _COM voltage supplied to each corrugated counter electrode is provided, and the drain bus line is provided. The supplied voltage data is
The polarities are different between the adjacent drain buses, the polarities are inverted every scanning line cycle, and the positive polarity and negative polarity voltage data are supplied as mutually inverted voltage information, and the voltage signal supplied to each counter electrode is A pixel corresponding to each counter electrode, which changes in synchronization with the write timing of the gate bus line selected first of the two gate bus lines connected to the pixel electrode corresponding to each counter electrode via the TFT. By supplying the voltage data including the polarity data of the electrode group and the offset voltage and the effective voltage correction voltage corresponding to the threshold voltage of the liquid crystal, the average effective voltage of the liquid crystal cell is made uniform and the switching driver of the gate bus line and the drain bus line. It is possible to achieve low withstand voltage.

[Brief description of drawings]

FIG. 1 is a schematic perspective view of an active matrix thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 3 is a schematic block diagram of a data circuit of an active matrix thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 4 is a diagram showing the timing of voltage data supplied to the drain bus of the active matrix thin film transistor liquid crystal panel showing the embodiment of the present invention.

FIG. 5 is a schematic block diagram of a common variation circuit of an active matrix thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 6 is a first operation timing chart of the common variation circuit of the active matrix thin film transistor liquid crystal panel showing the embodiment of the present invention.

FIG. 7 is a second operation timing chart of the common variation circuit of the active matrix thin film transistor liquid crystal panel showing the embodiment of the present invention.

FIG. 8 is an equivalent circuit diagram of a liquid crystal cell of an active matrix thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 9 is an equivalent circuit diagram of an active matrix thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 10 is a timing chart showing changes in driving voltage and pixel voltage of a thin film transistor connected to an odd drain bus according to an embodiment of the present invention.

FIG. 11 is a timing chart showing changes in driving voltage and pixel voltage of a thin film transistor connected to an even drain bus according to an embodiment of the present invention.

FIG. 12 is a schematic configuration diagram of an active matrix thin film transistor liquid crystal panel showing another embodiment of the present invention.

FIG. 13 is a configuration diagram of a conventional active matrix thin film transistor liquid crystal panel.

FIG. 14 is a diagram showing a drive timing chart of a conventional active matrix thin film transistor liquid crystal panel.

FIG. 15 is a diagram showing electro-optical characteristics of a conventional TN liquid crystal cell.

FIG. 16 is a schematic perspective view of an active matrix type thin film transistor liquid crystal panel showing another embodiment of the present invention.

FIG. 17 is a diagram showing a structure of a counter electrode of an active matrix type thin film transistor liquid crystal panel showing an example of the present invention.

FIG. 18 is a schematic configuration diagram of an active matrix type thin film transistor liquid crystal panel of another embodiment of the present invention.

FIG. 19 is a diagram showing the timing of voltage data supplied to the drain bus of an active matrix thin film transistor liquid crystal panel according to another embodiment of the present invention.

FIG. 20 is a diagram showing a common variation circuit of an active matrix thin film transistor liquid crystal panel showing an example of the present invention.

FIG. 21 is a diagram showing a first timing chart of a common variation circuit of an active matrix thin film transistor liquid crystal panel showing another embodiment of the present invention.

FIG. 22 is a diagram showing a second timing chart of the common variation circuit of the active matrix thin film transistor liquid crystal panel showing another embodiment of the present invention.

FIG. 23 is a diagram showing a timing chart showing a drive voltage and a pixel voltage change of a TFT connected to an odd drain bus according to another embodiment of the present invention.

FIG. 24 is a diagram showing a timing chart showing changes in driving voltage and pixel voltage of TFTs connected to an even drain bus according to another embodiment of the present invention.

[Explanation of symbols]

 11 Gate Bus Line 12 Drain Bus Line 13 TFT 14 Pixel Electrode 15 Counter Electrode 15a Portion Facing the Pixel Electrode 15b Counter Electrode Joint 16 Liquid Crystal 17 Storage Capacitance 18 Storage Capacitance Line 19 Gap 20 Scan Circuit 30 Data Circuit 31 Data Generator 32 Data inversion unit A 33 Data inversion unit B 34 Data output unit A 35 Data output unit B 40 Common fluctuation circuit 41 Shift register unit A 42, 45 Voltage amplification unit 43 Driver unit A 44 Shift register unit B 46 Driver unit B

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Atsushi Takahashi 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Misei Chiba 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (5)

[Claims] 1. A gate bus line and a drain bus line arranged orthogonally on a rear substrate, and a thin film transistor corresponding to each pixel electrode is provided at an intersection of the gate bus line and the drain bus line, and is transparent on the front substrate. An opposite electrode is provided, and an alignment film that has been subjected to an alignment treatment in an appropriate direction is provided on the surfaces of the back substrate and the front substrate, and the alignment films of both substrates are bonded so as to be opposed to each other via a liquid crystal layer, and In a method of driving an active matrix type thin film transistor liquid crystal panel in which a polarizing film is attached to the back surface of a substrate and a front substrate, pixel electrode groups connected via a thin film transistor to one gate bus line are alternately staggered in the gate bus line direction. Pixel electrodes in the direction of the gate bus line by the pixel electrodes in one portion corresponding to two adjacent gate bus lines. Groups, each pixel electrode group arranged in the direction of the gate bus line is provided with one counter electrode, a circuit for switching each counter electrode is provided, and the polarity of voltage data of adjacent drain bus lines is different, and one scanning line is provided. A voltage signal indicating a voltage in which the polarity of the voltage data is inverted every cycle and the voltage data of positive polarity and negative voltage is inverted is supplied to each drain bus line, and the pixel electrode corresponding to each counter electrode is supplied. In two adjacent gate bus lines connected to each other via a thin film transistor, it fluctuates in synchronization with the write timing of the gate bus line selected first,
Further, a voltage signal including polarity data of the pixel electrode group corresponding to each counter electrode, an offset voltage corresponding to the threshold voltage of the liquid crystal, and an effective voltage correction voltage is supplied to each counter electrode, and a selection signal is supplied to the gate bus line. A method for driving an active matrix type thin film transistor liquid crystal panel, characterized in that voltage writing is performed on each pixel electrode by means of. 2. The active matrix type thin film transistor according to claim 1, wherein impedance components including capacitors C _DP1 and C _DP2 existing between the pixel electrode and an adjacent drain bus line are made equal to operate. Liquid crystal panel driving method. 3. An active matrix type thin film transistor according to claim 1, wherein an auxiliary capacitance C _S is provided electrically in parallel with a liquid crystal capacitance C _LC between the pixel electrode and the counter electrode to operate. Liquid crystal panel driving method. 4. A gate bus line and a drain bus line are provided orthogonally on a rear substrate, and a thin film transistor is provided at an intersection of the gate bus line and the drain bus line corresponding to each pixel electrode, and is transparent on the front substrate. A counter electrode is provided, and an alignment film that has been subjected to an alignment treatment in an appropriate direction is provided on the surfaces of the back substrate and the front substrate, and the alignment films of both substrates are opposed to each other via a liquid crystal layer and bonded together, and the back substrate And a driving method of an active matrix type thin film transistor liquid crystal panel in which a polarizing film is attached to the back surface of a front substrate, a pixel electrode group connected to one gate bus line via a thin film transistor is arranged in the gate bus line direction,
In a pixel electrode group connected to two adjacent gate bus lines via a thin film transistor, one wavy pattern is provided for the pixel electrode groups selected from two lines alternately in a zigzag manner in the gate bus line direction. A counter electrode is provided, a circuit for switching each corrugated counter electrode is provided, the polarities of the electrode data of the adjacent drain bus lines are different, and the polarities of the voltage data are inverted every scanning line cycle, and the polarity is positive and negative. A voltage signal indicating a voltage obtained by inverting the voltage data of each other is supplied to each drain bus line, and two adjacent gate bus lines connected to a pixel electrode corresponding to each counter electrode via a thin film transistor, The polarity data of the pixel electrode group and the liquid crystal of the pixel electrode group that fluctuates in synchronization with the write timing of the gate bus line selected earlier and corresponds to each counter electrode. A voltage signal including an offset voltage corresponding to a value voltage and an effective voltage correction voltage is supplied to each counter electrode, and a selection signal is supplied to a gate bus line to perform voltage writing to each pixel electrode. Type thin film transistor liquid crystal panel driving method. 5. The active matrix thin film transistor according to claim 4, wherein impedance components including capacitances C _DP1 and C _DP2 existing between the pixel electrode and an adjacent drain bus line are equalized to operate. Liquid crystal panel driving method.