JP3132904B2 - Active matrix display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type display device, and more particularly to an active matrix type display device having a structure in which a data bus line is shared between adjacent pixel pairs.

[0002]

2. Description of the Related Art In recent years, an active matrix type display device has been used as a thin type information terminal display device together with a simple matrix type display device, and liquid crystal is often used as a display medium. An active matrix liquid crystal display device can drive a large number of pixels independently of each other as compared with a simple matrix liquid crystal display device. It is characterized in that problems such as a decrease in the duty ratio of driving, a decrease in contrast, and a decrease in the viewing angle do not occur.

However, the active matrix type display device (active matrix type liquid crystal display device) has a complicated structure, so that the manufacturing equipment must be large-scale, and a complicated process is required, so that a high manufacturing yield is required. It takes a lot of effort to get Further, as an inevitable problem of the active matrix type display device, there is a problem that a large number of driver ICs are required as the display capacity increases.
These large capital expenditures, manufacturing yield issues, and
Due to factors such as an increase in the cost required for the driver IC, the active matrix type display device is unavoidably expensive, and at present the widespread use is hindered. Therefore, there is a demand for an active matrix display device having a high production yield and excellent display quality without incurring large-scale capital investment and cost increase.

FIG. 11 is a diagram showing a basic configuration of an active matrix type display device. In the figure, reference numeral 210 denotes an active matrix type display panel, and 211 denotes a scan bus driver for sequentially applying an address pulse to a scan bus line of the display panel 210. A period in which the address pulse is sequentially applied from the top to the bottom of the scan bus line is called a frame. In addition, a method of applying an address pulse every other line is called an interlace method. In this case, there are two frames, a first time frame and a second time frame, which are called an odd frame and an even frame, respectively.

A data bus driver 214 applies a data voltage to a data bus line of the display panel 210. Reference numeral 218 denotes a clock signal and a horizontal scanning signal (HS) supplied to the scan bus driver 211 and the data bus driver.
YNC) and a control signal generator that generates a vertical synchronization signal (VSYNC). 219 is a data bus driver 21
A data voltage generator 4 generates a data voltage to be applied to the data bus line, and generates a data voltage corresponding to a gradation stage when performing a gradation display. In addition, in the liquid crystal display device, it is necessary to apply a voltage of the opposite polarity to each display cell for each frame, and the data voltage generator 219 generates a data voltage of twice the gradation level.

The scan bus driver 211 includes a shift register 212 and an output circuit 213. The shift register 212 sequentially shifts the position of the scan bus line to which the address pulse is applied according to the HSYNC signal. The output circuit 213 is a driver circuit for outputting a signal from the shift register 212 to each scan bus line.

The data bus driver 214 includes a shift register / latch 215 and a data voltage selection switch array 21.
6 and an output circuit 217. The shift register / latch 215 fetches input display data in synchronization with a clock signal and shifts the display data sequentially. When data for one row is completed, the data is latched by the HSYNC signal and output. The data voltage selection switch array 216 selects and outputs the data voltage from the data voltage generator 219 for each data bus line according to one row of display data from the shift register / latch 215. Output circuit 217
Is a driver circuit for outputting the data voltage for one row to the data bus line.

FIG. 12 is a diagram showing an equivalent circuit of an active matrix type liquid crystal display panel. In the figure, 12 is a scan bus line, and 13 is a data bus line. Scan canvas line 12 and data bus line 13
Thin film transistor (TFT) 1 corresponding to the intersection of
1 and a pixel electrode 15 are provided. Reference numeral 16 denotes an opposing pixel electrode on the opposing substrate, which is generally called a common electrode because it is commonly connected to all pixels. A liquid crystal material is filled between the pixel electrode 15 and the counter pixel electrode 16.

The controlled electrode of the TFT 11 is connected to the data bus line 13 and the pixel electrode 15, respectively, and the control electrode is connected to the data bus line 12. When an address pulse is applied to the scan line 13,
TFT 1 connected to the scan bus line 13
1 is in a conductive state, and the data bus line 13 and the pixel electrode 15 are connected. A voltage difference between the data bus line 13 and the opposing pixel electrode 16 is applied to the capacitor formed of the liquid crystal material between the pixel electrode 15 and the opposing electrode 16, and the state of the liquid crystal changes. When the application of the address pulse to the scan bus line 12 is completed, the TFT 1
Since 1 is in a non-conductive state, the state of the liquid crystal is maintained until the next address pulse is applied.

Active matrix type display panel 210
Operates as described above, so that the scan bus driver 211 only needs to sequentially output address pulses for making the TFT 11 conductive, and can be realized with a relatively simple configuration. In contrast, the data bus driver 214 outputs a data voltage to be applied to the cell, but the state of the pixel material changes according to the applied voltage.
A highly accurate voltage output function is required. Since the shift register also operates in synchronization with the clock signal, the data bus driver 214 is required to operate at a higher speed.

Further, if gradation display is to be performed, the shift register / latch 215 needs to shift and hold multi-bit data corresponding to the number of gradation steps, and the number of switches in the data voltage selection switch array 216 is also limited. It increases by the number of gradation steps. Therefore, the data bus driver 214
Is much more complicated than the scan bus driver 211.

A typical active matrix type display device has a structure of 640 × 480 dots or the like, and has a larger number of pixels in a row direction (horizontal direction). Therefore, the number of data bus lines is larger than the number of scan bus lines. Further, in the case of performing color display, the number of data bus lines is four times as large as the number of scan bus lines because three RGB pixels forming one pixel are formed by vertically long pixels.

Although the scan bus lines and the data bus lines intersect at a right angle, there is a problem in that the number of data bus lines is large, as described above, and the layout restrictions are large. The data bus driver 214 is more complicated than the scan bus driver 211 even when driving the same number of bus lines. However, when the number of data bus lines is large as described above, the data bus driver 214 becomes larger and more complicated. This causes a problem in cost. In order to solve the above-mentioned problem, Japanese Patent Application Laid-Open Nos. 62-21887 and 3-38689 disclose a common data bus line via two TFTs capable of controlling adjacent pixel electrodes independently. And an active matrix display device in which the number of data bus lines is reduced by driving in a time sharing manner.

FIG. 13 is a diagram showing a configuration of a conventional example in which a data bus line is shared. In this specification, parts having the same function are denoted by the same reference numerals. In FIG. 13, 12 ₁ and 12 ₂ are sets of scan bus lines, and there are as many sets as the number corresponding to the pixel rows. 13 is a data bus line. 15 ₁ and 15
Reference numeral ₂ denotes pixel electrodes arranged in a matrix. 11 ₁
When 11 ₂ are pixels corresponding switching elements connected to the scan bus lines 12 _1, 12 ₂ and the data bus line 13. Between the electrodes facing the pixel electrodes 15 _1, 15 _2, there is an electro-optical device that is controlled by the switching element 11 ₁ and 11 _2. And the scan bus line 12
₁ and 12 pixel electrode pair 15 ₁ adjacent in the direction of ₂ and 15 ₂
Are connected to the same data bus line 13.

[0015] are connected to the same data bus line 13 by the switching element 11 ₁ and 11 ₂ pixel electrode pair 15 ₁ and 15 ₂ are independent. This switching element 1
1 ₁ and 11 ₂ is operated at the time division, if the supply voltage applied to each pixel in the data bus driver in accordance with the operation thereof, each pixel can be performed displayed independently. FIG. 14 is a diagram showing an example of an address signal in the configuration of FIG.

[0016] Figure 14 (a) is a set 12 ₁ and 12 ₂ of the scan bus lines corresponding to the pixel row of a row, is a diagram illustrating a case of applying an address pulse V _S1, V _S2 continuously . When the address pulse V _S1 , m is applied to the m-th scan bus line 12 ₁ , the switching element 11 ₁ connected to the control electrode becomes conductive, so that if a data voltage is applied to the corresponding data bus line 13 , the data voltage is applied to the pixel electrode 15 _1. Then the same m-th row of the scan bus line 12 ₂ to address pulse V
If output _S2, m, can apply a data voltage similarly to the pixel electrode 15 _2. Therefore, the data voltage is applied twice.

In this case, the conventional one horizontal scanning period (t _H )
To apply the data voltage to the pixel pair adjacent to
address pulse V _S1, m and V _S2, m to m-th row of scan bus lines 12 ₁ and 12 ₂ are respectively 1/2 t _H pulse width less is a pulse shifted by 1/2 t _H It is necessary. The same address pulse is applied to each scan bus line every frame. In this case, one frame corresponds to one screen display cycle.

FIG. 14B shows scan bus lines 12 ₁ and 12 ₂ for applying an address pulse for each frame.
FIG. 7 is a diagram showing a case where the image is alternately changed between the two frames, and one frame is displayed on one screen in two frames. Therefore, in the first frame, only the data voltage is applied to one pixel of each pixel pair, and in the second frame, the data voltage is applied to the other pixel. If the screen display cycle is the same in (a) and (b), h in the figure corresponds to 1/2 t _H.

As described above, even when the data bus line is shared, the application of the data voltage to each pixel can be performed independently. In FIG. 14, the switching element 11
₁ and 11 ₂ are shown as being in a conductive state by the address pulse of the same polarity, but it is also possible to use two kinds of switching elements turned in different polarities.

As apparent from FIG. 13, the number of scan bus lines is twice as large as the arrangement of pixels, but the number of data bus lines is reduced by half. Therefore, for example, in order to display 640 × 480 dots in color display,
The conventional active matrix type display device requires 480 scan bus lines and 1920 data bus lines. In the present invention, however, there are 960 scan bus lines and 960 data bus lines. This not only reduces the total number of bus lines from 2,400 to 1920, but also facilitates layout because the number of scan bus lines and the number of data bus lines are balanced.

Further, since the number of data bus lines driven by a complicated and high-cost data bus driver is halved,
The structure of the data bus driver is simplified, and the overall cost can be significantly reduced. Of course, the application time of the data voltage to one pixel is reduced by half, but there is no problem in the current driving performance of the data bus driver and the performance of the TFT. Although the shift cycle for one row in the data bus driver is also halved, the number of data to be shifted is also halved, so that the shift speed does not change and no cost increase in this respect occurs.

On the other hand, in the active matrix type display device, improvement in display quality and improvement in reliability are required.
One of the obstacles to this is the effect of the parasitic capacitance between the electrode and the bus line. In an active matrix liquid crystal panel, a parasitic capacitance exists in each pixel portion. For example, FIG.
, A parasitic capacitance exists between the scan bus line 12, the data bus line 13, and the opposing pixel electrode 16, respectively. Among them, the parasitic capacitance between the scan bus line 12 is particularly problematic. That is, as the scan bus line voltage returns from the write voltage to the holding voltage immediately after the address, the voltage fluctuation appears on the pixel electrode 15 through the parasitic capacitance, and a phenomenon occurs in which the voltage fluctuation is held until the next address. Since this voltage fluctuation has only one direction of the polarity of the address pulse,
Occurs in only one direction. It is desirable for the liquid crystal to have no DC component in the drive voltage waveform from the viewpoint of the life characteristics and the like. And a DC component is generated as a result. The generation of such a DC voltage not only adversely affects the life characteristics of the liquid crystal, but also causes flicker and afterimages, thereby deteriorating the display characteristics.

In order to solve such a problem, Japanese Patent Laid-Open No.
In Japanese Patent Application Laid-Open No. 3-144297, two positive and negative symmetric voltages are output through two types of switching elements which conduct one pixel electrode by an address pulse of opposite polarity applied to a common scan bus line. There is disclosed an active matrix display device which is connected to a data bus line and conducts two types of switching elements for each frame to cancel the influence of parasitic capacitance. However, this device has a problem that the number of data bus lines increases.

The applicant of the present invention has also disclosed Japanese Patent Application No. 2-118346.
And Japanese Patent Application No. Hei 2-118347, each pixel electrode is connected to a data bus line via two types of switching elements which conduct with address pulses of positive and negative polarities, and the two types of switching elements are simultaneously or frame by frame. An active matrix display device has been proposed in which the effects of the parasitic capacitance are canceled each other by alternately conducting.

FIG. 15 is a diagram showing a configuration of a conventional example for preventing generation of a DC component as described above. As shown, scan bus lines 12 ₁ and 12 ₂ are provided above and below each pixel row, and each pixel electrode 15 is connected to the data bus line 13 via two types of TFTs 11 ₁ and 11 ₂ . N channel (Nch) type TF on the upper side of the scan bus lines 12 ₁
T11 ₁ control electrode is connected, the control electrode of the Pch-type TFT 11 ₂ is connected to the scan bus line 12 ₂ lower.

The scan bus lines 12 ₁ and 12 in FIG.
_When each of the address pulses shown in FIG. 16 is applied to FIG. ₂ , the two types of switching elements 11 ₁ and 11 ₂ conduct simultaneously. In this case, since the address pulses have opposite polarities, the DC components due to the parasitic capacitances are in opposite directions and cancel each other.

[0027]

An adjacent pair of pixels in a pixel row is connected to a common data bus line via an independently controllable switching element, and driven in a time-division manner to reduce the number of data bus lines. There is a demand for improved display quality even in a reduced active matrix display device, and an object of the present invention is to improve display quality and reliability by preventing a DC component from being generated in an active matrix display device. And

[0028]

An active matrix type display device according to the present invention comprises a plurality of scan bus lines and data bus lines, pixel electrodes arranged in a matrix, and connection to the scan bus lines and data bus lines. An active matrix display device includes a switching element corresponding to a pixel and an electro-optical element filled between electrodes facing the pixel electrode and controlled by the switching element. To achieve the above object, a pair of pixel electrodes adjacent to each other in the direction of the scan bus line is connected to the same data bus line, and the scan bus line is vertically connected to one pixel row so as to sandwich the pixel row. And a first type of switching element that is turned on by applying a positive voltage to the control electrode, and is turned on by applying a negative voltage to the control electrode. It is composed of two types of switching elements and a second type of switching element, and both the first type of switching element and the second type of switching element are connected to both pixels of the pixel pair. A first type switching element connected to one pixel;
A second type of switching element connected to the other pixel is connected to one scan bus line adjacent to the pixel row, and a second type of switching element connected to one pixel of the pixel pair; The first type of switching element connected to the pixel is connected to another scan bus line adjacent to the pixel row.

[0029] Then, in the apparatus as described above, Suki
The address pulse applied to the campus line is one horizontal.
It has a pulse width less than half of the scanning period, and
The polarity is alternately inverted at the same time
It is characterized in that the application order can be switched between the lines.
You.

[0030]

According to the present invention, two scan bus lines are provided above and below the pixel row. Each pixel electrode is connected to the same data bus line via a first type and a second type of two switching elements. At this time, different types of switching elements connected to the respective electrodes of the pixel electrode pair are used. Are connected to the same scan bus line. Thereby, 4 connected to both electrodes of the pixel electrode pair
The switching elements can be controlled independently. By applying address pulses having different polarities to the two scan bus lines, two types of switching elements connected to one pixel are simultaneously turned on, so that generation of a DC component can be prevented.

In the conventional example shown in FIG. 15 for preventing the generation of a DC component, two switching elements connected to each pixel electrode are of the same type connected to the same scan bus line. Switching elements cannot be independently conducted. Therefore, in order to connect the pixel pairs to the same data bus line and drive them in a time division manner, the same type of switching element connected to the two electrodes of the pixel electrode pair as in the present invention is connected to different scan bus lines. Need to be done.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an active matrix type display panel according to the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the active matrix type liquid crystal display panel of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing an embodiment, in which the present invention is applied to a conventionally known ordinary active matrix type liquid crystal display panel. In the following description, a liquid crystal display panel is used as an example, and a pixel electrode may be expressed as a pixel or a liquid crystal cell.

As shown in FIG. 1, the active matrix type liquid crystal display panel of this embodiment has scan bus lines 12 ₁ , 12 ₂ and scan bus lines 12 ₁ , 1.
A plurality of data bus lines 13 orthogonal to 2 ₂ , pixel electrode pairs 15 ₁ , 15 ₂ arranged in a matrix, and TFTs 11 ₁₁ , 11 ₁₂ , 11 corresponding to pixels connected to the scan bus lines and the data bus lines. _21, 11 _22, is electrically connected to the pixel electrode TFT 11 _11, 11 _12, 11
And a liquid crystal controlled by _21, 11 _22. Here, the active matrix type liquid crystal display panel of this embodiment has scan bus lines 12 ₁ ,
12 ₂ , data bus line 13, pixel electrodes 15 ₁ , 15
₂ and form a _{TFT11 11, 11 12, 11 21} , 11 22, and is configured so as to sandwich liquid crystal between a solid shaped counter pixel electrode formed on the other insulating substrate (common electrode).

As shown in FIG.
12₁, 12_TwoRepresents one pixel row (in the figure, the horizontal direction
Two rows are provided above and below the row of pixels
Campus line 12₁, 12_TwoPixels adjacent in the direction
Pole 15₁And 15_TwoForm a pixel electrode pair. Pixel electrode
Both electrodes 15 of the pair₁, 15_TwoIs TFT11₁₁, 1
1 ₁₂, 11_{twenty one}, 11_{twenty two}Via the same data bus line
13. Pixel electrode 15₁Nch connected to
Type TFT11₁₁And Pch type TFT11₁₂Gate electrode of
Are the upper and lower scan bus lines 12₁And 12_TwoTo
Connected respectively. Pixel electrode 15_TwoPc connected to
h-type TFT11_{twenty one}And Nch TFT11_{twenty two}Gate electrode of
Is the scan bus line 12₁And 12_TwoConnect to each
Is done.

FIG. 2 is a diagram showing drive signals in the first embodiment. V _{S1, m} indicates a voltage change of a signal applied to the upper scan bus line of the m-th pixel row, and V _{S2, m} indicates m
It shows a voltage change of a signal applied to the scan bus line below the pixel row of the row. As shown, two scan bus lines 12 arranged above and below one pixel column
_1, consists of consecutive positive and negative address pulse having a pulse width of approximately 1/2 t _H in 12 _2, polar symmetrical address voltage waveform is applied to each other. Pixels LC _{m, 2n} are simultaneously Pch type a positive address pulse is applied to the TFT11 ₁₁ of the Nch-type timing addressed TFT11
₁₂ , a negative address pulse is applied, and this pixel LC
_m, TFT 11 ₁₁ and 11 ₁₂ of both being connected to _2n become conductive simultaneously. In the next 1/2 horizontal scanning period, the pixel LC
_m, and that _{2n + 1} of the Nch-type TFT 11 ₂₁ where both positive address a pulse is applied is applied a negative address pulse to TFT 11 ₂₂ of the Pch type simultaneously also in the TFT 11 ₂₁ and 11 ₂₂ are conductive at the same time Become. In this example,
Since the positive and negative address pulses are simultaneously applied to the upper and lower scan bus lines in the writing operation of each pixel, the DC level shift generated at the falling edge of the address pulse is canceled, and the display characteristics such as image sticking and flicker caused by the DC level shift are generated. It has the feature that the deterioration of can be prevented.

Further, since each pixel is controlled by two switching elements, it can operate even if one of the pixels fails, and as a result, the redundancy is improved. If the positive and negative pulses applied to the _two scan bus lines 12 ₁ and 12 ₂ are applied at the same time, there is no need for the continuous positive and negative pulses as shown in FIG. FIG. 3 is a modified example of the drive signal in the first embodiment. In this example, the polarity of the voltage waveform of the address pulse is inverted for each frame. In FIG. 2, Nc
h-type and Pch-type two TFTs 11 _11, 11 ₁₂ ; 11
_In contrast to the simultaneous writing at _21, 11 and ₂₂ , writing is performed by alternately turning on one of the two TFTs for each even and odd frame. However, in this case, it is necessary to change the order of the address pulses applied to the scan bus lines on both sides of the pixel as shown in FIG. With such a driving method, as shown in FIG. 2, the influence of the positive and negative address pulses cannot be simultaneously canceled in the writing operation of each pixel, but the DC level shift width in the even frame and the DC level shift in the odd frame are not eliminated. By balancing the widths, the averaged DC level shift over two even and odd frames can be reduced.

Next, a description will be given of a second embodiment in which the present invention is applied to an active matrix type display panel of the opposed matrix system. Before describing the second embodiment, the opposed matrix system will be briefly described. The opposed matrix method reduces the occurrence of defects due to the crossing structure of bus lines, which has been a problem in the production of conventional active matrix display panels, and enables the simplification of the production process and high yield. This is a method proposed for this purpose, for example, disclosed in Japanese Patent Application Laid-Open No. 61-235815.

FIG. 4 is an exploded perspective view showing an example of a conventional opposing matrix type active matrix type liquid crystal display panel, which is disclosed in the above-mentioned JP-A-61-235815. As shown in FIG. 4, a conventional opposing matrix type active matrix type liquid crystal display panel 50 is provided with a glass substrate 50 which is disposed oppositely.
a, a plurality of scan bus lines 52, a pixel electrode 55 of a liquid crystal cell provided for each pixel, and a thin film transistor (TFT) 51 for controlling the pixel electrode 55 are formed on one of the glass substrates 50a. On the other glass substrate 50b, a data bus line 53 extending in a direction orthogonal to the scan bus line 52 is formed as a counter electrode of a liquid crystal cell. Here, reference numeral 56 indicates a reference voltage bus line.

That is, in the active matrix type liquid crystal display device 50 of the opposed matrix type, the pixel electrode 55 which is one electrode of the liquid crystal cell is connected to the source electrode which is one controlled electrode of the TFT 51 and the other electrode of the liquid crystal cell. Are connected (also used) to the data bus line 53, and the liquid crystal cell is connected between the TFT 51 and the data bus line 53. Also, TF
The drain electrode serving as the other controlled electrode of T51 is commonly connected to a reference voltage bus line 56 formed in parallel with the scan bus line 52.

As described above, the conventional active matrix type liquid crystal display device 50 of the opposed matrix type has the following features.
Since the scan bus lines 52 and the data bus lines 53 arranged in a straight line are formed on one glass substrate 50a and the other glass substrate 50b which are arranged to face each other, no intersection of the bus lines occurs. Thus, the production yield can be improved.

FIG. 5 is a diagram showing the configuration of a second embodiment in which the present invention is applied to a facing matrix system. As shown in FIG. 5, in the active matrix type liquid crystal panel of this embodiment, pairs of pixel electrodes 65 ₁ and 65 adjacent in the row direction are provided.
₂ is connected to another reference voltage bus line 66 provided at a symmetrical position with respect to each pixel by TFTs 61 ₁₁ and 61 ₁₁ respectively.
They are connected via 1 ₁₂ , 61 ₂₁ and 61 ₂₂ . Here, the gate electrode of the TFT 61 ₁₁ and TFT 61 ₂₁ is connected to the scan bus line 62 ₁ disposed on the upper side of the pixel row, TFT 61 ₁₂ and TFT 61 ₂₂ gate electrode of which is connected to the scan bus line 62 _{and second} lower ing. Also,
Stripe electrodes made of ITO provided on a counter substrate (corresponding to the glass substrate 50b in FIG. 4) is also used as the data bus lines 63 are formed as the width of two pixels corresponding to the pixel pair 65 _1, 65 ₂ ing. The address pulse is substantially 1/2 t _H shifted by 1/2 horizontal scanning period (1/2 t _H ) in the same manner as described in the first embodiment.
A pulse having a width is sequentially applied, and a data signal waveform synchronized with the pulse is applied to the data bus line, or a signal whose polarity is inverted for each frame is applied.

In the second embodiment, by adopting the above configuration, not only the number of data bus lines can be reduced to 1/2 of the conventional one but also the IT bus on the counter substrate side.
The line width of the O-stripe electrode can be made twice as large as that of the normal opposing matrix system, and the effect of facilitating the production of the opposing-side ITO stripe electrode is also brought about. In the first and second embodiments, one pixel electrode has two pixels.
TFTs of different polarities are connected, and address pulses of different polarities are applied at the same time to cancel out the generation of DC components due to parasitic capacitance. As a result, since two switching elements are connected to one pixel electrode, there is an advantage that the switching element operates even if one switching element fails, but one switching element is sufficient for the operation of the pixel. , One of which acts essentially as a compensation pulse.

As shown in FIGS. 1 and 5, two scan bus lines and four TFTs are formed axially symmetrically with respect to the central axis of the pixel row, so that the pixel electrode and the upper and lower scan bus lines are connected. It is easy to make the respective parasitic capacitances between them almost the same value. In order to prevent the generation of a DC component by applying an address pulse having a symmetric reverse polarity,
It is necessary that these two parasitic capacitances are equal. This means that the address signal shown in FIG. 2 is applied if the parasitic capacitance between the pixel electrode and the upper and lower scan bus lines is the same even without one type of switching element connected to each pixel. This means that generation of a DC component can be prevented. Therefore, in the first embodiment, generation of a DC component can be prevented even if one type of switching element is eliminated, and a third embodiment is shown in FIG.

As shown in FIG. 6, the active matrix type liquid crystal display panel of this embodiment has a plurality of scan bus lines 12 ₁ and 12 ₂ and the scan bus lines 12 ₁ .
A plurality of data bus lines 13 perpendicular to the _1, 12 _2,
Pixel electrode pairs 15 ₁ , 15 arranged in a matrix
₂ , TFTs 11 ₁ and 11 ₂ of the same polarity corresponding to pixels connected to the scan bus line and the data bus line,
It has a liquid crystal electrically connected to the pixel electrode and controlled by the TFTs 11 ₁ and 11 ₂ .

As shown, the scan bus line 1
2₁, 12_TwoIs one pixel row (in FIG.
Two rows above and below the pixel row)
Bus line 12₁, 12_TwoDirection, that is, each pixel row
At the adjacent pixel electrode pair 15 ₁, 15_TwoCorresponding to
TFT11₁, 11_TwoEach control electrode (gate electrode)
Two scan bus lines 1 provided on both sides of the element
2₁, 12_TwoAre connected separately. Sand
And TFT11₁Gate electrode is scan bus line 1
2 ₁And the TFT 11_TwoGate electrode is
Canvas line 12_TwoIt is connected to the. Furthermore, T
FT11₁Is a pixel electrode pair 15₁Connected to
And TFT11_TwoIs a pixel electrode pair 15
_TwoAnd the TFT 11₁Drain electrode
And TFT11_TwoOf the same data bus
Commonly connected to line 13.

[0046] As apparent from comparison with the configuration 1, the third embodiment to remove any set of Nch-type TFT 11 ₁₁ and 11 _22, or Pch-type TFT 11 ₁₂ and 11 ₂₁ in the first embodiment Things. In FIG. 6, the TFT 11 ₁ ,
11 ₂ and a Nch type, Nch-type TFT and FIG. 1
Are inverted with respect to each data bus line.

With the above configuration, each of the pixel electrodes 15 ₁ ,
Equal the respective parasitic capacitance between the 15 ₂ and the upper and lower scan bus lines 12 _1, 12 _2, and applies the same drive signal as the first embodiment as shown in FIG. The positive pulse voltage waveform V _{s1, m} applied to the upper side of the scan bus lines 12 ₁ TFT 11 ₁ is conductive. Since the negative pulse at this time the voltage waveform V _{s2, m} in the lower scan bus line 12 ₂ is applied, TFT 11 ₂ is not conductive, the occurrence of the DC component of the pixel electrode 15 ₁ by the parasitic capacitance is canceled It is.

[0048] Since the positive pulse is applied to the scan bus line 12 _{and second} lower when the negative pulse is applied similarly to the upper scan bus lines 12 _1, TFT 11
₁ conducts the TFT 11 ₂ without conducting compensation operation of the DC voltage generator is also performed. However, in the above configuration,
The positional relationship between each of the pixel electrodes 15 ₁ and 15 ₂ and the upper and lower scan bus lines 12 ₁ and 12 ₂ is asymmetric, and the parasitic capacitance between them is usually not the same. Therefore, in the present embodiment, as shown in FIG. 6, the scan bus lines 12 ₁ , 1
2 to extend the extension 17 from _two near each pixel electrode 15 _1, 15 ₂ are adjusted parasitic capacitance. When such adjustment of the parasitic capacitance is not performed, a method of adjusting the voltage value of the compensation pulse to a value different from that of the address pulse is also effective.

FIG. 7 shows a fourth embodiment in which the configuration of the third embodiment is applied to an active matrix type display device of a counter matrix system.
FIG. 14 is a diagram illustrating an example, in which the same drive signals as in the third example are applied. Figure 8 is a diagram showing a layout on a substrate on which the scan bus lines 62 _1, 62 ₂ in the fourth embodiment there. In the figure, 61 ₁ and 61 ₂ are TFTs
, And the 62 _1, 62 ₂ is a scan bus line,
65 _1, 65 ₂ is the pixel electrode, 66 is a reference voltage bus line. 67 ₁ and 67 ₂ are extensions extending from the scan bus lines 62 ₁ and 62 ₂ along the pixel electrodes 65 ₂ and 65 ₁ , respectively, so that the parasitic capacitances are the same.

In the first to fourth embodiments, two scan bus lines are provided for each pixel row. However, in manufacturing a liquid crystal panel, it is desirable that the number of scan bus lines be as small as possible. The fifth embodiment fulfills this requirement. FIG. 9 is a diagram showing the configuration of the fifth embodiment. One scan bus line 12 is provided on the upper side in the scanning direction of each pixel row, and one pixel electrode 1 of each pixel pair is provided.
5 ₁ is connected to the data bus line 13 via the Nch-type TFT 11 _1, the other pixel electrode 15 ₂ Pch-type T
Connected to the same data bus line 13 via the FT11 _2. The gate electrodes of the _two TFTs 11 ₁ and 11 ₂ are connected to the same scan bus line 12.

Also in this embodiment, each pixel electrode 15 ₁ ,
It is desirable parasitic capacitance is the same between 15 ₂ and the scan bus line 12 of the upper and lower sandwiching the, or adjust the parasitic capacitance is provided an extension extending from the scan bus line 12 described above, the pixel The parasitic capacitance is adjusted by changing the distance between the row and the upper and lower scan bus lines, but is not shown in the figure.

FIG. 10 shows drive signals in the fifth embodiment. In the figure, _VD is a data voltage applied to the data bus line 13, and this voltage is applied to each electrode. Here, the polarity is changed to the positive / negative reverse polarity with a cycle of 1/2 t _H. V _{s, m} is a voltage waveform applied to the m-th scan bus line, and V _{s, m + 1} is a voltage waveform applied to the (m + 1) -th scan bus line.

As shown in FIG.
The applied voltage waveform is 1 / 2t_HAddress pulse of continuous width
And a compensating pulse portion indicated by oblique lines.
For example, V_{s, m}Pixel of the m-th row by the positive address pulse of
One pixel electrode 15 of the pair₁TFT11 connected to₁But
And the data voltage of the data bus line 13 is applied to the pixel electrode
Fifteen₁Is applied to At this time, the scan attached to the next pixel row
V on the campus line _{s, m + 1}Negative compensation pulse is applied
It is. Thereby, the pixel electrode 15 in the m-th row₁Of the DC component of
Occurrence can be prevented. Similarly V_{s, m}Negative address pulse
And V_{s, m + 1}DC component is generated by the positive compensation pulse of
The pixel electrode 15 in the m-th row_TwoData voltage to
Is applied.

Since the compensation pulse is applied to all the scan bus lines so as to compensate for the previous pixel row, for example, the voltage waveform Vs _{, m} applied to the mth scan bus line has the compensation pulse as the address pulse. Is added to the waveform as shown in the figure. Therefore, the data voltage applied to the previous pixel row is temporarily applied by the compensation pulse, and the applied voltage of the pixels LC _{m, 2n} and LC _{m, 2n + 1 in} the m-th row is V
It changes as shown by LC _{m, 2n} and VLC _{m, 2n +1} . That is, the first negative compensation pulse causes the Pch-type TFT 11 _2
Are conducted, the pixel LC _{m, 2n + 1} is connected to the pixel LC _{m-1,2n + 1}
, And this state continues for a period of 3/2 t _H during which the normal data voltage is applied. Similarly, the pixel L
The data voltage of the pixel LC _m-1,2n is applied to C _{m, 2n} , and this state continues for a period of １ ／ t _H.

As described above, in this embodiment, the data voltage of the previous pixel row is temporarily applied to each pixel.
An active matrix type liquid crystal display panel usually used for a display panel of a personal computer or the like has 400 or more pixel rows, and a ratio of a period in which another data voltage is applied is at most 0.4% or less. Yes, no problem in practical use.

The structure and the driving method of the fifth embodiment can be applied to the opposed matrix system, but the description is omitted. In the above-described embodiment, a liquid crystal is used as the electro-optical element. As the electro-optical element, various elements such as an electroluminescent element and an electrochromic element can be used. Further, it goes without saying that various structures, shapes, materials, and the like of the active matrix display device (panel) can be used in addition to those described above and can be modified.

As described above, according to the active matrix type display device of this embodiment, the driver I which has been a large cost factor of the active matrix type display device up to now.
After significantly reducing the number of C, the generation of DC components due to parasitic capacitance, which is a problem in active matrix display devices, can be significantly reduced, realizing an active matrix display device with excellent display characteristics. can do.

[0058]

As described above, according to the active matrix display device of the present invention, the cost of the active matrix display device can be reduced, and the display quality can be improved. .

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the active matrix display device of the present invention.

FIG. 2 is a diagram illustrating drive signals according to the first embodiment.

FIG. 3 is a diagram showing a modified example of a drive signal in the first embodiment.

FIG. 4 is an exploded perspective view showing an example of an active matrix type liquid crystal display panel of a facing matrix type.

FIG. 5 is a diagram showing a configuration of a second embodiment.

FIG. 6 is a diagram showing a configuration of a third embodiment.

FIG. 7 is a diagram showing a configuration of a fourth embodiment.

FIG. 8 is a diagram showing a scan bus line having a parasitic capacitance adjusting extension in a fourth embodiment.

FIG. 9 is a diagram showing a configuration of a fifth embodiment.

FIG. 10 is a diagram showing drive signals in a fifth embodiment.

FIG. 11 is a diagram illustrating a basic configuration of an active matrix display device.

FIG. 12 is a diagram showing an equivalent circuit of an active matrix type liquid crystal panel.

FIG. 13 is a diagram showing a conventional example in which data bus lines are shared.

FIG. 14 is a diagram illustrating an address signal in the example of FIG. 13;

FIG. 15 is a diagram showing a configuration of a conventional example for preventing generation of a DC component.

FIG. 16 is a diagram showing drive signals in the example of FIG.

[Explanation of symbols]

11 _1, 11 _2, 61 _1, 61 ₂ ... switching elements _{(TFT) 12,12 1, 12 2} , 62 1, 62 2 ... scan bus lines 13,63 ... data bus lines 15 _1, 15 _2, 65 _1, 65 ₂ ... pixel electrode 66, 66 ₁ , 66 ₂ ... reference voltage bus line

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-178632 (JP, A) JP-A-4-14090 (JP, A) JP-A-62-18987 (JP, A) JP-A-63-1987 241524 (JP, A) JP-A-2-42420 (JP, A) JP-A-3-38689 (JP, A) JP-A-59-119390 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/1368 G02F 1/133 550

Claims (3)

(57) [Claims] A plurality of scan bus lines (12 ₁ , 1
2 ₂ ) and data bus lines (13), pixel electrodes (15 ₁ , 15 ₂ ) arranged in a matrix, switching elements corresponding to the pixels connected to the scan bus lines and the data bus lines, and Electrode (1
5 ₁ , 15 ₂ ), an active matrix type display device including an electro-optical element filled between electrodes facing each other and controlled by the switching element, the display element being adjacent to the scan bus line (12 ₁ , 12 ₂ ). The pixel electrode pairs (15 ₁ and 15 ₂ ) are connected to the same data bus line (13), and the scan bus lines (12 ₁ and 12 ₂ ) sandwich the pixel row with respect to one pixel row. The switching elements are provided on the upper and lower sides as described above, and the switching elements are first type switching elements (11 ₁₁ and 11 ₂₂ ) that are brought into conduction by applying a positive voltage to the control electrode, and and it consists of two elements of a second type of switching elements become conductive by applying a negative voltage (11 _12, 11 _21), both of said pixel pairs The pixel both are connected to the said first type of switching elements second type switching element, a first type of switching elements connected to one of the pixels of the pixel pair (11 _11), the other The second type of switching element (11 ₂₁ ) connected to one pixel is connected to _one scan bus line (12 ₁ ) adjacent to the pixel row, and the second type switching element (11 ₂₁ ) is connected to one pixel of the pixel pair. The switching element (11 ₁₂ ) of the type and the switching element (11 ₂₂ ) of the first type connected to the other pixel are connected to another scan bus line (12 ₂ ) adjacent to the pixel row. Are applied to the scan bus lines (12 ₁ , 12 ₂ ).
Address pulse is less than half of one horizontal scanning period.
When the polarity is reversed alternately for each display frame
At the same time, the adjacent scan bus lines (12 ₁ , 1
An active matrix type display device characterized in that the application order is switched between 2 ₂ ) . 2. A plurality of scan bus lines (62 ₁ , 62 ₂ ) and pixel electrodes (65 ₁ , 65 ₂ ) arranged in a matrix on one substrate and a plurality of pixel electrodes connected to the scan bus lines. A switching element, and another opposing pixel electrode on the other substrate and a data bus line (63) connected thereto.
₁ , 65 ₂ ) and an electro-optical element filled between the opposed pixel electrodes and controlled by the switching element, the active matrix type display device being adjacent to the scan bus line (62 ₁ , 62 ₂ ). two opposing pixel electrode facing the pixel electrode pairs (65 _1, 65 ₂₎ which are connected to the same data bus line (6 3), the scan bus line (62 _1, 62 ₂₎ is the one Two switching elements are provided above and below the pixel row so as to sandwich the pixel row, and the switching element is a first type switching element (61) that is turned on by applying a positive voltage to the control electrode. _11, 61 _22), or two elements of the second type of switching elements become conductive by applying a negative voltage to the control electrode (61 _12, 61 ₂₁₎ The first type switching element and the second type switching element are both connected to both pixels of the pixel pair, and the first type connected to one pixel of the pixel pair. a switching element (61 _11), a second type of switching elements (61 ₂₁₎ connected to the other pixels is connected to one scan bus line adjacent to the pixel row (6 2 _1), the pixel A second type of switching element (61 ₁₂ ) connected to one pixel of the pair and a first type of switching element (61 ₂₂ ) connected to the other pixel are used for another scan adjacent to the pixel row. is connected to the bus line (6 2 _2), it is applied to the scan bus line (62 _1, 62 ₂₎
Address pulse is less than half of one horizontal scanning period.
When the polarity is reversed alternately for each display frame
At the same time, the adjacent scan bus lines (62 ₁ , 6
An active matrix display device characterized in that the order of application is switched between 2 ₂ ) . 3. A plurality of scan bus lines (62) and pixel electrodes (65) arranged in a matrix on one substrate.
_1, 65 ₂₎ and the scan pixels connected to the bus line corresponding switching element (62 _1, 62 ₂₎ and having a data bus connected with another opposing pixel electrode to the other substrate An active matrix display device having a line (63) and comprising an electro-optical element filled between the pixel electrodes (65 ₁ , 65 ₂ ) and the counter pixel electrode and controlled by the switching element; two opposing pixel electrode facing the pixel electrode pairs (65 _1, 65 ₂₎ adjacent in the direction of the scan bus lines (62) are connected to the same data bus line (6 3), the scan bus line Are provided on the upper side in the scanning direction for each pixel row, and the switching elements (61 ₁ , 61 ₂ ) apply a positive voltage to the control electrode. Therefore, the pixel electrode pair includes a first type of switching element that is in a conductive state, and a second type of switching element that is in a conductive state when a negative voltage is applied to the control electrode. (65 _1, 65 ₂₎ in the different two switching elements (61 _1, 61 ₂₎ are connected respectively, the same pixel row switching element (61 _1, 61 ₂₎ are the same scan bus line (62) It is connected to, wherein the scan bus line (6 2), 1/2 positive and negative polarity opposite consecutive address pulse of the timing obtained by shifted horizontal scanning period has half or less of the pulse width of one horizontal scanning period is applied, the scan bus line (6 2)
An active matrix type display device, wherein a compensation pulse obtained by inverting the address pulse and the positive / negative pulse is applied to the next scan bus line sandwiching the pixel row driven by (1).