JPH0635418A - Method for driving active matrix type thin film transistor liquid crystal panel - Google Patents

Abstract

PURPOSE:To make the mean effective voltage of a liquid crystal cell uniform and to lower the dielectric strength of switching drivers for gate bus lines and drain bus lines. CONSTITUTION:The group of pixel electrodes 14 connected via thin film transistors(TR) 13 are arranged zigzag alternately in the direction of gate bus lines 11 to constitute pixel electrodes 14 in the direction of two adjacent gate bus lines 11 and one counter electrode 15 is provided on the group of the pixel electrodes 14 and the even-numbered and odd-numbered counter electrodes among plural counter electrodes are mutually connected and switching elements are provided. A voltage signal inverted in the polarity of voltage data at a period twice as long as one scanning line period is applied to respective drain bus lines 12 and the polarity data of the group of pixel electrodes 14 which are different in polarity between adjacent counter electrodes 15 and correspond to the respective counter electrodes 15 and a voltage signal including an offset voltage and an effective voltage correction voltage corresponding to the threshold voltage of liquid crystal are supplied to the respective counter electrodes 15 to write the voltage in the pixel electrodes 14 with the selective signal of the gate bus lines 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving an active matrix type thin film transistor liquid crystal panel.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, Journal of Television Society Vol. 42, No.
1, P. 10-16 and P.I. 23-29. Conventionally, an active matrix type liquid crystal panel, especially one using a thin film transistor (TFT-L
As a driving method of (CD), several kinds of different methods are used depending on the difference of the alternating method, but the concept of the voltage supply method is the same. So, as a typical example,
A driving method (hereinafter, referred to as a frame mode) for performing alternating current for each scanning cycle will be described.

FIG. 12 is a block diagram of such a conventional active matrix type thin film transistor liquid crystal panel, and FIG. 13 is a drive timing chart thereof. As shown in the figure, the active matrix thin film transistor liquid crystal panel is
In general, a gate bus line 51 and a drain bus line 52 are arranged orthogonally on a rear substrate, and a thin film transistor (T) is provided at the intersection as a switching element corresponding to each pixel electrode.
FT) 53, a transparent counter electrode 54 is provided on the front substrate, an alignment film that has been subjected to an alignment treatment in an appropriate direction is provided on the surfaces of both substrates, and the alignment films of both substrates are arranged to face each other through a liquid crystal layer. And a polarizing film is attached to the rear surfaces of the front substrate and the rear substrate such that their polarization axes are parallel or perpendicular to each other, and the voltage of the pixel electrode supplied via the TFT 53 and the counter electrode 54. The liquid crystal 55 in the portion sandwiched between the two electrodes is switched by the potential difference from the voltage.

As a TFT switching means, a scanning circuit 60 is connected to the gate bus line 51, and a data circuit 70 is connected to the drain bus line 52.
ON voltage V from the scanning circuit 60 as a gate selection signal of
_{G (+)} and OFF voltage V _{G (-)} are the drain selection and luminance data signal of the TFT 53, and the positive write voltage V _{D (+)} and the negative write voltage V _{D (-)} are output from the data circuit 70. Supplied.

As shown in FIG. 13, the voltage V _S of the pixel electrode written by the TFT 53 causes a voltage fluctuation twice in the voltage holding state. First, when the gate selection signal of the TFT 53 changes from the ON state to the OFF state, the voltage V _{S of the} pixel electrode connected to the TFT 53 to which the selection signal is supplied is ΔV due to the parasitic capacitance C _gS of the _TFT 53. _It fluctuates by ₁ .

Secondly, when the data signal changes to a polarity opposite to the polarity at the time of writing, it changes by ΔV ₂ due to the electric field effect between the pixel electrode and the drain bus line 52.
For this reason, the potential difference between the pixel electrode and the counter electrode is made uniform with respect to the variation of the voltage V _S of the pixel electrode during the positive polarity writing and during the negative polarity writing. Voltage V _COM is supplied.

FIG. 14 shows the electro-optical characteristics of a TN liquid crystal cell in the case where two polarizing films are attached so that their polarization axes are parallel to each other. The TN liquid crystal cell used in the active matrix type thin film transistor liquid crystal panel has a threshold voltage V _{TH at} which the light transmittance sharply increases and a saturation voltage V at which the light transmittance does not vary with respect to the potential difference between the pixel electrode and the counter electrode. _{In the} presence of _SAT , in the voltage range ΔV from V _{TH to} V _SAT , the voltage fluctuation shows a change in light transmittance. For this reason,
In order to achieve a complete ON state, V in the positive polarity
_SAT <V _S −V _COM , V _SAT <V _COM in negative polarity
In order to set a voltage condition of −V _S and achieve a complete OFF state, a voltage condition of V _TH > V _S −V _{COM in} the positive polarity and V _TH > V _COM −V _{S in} the negative polarity are set. By doing so, the liquid crystal cell can be switched.

[0008]

However, in the driving method described above, when the time from the writing of the data signal to the pixel electrode until the voltage polarity of the drain bus line is inverted is different, for example, depending on the scanning circuit. Comparing the voltage V _{S of the} pixel electrode connected to the selected first gate bus line and the Nth gate bus line via the TFT, respectively, the electric field effect between the pixel electrode and the drain bus line shows that Since the period in which the voltage fluctuates by ΔV ₂ is different, the average effective voltage applied to the liquid crystal layer for each scanning cycle is different, and the light transmittance is also different.

Further, for the switching of the liquid crystal layer, it is sufficient to generate a voltage fluctuation of ΔV between the pixel electrode and the counter electrode, but the voltage of the counter electrode is fixed and the voltage of the pixel electrode is positive. In order to change to a negative polarity, the driver of the drain bus line requires a switching voltage of V _SAT × 2 [corresponding to (V _TH + ΔV) × 2], and ΔV + V _TH ×
2 extra switching voltage is needed,
This has been an obstacle to lowering the breakdown voltage of the driver.

The object of the present invention is to disperse the average effective voltage applied to the liquid crystal layer for each scanning period and the extra switching voltage V _TH × 2 + Δ applied to the drain bus line.
In order to reduce or eliminate V, pixel electrode groups connected to one gate bus line via TFTs are alternately arranged in a staggered pattern in the gate bus line direction, and two pixel electrode groups arranged in the gate bus line direction are arranged. In the configuration controlled by a book gate bus line, each counter electrode is provided corresponding to each pixel electrode group arranged in the gate bus line direction, and adjacent drain buses and adjacent counter electrodes show different polarities, By the alternating method in which the polarities are inverted every double the period of one scanning line, the variation of the average effective voltage is eliminated, and the positive polarity data and the negative polarity data supplied to each drain bus line are mutually inverted. The data structure is such that it is supplied as the generated voltage information, each counter electrode has the same voltage amplitude, and the write voltage is compensated by the voltage amplitude, It is to provide an excellent method of driving an active matrix type thin film transistor liquid crystal panel to achieve the lowering of the withstand voltage of the switching driver Surain and the gate bus line.

Another object of the present invention is to arrange pixel electrode groups connected to one gate bus line via a TFT in the line direction, and to connect two adjacent gate bus lines via a TFT. In a pixel electrode group to be connected, one wavy counter electrode is provided for a pixel electrode group selected from two gate bus lines alternately in a zigzag direction in the gate bus line direction, and adjacent drain electrodes are provided. The bus lines and adjacent counter electrodes show different polarities.
By the alternating method in which the polarities are inverted every double the scanning line period, the variation of the average effective voltage is eliminated, and the positive polarity data and the negative polarity data supplied to each drain bus line are mutually inverted. An excellent active matrix type which has a data structure which is supplied as voltage information, has an equal voltage amplitude to each counter electrode, and compensates a write voltage by the voltage amplitude to achieve a low breakdown voltage of a switching driver of a drain bus line. It is an object to provide a driving method of a thin film transistor liquid crystal panel.

[0012]

In order to achieve the above object, the present invention provides a gate bus line and a drain bus line which are arranged orthogonally on a back substrate, and which is provided at the intersection of the gate bus line and the drain bus line. A thin film transistor corresponding to each pixel electrode is provided, a transparent counter electrode is provided on the front substrate, alignment films that are oriented in appropriate directions are provided on the surfaces of the back substrate and the front substrate, and the alignment films of both substrates are provided. In a method for driving an active matrix thin film transistor liquid crystal panel, which is arranged so as to face each other with a liquid crystal layer interposed therebetween and is adhered, and a polarizing film is adhered to the back surfaces of the back substrate and the front substrate, one gate bus line is provided with a thin film transistor interposed therebetween. Pixel electrode groups to be connected are alternately arranged in a zigzag pattern in the direction of the gate bus lines to correspond to two adjacent gate bus lines. A pixel electrode group in the gate bus line direction is formed by the partial pixel electrode group, one counter electrode is provided for the pixel electrode group arranged in the gate bus line direction, and an odd-numbered counter electrode of the plurality of counter electrodes is provided. The electrodes are connected to each other and the even-numbered counter electrodes are connected to each other, and the switching elements are provided to the odd-numbered counter electrode groups and the even-numbered counter electrode groups. A voltage signal indicating a voltage in which the polarity of the voltage data is inverted in a cycle twice as long as that of the positive polarity and the voltage data of the negative polarity is inverted to each other is supplied to each drain bus line, Polarity is different, and the voltage data including the polarity data of the pixel electrode group corresponding to each counter electrode, the offset voltage corresponding to the threshold voltage of the liquid crystal, and the effective voltage correction voltage are countered. It is supplied to the electrode, in which to perform the voltage written to the pixel electrodes by the selection signal of the gate bus line.

Pixel electrode groups connected to one gate bus line via thin film transistors are arranged in the gate bus line direction, and pixel electrode groups connected to two adjacent gate bus lines via thin film transistors. In the configuration described above, one wavy counter electrode is provided for a pixel electrode group selected from two gate bus lines alternately in a zigzag direction in the gate bus line direction, and wavy counter electrodes that are not adjacent are connected to each other. However, the polarity of the voltage data of adjacent drain bus lines is different, and the polarity of the voltage data is inverted in a period twice as long as one scanning line period, and the positive and negative voltages are provided. A voltage signal indicating a voltage in which data is inverted from each other is supplied to each drain bus line, and the polarities of adjacent counter electrodes are different,
Further, a voltage signal including the polarity data of the pixel electrode group corresponding to each counter electrode, the offset voltage corresponding to the threshold voltage of the liquid crystal, and the effective voltage correction voltage is supplied to each counter electrode, and the pixel electrode is supplied to the pixel electrode by the selection signal of the gate bus line. Voltage writing is performed.

[0014]

According to the present invention, as described above, the pixel electrode groups connected to one gate bus line via the TFT are alternately arranged in the gate bus line direction in a zigzag pattern, and the pixel electrode groups are arranged in the gate bus line direction. The pixel electrode group arranged side by side is configured to be controlled by two gate bus lines, and each counter electrode is provided corresponding to each pixel electrode group arranged in the gate bus line direction,
Adjacent drain buses and adjacent counter electrodes have different polarities, and the polarity is inverted every two scanning line periods. By the alternating method, the average effective voltage applied to the liquid crystal layer is varied. Further, the positive polarity data and the negative polarity data supplied to each drain bus line are supplied as voltage information inverted from each other, and each counter electrode has an equivalent voltage amplitude.
By supplementing the write voltage, an extra switching voltage applied to the drain bus line can be eliminated.

Alternatively, one gate bus line may be provided with TF.
Pixels in which pixel electrode groups connected via Ts are arranged in the line direction, and the pixel electrode groups connected to two adjacent gate bus lines via TFTs are alternately selected in a staggered pattern in the gate bus line direction. One corrugated counter electrode is provided for the electrode group, adjacent drain bus lines and adjacent counter electrodes have different polarities, and each of them has a period twice as long as one scanning line period. By the alternating method of reversing the polarity, the variation of the average effective voltage applied to the liquid crystal layer is eliminated, and the positive polarity data and the negative polarity data supplied to each drain bus line are supplied as the voltage information inverted from each other, and Each counter electrode has the same voltage amplitude, and by supplementing the write voltage with the voltage amplitude, it is possible to eliminate the extra switching voltage applied to the train bus. .

Therefore, the average effective voltage of the liquid crystal cell can be made uniform and the withstand voltage of the drain bus line and gate bus line switching drivers can be reduced. Further, this driving method can obtain the same effect even when an analog voltage is input to the drain bus line, and thus can be sufficiently applied to the grayscale driving of the active matrix thin film transistor liquid crystal panel.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a schematic perspective view of an active matrix thin film transistor liquid crystal panel showing an embodiment of the present invention. As shown in this figure, a gate bus line 11 and a drain bus line 12 are arranged orthogonal to each other on a transparent rear substrate, and a TFT 13 is provided at the intersection thereof.
Transparent pixel electrodes 14 corresponding to individual display cells
Connect to. And TF is connected to one gate bus line 11.
Pixel electrode groups 14 connected through T13 are alternately arranged in a zigzag pattern in the gate bus line direction, and two adjacent gate bus lines 11 switch pixel electrode groups arranged in a line in the gate bus line direction. Configure Further, an alignment film that has been subjected to an alignment treatment in an appropriate direction is provided on the back substrate.

On the other hand, the transparent counter electrode 1 is divided into the same number of lines as the pixel electrode group on the transparent front substrate.
5, the counter electrodes corresponding to the odd-numbered drain bus lines and the counter electrodes corresponding to the even-numbered drain bus lines are connected to each other to provide an alignment film that is oriented in an appropriate direction. The alignment films of the back substrate and the front substrate are faced to each other, and the pixel electrode group arranged in a line and one counter electrode are aligned so as to face each other, and an appropriate gap is provided between the two substrates, Is injected and then sealed, and a polarizing film is attached to the exposed surfaces of both substrates so that the polarization axes are parallel or perpendicular to each other. Reference numeral 15a is a portion facing the pixel electrode.

FIG. 2 is a schematic configuration diagram of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention,
3 is a schematic block diagram of a data circuit of an active matrix thin film transistor liquid crystal panel showing an embodiment of the present invention, and FIG. 4 is a diagram showing a common variation circuit of an active matrix thin film transistor liquid crystal panel showing an embodiment of the present invention.

As shown in these figures, the number of gate bus lines 11 is N + 1 and the number of drain bus lines 12 is M.
Then, the scanning circuit 20 is connected to the N + 1 gate bus lines 11, and the ON voltage V _{G (+)} ′ is sequentially supplied from the first gate bus line 11 in time sequence for t _on time corresponding to one scanning time. , A data circuit 30 including a data generation unit 31, a data inversion unit A32, a data inversion unit B33, a data output unit A34, and a data output unit B35 is connected to the M drain bus lines 12, and the brightness data and the polarity data are transmitted. Including the voltage data, the buffers 41 and 42, the operational amplifiers 43 and 44, and the MO to the opposing electrode group divided into two systems.
A voltage including an offset voltage and an effective voltage correction voltage corresponding to the polarity data corresponding to the voltage data supplied to the drain bus line 12 and the threshold voltage of the liquid crystal 16 by connecting the common fluctuation circuit 40 configured by the SFETs 45 and 46 and the like. Supply a signal.

FIG. 5 shows the timing of the voltage data supplied to the drain bus of the active matrix type thin film transistor liquid crystal panel showing the embodiment of the present invention. In this embodiment, one gate bus line 11 alternately switches the pixel electrodes arranged in a zigzag pattern in the gate bus line direction. Therefore, in the first gate bus line and the (N + 1) th gate bus line, respectively. TF connected to even-numbered pixel electrodes in the gate bus line direction
Only the TFTs connected to T and the odd-numbered pixel electrodes are switched. Therefore, when writing one frame of image data, the odd-numbered pixel electrode groups in the gate bus line direction are written at the write timing from the second gate bus line to the (N + 1) th gate bus line.
Further, voltage data must be supplied from the drain bus lines to the even-numbered pixel electrode groups in the gate bus line direction at the write timing of the first gate bus line to the Nth gate bus line.

Therefore, the data generator 3 of the data circuit 30
1, the luminance data of one line is divided into the data of the odd-numbered display cells in the gate bus line direction and the data of the even-numbered display cells, and the data of the odd-numbered display cells in the gate bus line direction is Dummy data d _D is the data corresponding to the first gate bus line, and data d ₁ of the first line is the data corresponding to the second gate bus.
, As the data corresponding to the third gate bus, the data d ₂ of the second line, ..., The data d _N of the N line as the data corresponding to the (N + 1) th gate bus are sequentially created as data 1.

As the data of the even-numbered display cells in the gate bus line direction, the data d ₁ of the first line as the data corresponding to the first gate bus and the second line as the data of the second gate bus. Data d ₂ of
The data 2 for sequentially supplying the data d _N of the Nth line as the data corresponding to the Nth gate bus and the dummy data d _D as the data corresponding to the N + 1th gate bus are created.

In the data generator 31, the odd-numbered drain bus and the even-numbered drain bus have different write polarities, and the polarities of the adjacent counter electrodes are different at every double scan line cycle. An alternating signal 1 corresponding to the odd-numbered drain buses and an alternating signal 2 corresponding to the even-numbered drain buses are created as the alternating signals whose polarities are inverted.

Further, the data 1 and the alternating signal 1 are calculated by the data inverting section A32 to create voltage data and data 3 including the brightness data and the polarity data, and the data output section A34.
The odd-numbered drain buses D ₁ , D _3, ..., D
Output to _M-1 . Similarly, the data 2 and the AC signal 2 are calculated by the data inversion unit B33 to create voltage data and data 4 including the brightness data and the polarity data, and the data output unit B35 outputs even-numbered drain buses D ₂ , D.
₄ ..., Output to D _M.

The voltage data setting conditions for each drain bus output from the data circuit 30 are as follows: ON voltage V _{D (+)} ', OFF voltage V _{D (-)} ', and negative polarity in positive polarity writing. In writing, since the ON voltage V _{D (-)} 'and the OFF voltage V _{D (+)} ' are set, the voltage amplitude can be set to be equal to ΔV shown in FIG. 14, and V _{D (+)} '-V
_Since it is given under the condition of _{D (-)} '= V _SAT -V _TH = ΔV,
Compared with the conventional example of FIG. 13, the amplitude of the drain voltage is V _TH ×
It can be reduced by 2 + ΔV.

FIG. 6 is a timing chart of a common variation circuit of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention. In this embodiment, instead of setting the amplitude of the drain voltage to be equal to ΔV, a voltage such as an offset voltage of the liquid crystal is supplied by the voltage signal of the counter electrode. Therefore, an offset voltage of the write polarity of the even drain bus is written to the counter electrode corresponding to the odd line at the write timing of the first gate bus line, and an offset voltage of the odd drain bus is written at the write timing of the second gate bus line. A voltage signal is supplied to supplement the offset voltage of the write polarity. That is, at the write timing of the odd-numbered gate bus line, a voltage signal for supplementing the offset voltage of the write polarity of the even-drain bus is supplied, and at the write timing of the even-numbered gate bus line, the offset voltage of the odd-drain bus write polarity is written. The voltage signal V _COM A for replenishing the voltage and the like is supplied. On the other hand, at the write timing of the odd-numbered gate bus line, the counter electrode corresponding to the even-numbered line is supplied with a voltage signal for supplementing the offset voltage of the write polarity of the odd-numbered drain bus and the write timing of the even-numbered gate bus line. In this case, the voltage signal V _COM B is supplied to supplement the offset voltage of the write polarity of the even drain bus. Further, since the write polarities of the odd drain bus and the even drain bus are set to different write polarities at the same write timing, the voltage signal V _COM
A and V _COM B are also set to different write polarities at the same write timing.

An inverted signal DF satisfying the above conditions is created and supplied to the non-inverting logic buffer 41 and the inverting logic buffer 42 of the common variation circuit, respectively, and the operational amplifier 4 is used for each.
The resistance values R ₁ and R ₂ are set so as to have appropriate voltage amplitudes by 3, 44, amplified by R ₂ / R ₁ times, and output from the MOSFETs 45 and 46 respectively are V _COM A
And V _COM B.

FIG. 7 shows an active marker according to an embodiment of the present invention.
Trix type thin film transistor LCD panel liquid crystal cell etc.
It is a value circuit diagram. In the case of the driving method described above, the liquid crystal cell
The fluctuation of the effective voltage in the charge holding state is at least 3
It occurs in one condition. First connected to the pixel electrode
Immediately after writing to the TFT, the parasitic capacitance C of the TFT_gsBy
, ΔV₁′ ＝ [C_gs/ (C_gs+ C_LC)] ×
(V_{G (+)}′ -V_{G (-)}′) And then insert the pixel electrode
The two drain buses have a Δ
V_D1′, ΔV_D2When it changes only by ′, the pixel electrode and the two
Capacity C with rain bus_DP1And C_DP2By Δ
V₂′ ＝ (C_DP1/ C_LC) × ΔV_D1′-(C_DP2/
C_LC) × ΔV_D2′, And charge is stored between the pixel electrode and
The voltage of the counter electrode that performs the product is ΔV _COMWhen it fluctuates
And the parasitic capacitance C of the TFT_gsBy ΔV₃′ ＝ [C_gs/
(C _gs+ C_LC)] × ΔV_COMIs.

If the same TFT is formed in all the pixel electrodes, the potential fluctuation ΔV ₁ ′ has the same polarity and the same potential regardless of the write voltage and the write timing, and therefore the voltage supplied to the counter electrode. In the setting of, Δ
By setting the shift by V ₁ ′, the same effective voltage can be maintained in all liquid crystal cells.

The potential fluctuations ΔV ₂ ′ and ΔV ₃ ′ have different polarities of effective voltage fluctuation depending on the polarities at the time of writing. It shows the largest voltage fluctuation when it changes. Therefore, in each pixel electrode, if there is a short period and a long period in which the polarities of the two are changed with respect to the polarities at the time of writing, the average effective voltage is different, and display unevenness occurs.

FIG. 9 is a timing chart showing changes in driving voltage and pixel voltage of TFTs connected to an odd drain bus of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention. FIG. 10 shows an embodiment of the present invention. 6 is a timing chart showing changes in driving voltage and pixel voltage of a TFT connected to an even drain bus of an active matrix thin film transistor liquid crystal panel.

In this embodiment, the voltage signals V _COM A and V _COM B supplied to the counter electrodes are set by shifting the voltage fluctuation amount ΔV ₁ ′, and the polarities of the drain buses and the counter electrodes are Since the AC driving is performed in which the polarity is inverted at a period twice as long as one scanning line period,
V _S2A , V _S3A , ... V _{S (N + 1) A} , V _S1B , V _S2B , ...,
The waveform of the pixel electrode indicated by V _{SN B} is obtained, and for all the pixel electrodes, the period during which the polarities of the two drain buses and the counter electrode sandwiching the pixel electrode are the same as during writing, and the average The effective voltage becomes uniform.

Further, V _COM A and V supplied to the counter electrode
Average voltage variation ΔV ₂ ′ of all pixel electrodes calculated by analogy to the voltage signal of _COM B from the display data Δ
V ₂ ′ (average value) is the effective voltage loss caused by the voltage fluctuation of ΔV ₂ ′, and V in the state including the correction data.
In order to supply added _COM A and V _COM [Delta] V ₃ 'average voltage variation [Delta] V ₃ of' calculated from the voltage amplitude of B (average value) as the effective voltage loss in caused by the voltage variation of [Delta] V ₃ ', V The voltage waveforms of _COM A and V _COM B are changed to V _{D (+)} ′ − ΔV−V _TH −ΔV ₁ ′ − during positive polarity writing.
At the voltage level of [ΔV ₂ ′ (average value)] − [ΔV ₃ ′ (average value)], V _{D (−)} ′ + ΔV when writing with negative polarity
+ V _TH −ΔV ₁ ′ + [ΔV ₂ ′ (average value)] + [Δ
V ₃ ′ (average value)] set to a voltage level of ΔV + 2V
_When a voltage signal with a fluctuation amplitude of _TH + 2 × [ΔV ₂ ′ (average value)] + 2 × [ΔV ₃ ′ (average value)] is supplied and the amplitude of the voltage data output from the data circuit is set to ΔV Also, the average effective voltage of all pixels is ΔV
It can be made approximately the same as + V _TH .

FIG. 8 is an equivalent circuit diagram of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention. As shown in FIGS. 1 and 2, the active matrix type thin film transistor liquid crystal panel is provided with a large number of electrical wirings. Therefore, there is a wiring capacitance as a constituent condition of the liquid crystal panel, and a liquid crystal capacitance C of each display cell is present. _A loss current is generated when writing to _LC . The capacitance C _GD created by the intersection of the drain bus and the gate bus is
Each time the drain bus voltage changes, a loss current proportional to the amount of drain bus voltage change is generated in the gate bus and drain bus, and the capacitance created between the drain bus and the counter electrode via the liquid crystal layer. Similarly, C _DC causes the drain bus and the counter electrode to generate a loss current proportional to the amount of voltage change of the drain bus each time the voltage of the drain bus changes.

Here, although the amount of current generated by C _GD and C _DC existing in each display cell unit is not so large, it is a considerably large current in view of the wiring as a whole. For example, in order to discharge to the outside of the panel in a line cycle, it is necessary to reduce the resistance of the drain bus, the gate bus, and the counter electrode and increase the current capacity of the external driver connected to each wiring.

In this embodiment, when the polarities of the adjacent drain buses are different, and when the polarities are changed, the adjacent drain buses always have different polarities, for example, when one of them changes from the positive polarity to the negative polarity, The other will change from negative polarity to positive polarity. Therefore, the loss currents generated by the adjacent capacitances C _GD or by the capacitances C _DC adjacent to each other on one counter electrode divided for each line are currents flowing in opposite directions. Tend to cancel out.

Further, also in the adjacent counter electrodes divided for each line, when the polarities change, similarly, the adjacent counter electrodes inevitably change in voltage with different polarities. Therefore, the loss currents generated by the adjacent capacitors C _DC on one drain bus line also tend to cancel each other. Therefore, the loss current flowing through one gate bus line and drain bus line and the counter electrode divided for each line becomes very small, and the resistance of each wiring is reduced and the external driver connected to each wiring is reduced. It is possible to provide a liquid crystal panel that does not need to have a large capacity and is suitable for a large capacity and high definition of the liquid crystal panel.

FIG. 11 is an actuator showing a modified embodiment of the present invention.
Schematic structure of a live-matrix thin film transistor liquid crystal panel
It is a diagram. The details of this embodiment are shown in FIGS.
The active matrix type thin film transistor having the configuration described in detail.
Liquid crystal between each pixel electrode and counter electrode of the liquid crystal panel
Capacity C_LCAuxiliary capacitance C electrically parallel to_sSet up 17
The auxiliary capacity C_s17 is connected to the auxiliary capacitance line 18
A liquid crystal cell
The variation of the effective voltage in the charge holding state of
V₁″ ＝ [C_gs/ (C _gs+ C_LC+ C_s)] ×
(V_{G (+)}′ -V_{G (-)}′), ΔV₂″ ＝ (C_DP1/ C
_LC+ C_s) × ΔV_D1′-(C_DP2/ C_LC+ C_s) × ΔV
_D2′, ΔV₃″ ＝ [C_gs/ (C_gs+ C_LC+ C_s)] × Δ
V_COMCan be reduced to.

By this effect, V supplied to the counter electrode
By reducing the correction voltage and voltage amplitude of _COM A and V _COM B, the voltage amplitude supplied to the gate bus can be easily reduced. FIG. 15 is a schematic perspective view of an active matrix type thin film transistor liquid crystal panel showing another embodiment of the present invention.

As shown in this figure, a gate bus line 11 and a drain bus line 12 are arranged orthogonal to each other on a transparent rear substrate, and a TFT 13 is provided at the intersection of the gate bus line 11 and the drain bus line 12. Connected to the pixel electrode 14
A group of pixel electrodes connected to one gate bus line 11 through the TFT 13 is arranged in the gate bus line direction, and an alignment film that has been subjected to an alignment treatment in an appropriate direction is provided.

On the other hand, from the pixel electrode groups connected via the TFT 13 to the two adjacent gate bus lines on the transparent front substrate, the pixel electrode groups alternately selected in the gate bus line direction are formed in a staggered manner. One transparent corrugated counter electrode 15 is provided, and a plurality of corrugated counter electrodes 15 are provided.
The non-adjacent corrugated electrodes are connected to each other to provide an alignment film that has been subjected to an alignment treatment in an appropriate direction. Reference numeral 15a is a portion facing the pixel electrode.

The alignment films of the back substrate and the front substrate are faced to each other and aligned, an appropriate gap is provided between both substrates, liquid crystal is injected, and then sealed, and the polarization axes are mutually on the exposed surfaces of both substrates. A polarizing film is attached so as to be parallel or vertical. FIG. 16 is a diagram showing a structure of a counter electrode of an active matrix type thin film transistor liquid crystal panel showing another embodiment of the present invention.

As shown in this figure, the corrugated counter electrodes are pixels selected in a zigzag pattern alternately in the gate bus line direction from a pixel electrode group connected to two adjacent gate bus lines via the TFT 13. Since it is provided as one transparent counter electrode for the electrode group, it is formed across two adjacent gate bus lines as shown in the pattern configuration 1 of FIG. For this reason, in the pattern 1 configuration, when the pixel pitch is made finer, the junction extending over the two lines of the gate bus becomes thin, the electrical resistance value increases, and the potential difference to the extent that display unevenness can be recognized is small. Can occur.

In the pattern structure 2 of FIG. 16 (b), the counter electrode bonding portion 15b is formed of aluminum or the like having a low electric resistance value so as to cope with the miniaturization of the pixel pitch. FIG. 17 is a schematic block diagram of an active matrix type thin film transistor liquid crystal panel showing another embodiment of the present invention, and the data circuit of the active matrix type thin film transistor liquid crystal panel showing another embodiment of the present invention is the same as in FIG. Is.

As shown in FIG. 17, the gate bus line 1
When the number of 1s is N and the number of drain bus lines 12 is M, the scanning circuits 20 are connected to the N gate bus lines 11, and the first gate bus lines 11 are turned on sequentially in time.
The voltage V _{G (+)} ′ is supplied for a time t _on corresponding to one scanning time,
In the M drain bus lines 12, as shown in FIG.
A data circuit 30 including a data generation unit 31, a data inversion unit A32, a data inversion unit B33, a data output unit A34, and a data output unit B35 is connected to supply voltage data including brightness data and polarity data, and FIG. As shown in FIG.
2, a common variation circuit 40 including operational amplifiers 43 and 44, MOSFETs 45 and 46, etc. is connected, and polarity data corresponding to the voltage data supplied to the drain bus line 12 and an offset voltage corresponding to the threshold voltage of the liquid crystal 16 and A voltage signal including an effective voltage correction voltage is supplied.

FIG. 18 is a diagram showing the timing of voltage data supplied to the drain bus of an active matrix type thin film transistor liquid crystal panel showing another embodiment of the present invention. FIG. 18 (a) shows the voltage of the odd drain bus. A data waveform diagram, FIG. 18B is a voltage data waveform diagram of the even drain bus. In this embodiment, in the data generating section 31 of the data circuit 30, the luminance data of one line is divided into data of odd display cells and data of even display cells in the gate bus line direction to obtain data 1. Create data 2.

Further, as the alternating signal for which the polarities are inverted every two times the period of one scanning line such that the writing polarities of the odd drain bus and the even drain bus are different and the polarities of the adjacent counter electrodes are different, An alternating signal 1 corresponding to the odd-numbered drain buses and an alternating signal 2 corresponding to the even-numbered drain buses are created. The data 1 and the alternating signal 1 are calculated by the data inverting unit A32 to create voltage data including brightness data and polarity data, and data 3,
The data output unit A34 outputs the data to the odd-numbered drain buses D ₁ , D _3, ..., D _M-1 . Similarly, the data 2 and the AC signal 2 are calculated by the data inversion unit B33 to create voltage data and data 4 including the brightness data and the polarity data, and the data output unit B35 outputs even-numbered drain buses D ₂ , D. ₄ , ..., Output to D _M.

The voltage data setting conditions for each drain bus output from the data circuit 30 are as follows: ON voltage V _{D (+)} ', OFF voltage V _{D (-)} ' in negative polarity, and negative polarity in positive polarity writing. In writing, since the ON voltage V _{D (-)} 'and the OFF voltage V _{D (+)} ' are set, the voltage amplitude can be set to be equal to ΔV shown in FIG. 14, and V _{D (+)} '-V
_Since it is given under the condition of _{D (-)} '= V _SAT -V _TH = ΔV,
Compared with the conventional example of FIG. 13, the amplitude of the drain voltage is V _TH ×
It can be reduced by 2 + ΔV.

FIG. 19 is a timing chart of a common variation circuit of an active matrix type thin film transistor liquid crystal panel showing another embodiment of the present invention. In this embodiment, instead of setting the amplitude of the drain voltage to be equal to ΔV, a voltage such as an offset voltage of the liquid crystal is supplied by the voltage signal of the counter electrode. Each counter electrode is shown in FIGS.
And, since it is arranged as described in detail in FIG. 17, for the odd-numbered counter electrode groups, at the write timing of the odd-numbered gate bus lines, the offset voltage of the write polarity of the odd-numbered drain bus, etc. At the write timing of the even-numbered gate bus line, V _COM A indicating the offset voltage of the write polarity of the even-numbered drain bus is supplied, and the odd-numbered gate bus line is supplied to the even-numbered counter electrode. An offset voltage of the write polarity of the even drain bus is supplied at the write timing, and a V _COM B indicating the offset voltage of the write polarity of the odd drain bus is supplied at the write timing of the even-numbered gate bus line. It will be.

[0051] The write polarity of the odd drain bus and the even drain bus, at the same write timing, to set the different write polarity, in the same write timing voltage signal V _{CO M} A and V _COM B, writing different It will be set to polarity.
The inverted signal DF that satisfies the above conditions is created and supplied to the normal logic buffer 41 and the inverted logic buffer 42 of the common variation circuit 40, and the operational amplifiers 43 and 44 are respectively provided.
The resistance values R ₁ and R ₂ so that the voltage amplitude becomes appropriate.
Set and amplify R ₂ / R ₁ times,
Those output by T45,46 is V _{CO M} A and V _COM B
Is.

Active matrix thin film transistor
The equivalent circuit of the liquid crystal cell of the liquid crystal panel is the same as in FIG.
In the case of the above-mentioned driving method, the charge holding state of the liquid crystal cell is set.
Fluctuation of the effective voltage under at least three conditions
Occur. First, write the TFT connected to the pixel electrode
Immediately after that, the parasitic capacitance C of the TFT_gsBy ΔV₁′ ＝ [C
_gs/ (C_gs+ C_LC)] × (V_{G (+)}′ -V_{G (-)}')When
Then, write two drain buses that sandwich the pixel electrode.
ΔV from the measured voltage_D1′, ΔV_D2Image when it fluctuates
Capacitance C between element electrode and two drain buses_DP1And C
_DP2By ΔV₂′ ＝ (C_DP1/ C_LC) × ΔV_D1′-
(C_DP2/ C_LC) × ΔV_D2′, And the pixel electrode
The voltage of the counter electrode that accumulates charge during _COMOnly
When changing, parasitic capacitance C of TFT_gsBy ΔV₃′
= [C_gs/ (C _gs+ C_LC)] × ΔV_COMIs.

If the same TFT is formed in all pixel electrodes, the potential variation ΔV ₁ ′ is of the same polarity and the same potential regardless of the write voltage and the write timing, and therefore is supplied to the counter electrode. In setting the voltage to be set, the same effective voltage can be maintained in all the liquid crystal cells by shifting the setting by ΔV ₁ ′.

Further, the potential fluctuations ΔV ₂ ′ and ΔV ₃ ′ have different polarities of effective voltage fluctuation depending on the polarities at the time of writing.
The fluctuation amount shows the largest voltage fluctuation when the polarities of the two drain buses sandwiching the pixel electrode and the counter electrode change during writing. Therefore, in each pixel electrode, if there is a short period and a long period in which the polarities of the two are changed with respect to the polarities at the time of writing, the average effective voltage is different, and display unevenness occurs.

FIG. 20 is a timing chart showing a driving voltage and a pixel voltage change of a TFT connected to an odd drain bus of an active matrix type thin film transistor liquid crystal panel showing another embodiment of the present invention, and FIG. 21 is another embodiment of the present invention. 7 is a timing chart showing changes in driving voltage and pixel voltage of a TFT connected to an even drain bus of an active matrix thin film transistor liquid crystal panel showing an example.

In this embodiment, the voltage signals V _COM A and V _COM B supplied to the counter electrodes are set by shifting the voltage variations ΔV ₁ ′, and the polarities of the drain buses and the counter electrodes are Since alternating drive is performed in which the polarity is inverted at a period twice as long as one scanning line period, the polarities of the two drain buses sandwiching the pixel electrode and the counter electrode change from those at the time of writing, for all the pixel electrodes. That is, the periods are the same and the average effective voltage becomes uniform.

Further, V _COM A and V supplied to the counter electrode
The average voltage fluctuation amount ΔV ₂ ′ of ΔV ₂ ′ in all pixel electrodes calculated by analogy with the display data for the _COM B voltage signal
_{2 COM} (average value) is the effective voltage loss caused by the voltage fluctuation of ΔV ₂ ′, and V _{COM including the} correction data
In order to supply added [Delta] V ₃ calculated from voltage amplitude of the A and V _COM B 'average voltage fluctuation amount [Delta] V _3' (average value) as the effective voltage loss in caused by the voltage fluctuation of ΔV ₃ ', V _COM The voltage waveforms of A and V _COM B are V _{D (+)} ′ − ΔV−V _TH −ΔV ₁ ′ − [Δ
V ₂ ′ (average value)] − [ΔV ₃ ′ (average value)] voltage level, V _{D (−)} ′ + ΔV + V when writing with negative polarity
_TH −ΔV ₁ ′ + [ΔV ₂ ′ (average value)] + [ΔV ₃ ′
(Average value)] ΔV + 2V _TH +2 set to the voltage level
When a voltage signal having a fluctuation amplitude of × [ΔV ₂ ′ (average value)] + 2 × [ΔV ₃ ′ (average value)] is supplied, even when the amplitude of the voltage data output from the data circuit is set to ΔV. , The average effective voltage of all pixels is ΔV +
It can be made as high as V _TH .

The equivalent circuit diagram of the active matrix type thin film transistor liquid crystal panel is similar to that of FIG.
As shown in FIG. 16 and FIG. 16, since a TFT-LCD is provided with a large number of electrical wirings, a wiring capacitance exists as a configuration condition of the liquid crystal panel, and the liquid crystal capacitance C _{LC of} each display cell is present.
A loss current is generated when writing to. The capacitance C _GD created by the intersection of the drain bus and the gate bus causes a loss current proportional to the amount of voltage change of the drain bus to the gate bus and the drain bus every time the voltage of the drain bus changes, and the liquid crystal The capacitance C _DC created between the drain bus and the counter electrode via the layer is the loss current proportional to the voltage variation of the drain bus in the drain bus and the counter electrode every time the voltage of the drain bus also varies. Generate.

C shown in each display cell unit shown here
Without large so much amount of current generated by _GD and C _DC, for considering the whole wire is fairly large current, short duration loss current, in order to release, for example, in line periods outside the panel, the drain bus It is necessary to reduce the resistance of the gate bus and the counter electrode and increase the current capacity of the external driver connected to each wiring.

In the embodiment of the present invention, when the polarities of the adjacent drain buses are different and the polarities are changed, the voltage fluctuations of the adjacent drain buses are always different polarities, for example, one is changed from the positive polarity to the negative polarity. In this case, the other will change from the negative polarity to the positive polarity. Therefore, the loss currents generated by the adjacent capacitors C _GD on one gate bus line or by the adjacent capacitors C _DC on each corrugated counter electrode are currents flowing in opposite directions. Tend to cancel out.

Also in each of the wave type counter electrodes, when the polarity changes, similarly, the adjacent counter electrodes always have voltage fluctuations of different polarities. Therefore, the loss currents generated by the adjacent capacitors C _DC on one drain bus line also tend to cancel each other. For this reason, the loss current flowing through one gate line and drain bus line and each corrugated counter electrode becomes very small, which reduces the resistance of each wiring and increases the capacity of the external driver connected to each wiring. It is possible to provide a liquid crystal panel that does not need to be drawn, and is suitable for large capacity and high definition of the liquid crystal panel.

The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0063]

As described above in detail, according to the present invention, the pixel electrode groups connected to one gate bus line through the thin film transistors are alternately arranged in the gate bus line direction in a zigzag pattern. Then, each counter electrode is provided corresponding to each pixel electrode group arranged in the gate bus line direction, and the pixel electrode group arranged in the gate bus line direction is controlled by two gate buses and one counter electrode. In the gate bus line direction, the counter electrodes corresponding to the pixel electrode groups on the odd-numbered lines are connected to each other, the counter electrodes corresponding to the pixel electrode groups on the even-numbered lines are connected to each other, and a switching circuit is provided for each of the adjacent counter electrodes. The polarity is different and the polarity is inverted in a cycle twice as long as one scanning line cycle, and the polarity data and the voltage data including the offset voltage of the liquid crystal cell and the effective voltage correction voltage are provided. In addition, the voltage data supplied to the drain bus lines have different polarities in the adjacent drain buses, and the polarities are inverted in a period twice as long as one scanning line period, and the positive polarity data and the negative polarity data are inverted to each other. By supplying it as information, it is possible to make the average effective voltage of the liquid crystal cell uniform and lower the withstand voltage of the switching driver of the gate bus line and the drain bus line.

Further, this driving method is also suitable for a large capacity and high definition display because it can reduce the generation of loss current generated by the wiring capacitance in the panel. In addition, this driving method has the same effect even when an analog voltage is input to the drain bus line, and thus can be sufficiently applied to gray scale driving of an active matrix thin film transistor liquid crystal panel.

Further, according to the present invention, the pixel electrode group connected to one gate bus line via the thin film transistor is arranged in the gate bus line direction, and the two adjacent gate bus lines are connected via the TFT. In the pixel electrode group to be connected, 1 for the pixel electrode group selected from two gate bus lines alternately in a zigzag pattern in the gate bus line direction.
The number of wave-shaped opposite electrodes provided is different, and the wave-type opposite electrodes which are not adjacent to each other are connected to each other, and the switching circuits are provided respectively, so that the data supplied to the drain buses have different polarities in the adjacent drain buses, and one scanning line. The polarity of each drain bus is inverted in a period twice the period, and positive polarity and negative polarity voltage data are supplied as mutually inverted voltage information, and the polarity data of the pixel electrode group corresponding to each counter electrode and the liquid crystal are supplied. The average effective voltage of the liquid crystal cell is made uniform and the withstand voltage of the switching driver of the drain bus line is reduced by supplying it to each counter electrode as a voltage signal including the offset voltage and the effective voltage correction voltage corresponding to the threshold voltage of can do.

[Brief description of drawings]

FIG. 1 is a schematic perspective view of an active matrix thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 3 is a schematic block diagram of a data circuit of an active matrix thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 4 is a diagram showing a common variation circuit of an active matrix thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 5 is a diagram showing timing of voltage data supplied to the drain bus of the active matrix type thin film transistor liquid crystal panel showing the embodiment of the present invention.

FIG. 6 is an operation timing chart of a common variation circuit of an active matrix thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 7 is an equivalent circuit diagram of a liquid crystal cell of an active matrix thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 8 is an equivalent circuit diagram of an active matrix thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 9 is a timing chart showing a drive voltage and a pixel voltage change of a TFT connected to an odd drain bus of an active matrix thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 10 is a timing chart showing a drive voltage and a pixel voltage change of a TFT connected to an even drain bus of an active matrix thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 11 is a schematic configuration diagram of an active matrix thin film transistor liquid crystal panel showing a modified embodiment of the present invention.

FIG. 12 is a configuration diagram of a conventional active matrix thin film transistor liquid crystal panel.

FIG. 13 is a diagram showing a drive timing chart of a conventional active matrix thin film transistor liquid crystal panel.

FIG. 14 is a diagram showing electro-optical characteristics of a conventional TN liquid crystal cell.

FIG. 15 is a schematic perspective view of an active matrix thin film transistor liquid crystal panel showing another embodiment of the present invention.

FIG. 16 is a diagram showing a structure of a counter electrode of an active matrix type thin film transistor liquid crystal panel showing another embodiment of the present invention.

FIG. 17 is a schematic block diagram of an active matrix thin film transistor liquid crystal panel showing another embodiment of the present invention.

FIG. 18 is a diagram showing timing of voltage data supplied to a drain bus of an active matrix type thin film transistor liquid crystal panel showing another embodiment of the present invention.

FIG. 19 is a timing chart of a common variation circuit of an active matrix thin film transistor liquid crystal panel showing another embodiment of the present invention.

FIG. 20 is a timing chart showing a drive voltage and a pixel voltage change of a TFT connected to an odd drain bus of an active matrix type thin film transistor liquid crystal panel showing another embodiment of the present invention.

FIG. 21 is a timing chart showing changes in driving voltage and pixel voltage of a TFT connected to an even drain bus of an active matrix thin film transistor liquid crystal panel showing another embodiment of the present invention.

[Explanation of symbols]

 11 gate bus line 12 drain bus line 13 TFT (thin film transistor) 14 pixel electrode 15 counter electrode 15a part facing pixel electrode 15b counter electrode junction 16 liquid crystal 17 auxiliary capacitance 18 auxiliary capacitance line 19 gap 20 scanning circuit 30 data circuit 31 data Generation unit 32 Data inversion unit A 33 Data inversion unit B 34 Data output unit A 35 Data output unit B 40 Common fluctuation circuit 41, 42 Buffer 43, 44 Operational amplifier 45, 46 MOSFET

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Atsushi Takahashi 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Hiro Hiroshi Hamano 1-12-12 Toranomon, Minato-ku, Tokyo Offshore Electric Industry Co., Ltd.

Claims (5)

[Claims] 1. A gate bus line and a drain bus line are provided orthogonally on a rear substrate, and a thin film transistor corresponding to each pixel electrode is provided at an intersection of the gate bus line and the drain bus line. An opposing electrode is provided, and an alignment film that has been oriented in an appropriate direction is provided on the surfaces of the back substrate and the front substrate, and the alignment films of both substrates are placed facing each other via a liquid crystal layer and bonded together, and the back substrate In a method for driving an active matrix thin film transistor liquid crystal panel in which a polarizing film is attached to the back surface of a front substrate and a front substrate, pixel electrode groups connected via a thin film transistor to one gate bus line are alternately staggered in the gate bus line direction. The pixel in the gate bus line direction by the pixel electrode group of one part corresponding to two adjacent gate bus lines. One counter electrode is provided for the pixel electrode group that is arranged in the gate bus line direction to form a pole group, and odd-numbered counter electrodes and even-numbered counter electrodes of the plurality of counter electrodes are connected to each other. Then, a switching element is provided in the odd-numbered counter electrode group and the even-numbered counter electrode group,
The polarities of the voltage data of the adjacent drain bus lines are different, and the polarities of the voltage data are inverted in a cycle twice as long as one scanning line cycle, and the positive and negative voltage data are inverted to each other. The voltage signal is supplied to each drain bus line, and the polarity data of the pixel electrode group corresponding to each counter electrode having different polarities and the offset voltage and the effective voltage correction voltage corresponding to the threshold voltage of the liquid crystal are set. A method of driving an active matrix thin film transistor liquid crystal panel, comprising supplying a voltage signal including the voltage to each counter electrode and writing a voltage to the pixel electrode according to a selection signal of a gate bus line. 2. The active matrix type thin film transistor according to claim 1, wherein impedance components including capacitors C _DP1 and C _DP2 existing between the pixel electrode and an adjacent drain bus line are made equal to operate. Liquid crystal panel driving method. 3. The active matrix type thin film transistor according to claim 1, wherein an auxiliary capacitance C _S is provided electrically in parallel with the liquid crystal capacitance C _LC between the pixel electrode and the counter electrode to operate. Liquid crystal panel driving method. 4. A gate bus line and a drain bus line are provided orthogonally on a rear substrate, and a thin film transistor corresponding to each pixel electrode is provided at an intersection of the gate bus line and the drain bus line. An opposing electrode is provided, and an alignment film that has been oriented in an appropriate direction is provided on the surfaces of the back substrate and the front substrate, and the alignment films of both substrates are placed facing each other via a liquid crystal layer and bonded together, and the back substrate And a driving method of an active matrix type thin film transistor liquid crystal panel in which a polarizing film is attached to the back surface of a front substrate, a pixel electrode group connected to one gate bus line via a thin film transistor is arranged in the gate bus line direction,
In a pixel electrode group connected to two adjacent gate bus lines via a thin film transistor, one pixel electrode group is selected alternately from two gate bus lines in a zigzag pattern in the gate bus line direction. Wave counter electrodes are provided, and non-adjacent wave counter electrodes are connected to each other, and a switching element is provided for each, and the polarity of the voltage data of the adjacent drain bus lines is different. The polarity of the voltage data is reversed,
Further, a voltage signal indicating a voltage in which the voltage data of positive polarity and the voltage data of negative polarity are inverted to each other is supplied to each drain bus line, and the polarity of adjacent counter electrodes is different, and the pixel electrode group of the pixel electrode group corresponding to each counter electrode is supplied. An active matrix in which a voltage signal including polarity data and an offset voltage corresponding to a threshold voltage of liquid crystal and an effective voltage correction voltage is supplied to each counter electrode, and voltage is written to a pixel electrode by a selection signal of a gate bus line. Type thin film transistor liquid crystal panel driving method. 5. The active matrix thin film transistor liquid crystal according to claim 1, wherein impedance components including capacitances C _DP1 and C _DP2 existing between the pixel electrode and an adjacent drain bus are equalized to operate. How to drive the panel.