JP3119942B2 - Driving method of active matrix type thin film transistor liquid crystal panel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving an active matrix type thin film transistor liquid crystal panel.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, the Journal of the Institute of Television Engineers of Japan Vol. 42, No.
1, P. 10 to 16 and P.E. 23-29.

Conventionally, active matrix type liquid crystal panels, especially those using thin film transistors (TFT-L
Although several different methods are used for the drive method of the CD) due to the difference in the AC conversion method, the concept of the voltage supply method is the same. So as a typical example,
A description will be given of a driving method (hereinafter, referred to as a frame mode) for performing an alternating operation for each scanning cycle.

FIG. 12 is a configuration diagram of such a conventional active matrix type thin film transistor liquid crystal panel, and FIG. 13 is a driving timing chart thereof.

As shown in the figure, an active matrix thin film transistor liquid crystal panel generally has a gate bus line 51 and a drain bus line 52 arranged orthogonally on a rear substrate, and a thin film transistor as a switching element corresponding to each pixel electrode at the intersection. (TFT) 53 is provided, a transparent counter electrode 54 is provided on the front substrate, and an alignment film that has been subjected to an alignment treatment in an appropriate direction is provided on the surfaces of both substrates, and the alignment films of both substrates are arranged to face each other via a liquid crystal layer. And a polarizing film is stuck on the back surface of the front substrate and the back substrate such that their polarization axes are parallel or perpendicular to each other.
The liquid crystal 55 in a portion sandwiched between the two electrodes is switched by a potential difference between the voltage of the pixel electrode supplied through the FT 53 and the voltage of the counter electrode 54.

As a TFT switching means, a scanning circuit 60 is connected to the gate bus line 51 and a data circuit 70 is connected to the drain bus line 52.
From the scanning circuit 60 as an ON voltage V
_{G (+),} OFF voltage V _{G (-)} is, as a drain selection and luminance data signals TFT 53, from the data circuit 70 positive write voltage V _{D (+),} negative write voltage V _{D (-)} is Supplied.

As shown in FIG. 13, the voltage V _S of the pixel electrode written by the TFT 53 fluctuates twice in the voltage holding state. First, when the gate selection signal of the TFT 53 changes from the ON state to the OFF state, the voltage V _{S of the} pixel electrode connected to the TFT 53 to which the selection signal is supplied becomes ΔV due to the parasitic capacitance C _gS of the _TFT 53. _It fluctuates by one.

Second, when the data signal changes to the polarity opposite to the polarity at the time of writing, it changes by ΔV ₂ due to the electric field effect between the pixel electrode and the drain bus line 52.
Therefore, with respect to fluctuation potential difference of the voltage V _S of the pixel electrode between the pixel electrode and the counter electrode, so that the uniformly between the time of the positive polarity writing during the negative polarity writing, to the counter electrode To supply the voltage _VCOM .

FIG. 14 shows the electro-optical characteristics of a TN liquid crystal cell in a case where two polarizing films are bonded so that their polarization axes are parallel.

In a TN liquid crystal cell used in an active matrix type thin film transistor liquid crystal panel, there is no change in the threshold voltage V _{TH at} which the light transmittance sharply increases and the light transmittance with respect to the potential difference between the pixel electrode and the counter electrode. Saturation voltage V
_SAT exists, and in a voltage range ΔV from V _{TH to} V _SAT , a voltage fluctuation indicates a change in light transmittance. Therefore, to achieve a complete ON state, V _SAT <
V _S −V _COM , and V _SAT <V _COM −V _{S for} negative polarity
Set voltage conditions, to achieve complete OFF state, V _TH> V _S -V _COM in positive polarity, by setting the voltage condition of V _TH> V _COM -V _S is in the negative polarity And a liquid crystal cell can be switched.

[0011]

However, in the above-described driving method, when the time from when the data signal is written to the pixel electrode to when the voltage polarity of the drain bus line is inverted is different, for example, the scanning circuit is used. When the voltage V _{S of the} pixel electrode connected to the selected first gate bus line and the N-th gate bus line via the TFT is compared, the electric field effect between the pixel electrode and the drain bus line indicates that Since the period during which the voltage fluctuates by ΔV ₂ is different, the average effective voltage applied to the liquid crystal layer in each scanning cycle is different, resulting in a difference in light transmittance.

Although it is sufficient for the switching of the liquid crystal layer to generate a voltage change of ΔV between the pixel electrode and the counter electrode, the voltage of the counter electrode is fixed and the voltage of the pixel electrode is changed to the positive polarity. And a switching voltage of V _SAT × 2 (equivalent to (V _TH + ΔV) × 2) is required for the driver of the drain bus line, and ΔV + V _TH ×
An extra switching voltage is required for the voltage of 2,
This was an obstacle to lowering the withstand voltage of the driver.

An object of the present invention is to provide the above-described variation in the average effective voltage of the liquid crystal layer in each scanning cycle and the extra switching voltage V _TH × 2 + Δ applied to the drain bus line.
In order to reduce or eliminate V, pixel electrode groups connected to one gate bus line via TFTs are alternately arranged in a staggered manner in the gate bus line direction, and two pixel electrode groups arranged in the gate bus line direction are arranged in a staggered manner. In the configuration controlled by the gate bus line, each counter electrode is provided corresponding to each pixel electrode group arranged in the gate bus line direction, and adjacent drain buses and adjacent counter electrodes have different polarities, The alternating method in which the respective polarities are inverted every twice the scanning line period eliminates variations in the average effective voltage, and the positive and negative data supplied to each drain bus line are inverted. The data configuration is provided as voltage information, and each counter electrode has the same voltage amplitude, and the write voltage is supplemented by the voltage amplitude. It is to provide an excellent method of driving an active matrix type thin film transistor liquid crystal panel to achieve the lowering of the withstand voltage of the switching driver Surain and the gate bus line.

Another object of the present invention is to dispose a group of pixel electrodes connected to one gate bus line via a TFT in a line direction, and to connect two adjacent gate bus lines to each other via a TFT. In the pixel electrode group to be connected, one corrugated counter electrode is provided for a pixel electrode group selected from two gate bus lines alternately in a staggered manner in the gate bus line direction, and an adjacent drain The bus lines and the adjacent counter electrodes have different polarities.
The alternating method in which the respective polarities are inverted every two times the scanning line period eliminates the variation in the average effective voltage, and the positive and negative data supplied to each drain bus line are inverted with each other. active that the data structure is supplied as a voltage information, the respective counter electrode has the same voltage amplitude, compensate the write voltage by the voltage amplitude, with excellent achieving low resistance conductive pressurization switching driver drain bus line An object of the present invention is to provide a method of driving a matrix type thin film transistor liquid crystal panel.

[0015]

In order to achieve the above object, the present invention provides a gate bus line and a drain bus line which are orthogonally arranged on a rear substrate, and at an intersection of the gate bus line and the drain bus line. A thin-film transistor corresponding to each pixel electrode is provided, a transparent counter electrode is provided on the front substrate, an alignment film that has been subjected to an alignment treatment in an appropriate direction is provided on the surfaces of the back substrate and the front substrate, and the alignment films of both substrates are separated from each other. In a method of driving an active matrix type thin film transistor liquid crystal panel in which a liquid crystal layer is opposed to each other and bonded to each other, and a polarizing film is bonded to the back surface of the rear substrate and the front substrate, a single gate bus line is provided with a thin film transistor through a thin film transistor. the pixel electrode group connected to staggered alternately to the gate bus line direction, Getobasura the one
Odd-numbered pixel electrode groups connected to
Even number connected to the gate bus line adjacent to the line
Th in a row to the gate bus line direction by the pixel electrode group
A pixel electrode group to be arranged is formed, and the gate bus line direction
Opposite to the pixel electrode group arranged in a row in the provided one counter electrode, the odd-numbered of the plurality provided counter electrode of the counter electrode and between the even-numbered counter electrode between the respectively connected, odd A circuit is provided for switching the first counter electrode group and the even-numbered counter electrode group , respectively. The polarity of the voltage data of the adjacent drain bus lines is different, and the polarity of the voltage data is inverted twice as long as one scanning line period. And a voltage signal indicating a voltage obtained by inverting the voltage data of the positive polarity and the negative polarity to each other is supplied to each drain bus line, and the polarity of the adjacent counter electrode is different, and the pixel electrode group corresponding to each counter electrode is provided. And a voltage signal including an offset voltage and an effective voltage correction voltage corresponding to the threshold voltage of the liquid crystal and the threshold voltage of the liquid crystal. It is obtained to perform the voltage writing.

[0016] 2 is arranged a single pixel electrode group connected through the thin film transistor to the gate bus lines in a line in the gate bus line direction, it is connected via a thin film transistor adjacent two gate bus lines One of the two gate bus lines in the pixel electrode group of the column.
Odd-numbered pixel electrodes connected to one gate bus line
Group and the even-numbered picture connected to the other gate bus line
To face the pixel electrode group to be provided with a single corrugated counter electrode, and is connected non-adjacent corrugated counter electrode to each other, respectively a circuit for switching provided, the polarity of the voltage data of the adjacent drain bus lines In contrast, a voltage signal indicating a voltage in which the polarity of the voltage data is inverted and the voltage data of the positive polarity and the polarity data of the negative polarity are inverted to each other twice in one scan line cycle is supplied to each drain bus line. A voltage signal including an offset voltage and an effective voltage correction voltage corresponding to the polarity data of the pixel electrode group corresponding to each of the opposed electrodes and the threshold voltage of the liquid crystal, and the polarity of the adjacent opposed electrodes being different, is supplied to each of the opposed electrodes. The voltage writing is performed on the pixel electrode by the selection signal of the gate bus line.

[0017]

According to the present invention, as described above, a group of pixel electrodes connected to one gate bus line via a TFT are alternately arranged in a staggered manner in the gate bus line direction. A configuration in which the pixel electrode groups arranged in a row is controlled by two gate bus lines, and each counter electrode is provided in correspondence with each pixel electrode group arranged in the gate bus line direction,
The variation of the average effective voltage applied to the liquid crystal layer can be reduced by an alternating method in which adjacent drain buses and adjacent counter electrodes have different polarities, and each polarity is inverted every twice the scanning line period. In addition, the data of the positive polarity and the data of the negative polarity supplied to each drain bus line are supplied as inverted voltage information, and have the same voltage amplitude to each counter electrode.
By supplementing the write voltage, an extra switching voltage applied to the drain bus line can be eliminated.

Alternatively, TF is connected to one gate bus line.
A pixel electrode group connected via T is arranged in the line direction, and pixels are alternately selected in a staggered manner in the gate bus line direction from the pixel electrode group connected via TFT to two adjacent gate bus lines. A configuration in which one corrugated counter electrode is provided for the electrode group, adjacent drain bus lines and adjacent counter electrodes have different polarities, and each of the drain bus lines has a different polarity every two scanning cycle periods By the alternating method in which the polarity is inverted, the dispersion of the average effective voltage applied to the liquid crystal layer is eliminated, and the positive and negative data supplied to each drain bus line are supplied as mutually inverted voltage information, and Each counter electrode has the same voltage amplitude, and by supplementing the write voltage with the voltage amplitude, it is possible to eliminate an extra switching voltage applied to the train bus. .

Therefore, the average effective voltage of the liquid crystal cell can be made uniform, and the withstand voltage of the switching driver for the drain bus line and the gate bus line can be reduced.

Furthermore, this driving method has the same effect even when an analog voltage is input to the drain bus line, and therefore can be sufficiently applied to gradation driving of an active matrix thin film transistor liquid crystal panel.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic perspective view of an active matrix type thin film transistor liquid crystal panel according to an embodiment of the present invention.

As shown in FIG. 1, a gate bus line 11 and a drain bus line 12 are arranged orthogonally on a transparent rear substrate, and a TFT 13 is provided at the intersection between the gate bus line 11 and the drain bus line 12. Connected to the pixel electrode 14. Then, a group of pixel electrodes 14 connected to one gate bus line 11 via the TFT 13 are alternately arranged in a staggered manner in the gate bus line direction, and two adjacent gate bus lines 11 form a line in the gate bus line direction. The pixel electrodes 14 arranged in a line are switched. Further, an alignment film that has been subjected to an alignment treatment in an appropriate direction is provided on the back substrate.

On the other hand, the counter electrode 15 to each other and even to the appropriate been transparent counter electrode 15 divided on the same number as the number of lines the pixel electrode 14 group in a line on a transparent front substrate is provided, and the odd drain bus line 12 Drain bus line 12
To connect to each other counter electrodes 15 corresponding, it provided the appropriate direction alignment-treated alignment film.

The alignment films of the rear substrate and the front substrate face each other, are aligned so that a group of pixel electrodes 14 arranged in a line and one counter electrode 15 are opposed to each other. After providing a gap, injecting liquid crystal, sealing,
A polarizing film is attached to the exposed surfaces of both substrates so that the polarizing axes are parallel or perpendicular to each other. Note that 15a
Is a portion facing the pixel electrode.

FIG. 2 is a schematic configuration diagram of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention.
FIG. 3 is a schematic block diagram of a data circuit of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention, and FIG. 4 is a diagram showing a common variation circuit of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention. Note that the common variation circuit 40
This is a circuit for switching the counter electrode 15.

As shown in these figures, the number of gate bus lines 11 is N + 1, and the number of drain bus lines 12 is M
When the scanning circuit 20 is connected to the (N + 1) gate bus lines 11, temporally sequentially supplies t _on time corresponding ON voltage V _G of ₍₊₎ 'in one scanning period from the first gate bus line 11 , And a data circuit 30 including a data generation unit 31, a data inversion unit A32, a data inversion unit B33, a data output unit A34, and a data output unit B35 are connected to the M drain bus lines 12, and luminance data and polarity data are transmitted. Voltage data including the buffer 41, 42, the operational amplifiers 43, 44, and the
A common variation circuit 40 including SFETs 45 and 46 is connected, and a voltage including polarity data corresponding to the voltage data supplied to the drain bus line 12, an offset voltage corresponding to a threshold voltage of the liquid crystal 16, and an effective voltage correction voltage. Supply signal.

FIG. 5 shows the timing of the voltage data supplied to the drain bus of the active matrix type thin film transistor liquid crystal panel according to the embodiment of the present invention.

In this embodiment, a single gate bus line 11 switches pixel electrodes arranged in a zigzag pattern alternately in the gate bus line direction.
In the gate bus line and the (N + 1) th gate bus line, only the TFTs connected to the even-numbered pixel electrodes and the TFTs connected to the odd-numbered pixel electrodes in the gate bus line direction are switched. Therefore, when image data of one frame is written, the odd-numbered pixel electrode groups in the gate bus line direction are written at the write timing from the second gate bus line to the (N + 1) th gate bus line and in the gate bus line direction. For even-numbered pixel electrode groups, voltage data must be supplied from the drain bus lines at the write timing from the first gate bus line to the Nth gate bus line.

Therefore, the data generator 3 of the data circuit 30
In 1, the luminance data of one line is divided into data of odd-numbered display cells in the gate bus line direction and data of even-numbered display cells, and the data of odd-numbered display cells in the gate bus line direction is Dummy data d _D as data corresponding to the first gate bus line, and data d ₁ of the first line as data corresponding to the second gate bus
Is generated as data 1 that sequentially supplies data d ₂ of the second line as data corresponding to the third gate bus,..., Data d _N of the N th line as data corresponding to the (N + 1) th gate bus.

As the data of the even-numbered display cells in the gate bus line direction, data d ₁ of the first line as data corresponding to the first gate bus and data of the second line as data corresponding to the second gate bus are used. Data d ₂ of
... N-th gate bus data d _N of the N-th line as corresponding data, to create a dummy data d _D data supplied sequentially 2 as data corresponding to the first N + 1 gate buses.

In the data generating section 31, the write polarity of the odd-numbered drain bus is different from the write polarity of the even-numbered drain bus, and the polarity of adjacent counter electrodes is different every two scanning line periods. As an alternating signal whose polarity is inverted, an alternating signal 1 corresponding to an odd-numbered drain bus and an alternating signal 2 corresponding to an even-numbered drain bus are created.

Further, the data 1 and the AC signal 1 are operated by a data inverting section A32 to generate voltage data including luminance data and polarity data, data 3, and a data output section A34.
, D, the odd-numbered drain buses D ₁ , D ₃ .
Output to _M-1 . Similarly, the data 2 and the alternating signal 2 are operated by the data inverting section B33 to generate voltage data and data 4 including luminance data and polarity data, and the data output section B35 to generate even-numbered drain buses D ₂ and D ₂ .
₄ ..., and outputs it to the D _M.

The voltage data setting condition of each drain bus output from the data circuit 30 is such that, in the writing of the positive polarity, the ON voltage V _{D (+)} ′, the OFF voltage V _{D (−)} ′, and the negative voltage. In the write operation, the ON voltage VD _(-) 'and the OFF voltage VD ₍₊₎ ', the voltage amplitude can be set to be equal to ΔV shown in FIG. 14, and VD ₍₊₎ '-V
_{D (-)} '= V _SAT -V _TH = ΔV
The amplitude of the drain voltage is V _TH ×
It can be reduced by 2 + ΔV.

FIG. 6 is a timing chart of a common variation circuit of an active matrix type thin film transistor liquid crystal panel according to an embodiment of the present invention.

In this embodiment, instead of setting the amplitude of the drain voltage to be equal to ΔV, a voltage such as an offset voltage of the liquid crystal is supplied by a voltage signal of the counter electrode. Therefore, at the write timing of the first gate bus line, an offset voltage or the like of the write polarity of the even drain bus is applied to the counter electrode corresponding to the odd line, and at the write timing of the second gate bus line, the offset voltage of the odd drain bus is applied. A voltage signal for supplementing an offset voltage or the like of a write polarity is supplied. That is, at the write timing of the odd-numbered gate bus line, a voltage signal that supplements the offset voltage of the write polarity of the even-numbered drain bus is supplied, and at the write timing of the even-numbered gate bus line, the offset of the write polarity of the odd-numbered drain bus is used. A voltage signal V _COM A for supplementing a voltage or the like is supplied. On the other hand, at the write timing of the odd-numbered gate bus line, a voltage signal that supplements the offset voltage of the write polarity of the odd-numbered drain bus is applied to the counter electrode corresponding to the even-numbered line, and the write timing of the even-numbered gate bus line is changed. in will supply a voltage signal V _COM B to replenish the offset voltage of the write polarity of the even drain bus. In addition, since the write polarities of the odd drain bus and the even drain bus are set to different write polarities at the same write timing, the voltage signals V _COM A and V _COM B are also set to different write polarities at the same write timing. Will be.

An inverted signal DF which satisfies the above conditions is created and supplied to the non-inverted logic buffer 41 and the inverted logic buffer 42 of the common variation circuit, respectively.
Resistance so that a suitable voltage amplitude by 3,44 R _1, sets the R _2, R ₂ / R was amplified to _1x, the V _COM A that is output from 45 and 46 to the MOSFET, respectively
And V _COM B.

FIG. 7 is an equivalent circuit diagram of a liquid crystal cell of an active matrix thin film transistor liquid crystal panel according to an embodiment of the present invention.

In the case of the above-described driving method, the fluctuation of the pixel voltage in the state where the charge of the liquid crystal cell is held occurs under at least three conditions.

Firstly, immediately after writing of the TFT connected to the pixel electrode, the parasitic capacitance C _gs of the TFT, [Delta] V ₁ '=
[C _gs / (C _gs + C _LC + C _DP1 + C _DP2 )] × (V
_{G (+)} ′ ₋ V _{G (−)} ′), and then 2
Of the drain bus lines 12 are equal to Δ
Due to the capacitances C _DP1 and C _DP2 between the pixel electrode and the two drain bus lines 12 when the voltage changes by V _D1 ′ and ΔV _D2 ′, ΔV ₂ ′ = (C _DP1 / C _gs + C _LC + C _DP1 +
C _DP2 ) × ΔV _D1 '-(C _DP2 / C _gs + C _LC + C _DP1 +
C _DP2) × ΔV _D2 'becomes, when the further voltage of the common electrode 15 for charge storage between the pixel electrode is varied only [Delta] V _COM, a liquid crystal capacitance C _LC, ΔV _3' = [C _LC /
(C _gs + C _LC + C _DP1 + C _DP2 )] × ΔV _COM .

The potential variation [Delta] V ₁ 'is long as it is equal TFT in all the pixel electrodes are formed, regardless of the write voltage and write timing, since the same polarity, a variation of the same potential, supplied to the counter electrode 15 In setting the voltage, the voltage is set to be shifted by ΔV ₁ ′, so that the voltage between the pixel electrode and the counter electrode 15 (hereinafter referred to as the effective voltage) can be maintained in the same state in all the liquid crystal cells. .

The potential fluctuations ΔV ₂ ′ and ΔV ₃ ′ differ in the polarity of the effective voltage fluctuation depending on the polarity at the time of writing, and the amount of the fluctuation depends on the two drain bus lines 12 sandwiching the pixel electrode.
And the largest voltage fluctuation when the polarity of the counter electrode 15 changes from that at the time of writing. Therefore, in each pixel electrode, if there is a short period and a long period during which both polarities are changed with respect to the polarity at the time of writing, the average effective voltage differs, and display unevenness occurs.

FIG. 9 is a timing chart showing the drive voltage and the pixel voltage change of the TFT connected to the odd drain bus of the active matrix type thin film transistor liquid crystal panel according to the embodiment of the present invention, and FIG. 10 shows the embodiment of the present invention. 5 is a timing chart showing a drive voltage and a pixel voltage change of a TFT connected to an even drain bus of an active matrix type thin film transistor liquid crystal panel.

In this embodiment, the voltage signals V _COM A and V _COM B supplied to the common electrode are shifted by the voltage variation ΔV ₁ ′ to set the voltage, and the polarity of each drain bus line and each common electrode is changed. Since the AC driving is performed in which the polarity is inverted twice as long as one scanning line period,
V _S2A , V _S3A ,... V _{S (N + 1) A} , V _S1B , V _S2B,.
Waveform obtained pixel electrode represented by V _SNB, to all the pixel electrodes, two drain bus line sandwiching the pixel electrode
The period during which the polarity of the negative electrode and the counter electrode changes during writing becomes equal, and the average effective voltage becomes uniform.

Further, V _COM A and V _COM supplied to the opposite electrode
Average voltage fluctuation ΔV ₂ ′ of all pixel electrodes calculated by analogy to the voltage signal of _COM B from display data
V ₂ ′ (average value) is defined as an effective voltage loss caused by a voltage change of ΔV ₂ ′, and V ₂ ′
In order to supply added _COM A and V _COM [Delta] V ₃ 'average voltage variation [Delta] V ₃ of' calculated from the voltage amplitude of B (average value) as the effective voltage loss in caused by the voltage variation of [Delta] V ₃ ', V The voltage waveforms of _COM A and V _COM B are set to V _{D (+)} ′ − ΔV−V _TH −ΔV ₁ ′ −
The voltage level of [ΔV ₂ ′ (average value)] − [ΔV ₃ ′ (average value)] is V _{D (−)} ′ + ΔV at the time of writing of negative polarity.
+ V _TH −ΔV ₁ ′ + [ΔV ₂ ′ (average value)] + [Δ
ΔV + 2V set to the voltage level of “V ₃ ′ (average value)]
_When supplied as a voltage signal having a fluctuation amplitude of _TH + 2 × [ΔV ₂ ′ (average value)] + 2 × [ΔV ₃ ′ (average value)], when the amplitude of the voltage data output from the data circuit is set to ΔV , The average effective voltage of all the pixels is ΔV
+ V _TH can be made approximately the same.

FIG. 8 is an equivalent circuit diagram of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention.

In FIG . 8, as shown in FIGS. 1 and 2, since a large number of electric wirings are provided in the active matrix type thin film transistor liquid crystal panel, a wiring capacitance exists as a constituent condition of the liquid crystal panel. When writing is performed on the liquid crystal capacitance _CLC of each display cell, a loss current is generated. Drain bus line 12 and gate bus line 1
The capacitance _CGD created by the intersection of the gate bus line and the gate bus line each time the voltage of the drain bus line 12 fluctuates.
11 and the drain bus line 12 to the drain bus line 1
To generate a loss current proportional to the voltage variation amount of 2, also the capacity C _DC that is created between the drain bus line 12 and the counter electrode 15 through the liquid crystal layer, similarly drain bus line
The drain bus line 12 and the counter electrode 15 each time the voltage of the emission 12 varies, generating a loss current proportional to the voltage variation of the drain bus line 12.

Here, the amount of current generated by C _GD and C _DC existing in each display cell unit is not so large, but it is a very large current in the entire wiring. For example, in order to discharge the voltage to the outside of the panel in the line cycle, it is necessary to reduce the resistance of the drain bus line 12, the gate bus line 11, and the counter electrode 15 and to increase the current capacity of the external driver connected to each wiring. No.

In this embodiment, when the adjacent drain bus lines 12 have different polarities, and the polarity fluctuates,
The adjacent drain bus lines 12 always change in voltage with different polarities, for example, when one of the drain bus lines 12 changes from positive to negative, the other changes from negative to positive.

Therefore, the loss currents generated by the adjacent capacitors C _GD or by the adjacent capacitors C _DC on one counter electrode 15 divided for each line are currents flowing in opposite directions. And the loss currents tend to cancel each other.

Also, when the polarity of adjacent opposing electrodes 15 divided for each line fluctuates, the adjacent opposing electrodes 15 also necessarily have voltage fluctuations of different polarities. Therefore, one drain bus line 1
The loss currents generated by the adjacent capacitors C _DC on the line 2 also tend to cancel each other.

For this reason, one gate bus line 11
The loss current flowing through the line 11, the drain bus line 12, and the opposing electrode 15 divided for each line becomes extremely small, and it is not possible to reduce the resistance of each wiring and increase the capacity of an external driver connected to each wiring. It can provide a liquid crystal panel that can be used, and is suitable for increasing the capacity and definition of the liquid crystal panel.

FIG. 11 is a schematic structural view of an active matrix type thin film transistor liquid crystal panel showing a modified embodiment of the present invention.

In this embodiment, the liquid crystal capacitance _CLC between each pixel electrode and the counter electrode 15 of the active matrix type thin film transistor liquid crystal panel having the structure described in detail with reference to FIGS. The auxiliary capacity C _s 17
And the auxiliary capacitance C _s 17 is connected to the common variation circuit 40 via the auxiliary capacitance line 18. The amount of fluctuation of the pixel voltage in the state of holding the charge of the liquid crystal cell is ΔV ₁ ″ = [C _gs / (C _gs + C _LC + C _s + C _DP1 + C
_{DP2)] × (V G (+) '} -V G (-)'), ΔV 2 "=
(C _DP1 / C _gs + C _LC + C _s + C _DP1 + C _DP2 ) × ΔV
_{D1 '- (C DP2 / C} gs + C LC + C s + C DP1 + C DP2)
× ΔV _D2 ′, ΔV ₃ ″ = [(C _LC + C _s ) / (C _gs + C
_{LC + C s + C DP1 +} C DP2) ] in which it is reduced to × [Delta] V _COM. The common fluctuation circuit 40 is
This is a circuit for switching the counter electrode 15.

According to this effect, the voltage amplitude supplied to the gate bus line 11 can be easily reduced by reducing the correction voltages and voltage amplitudes of V _COM A and V _COM B supplied to the counter electrode 15 .

FIG. 15 is a schematic perspective view of an active matrix type thin film transistor liquid crystal panel according to another embodiment of the present invention.

As shown in this figure, a gate bus line 11 and a drain bus line 12 are arranged orthogonally on a transparent rear substrate, and a TFT 13 is provided at the intersection between the gate bus line 11 and the drain bus line 12, so that transparent TFTs corresponding to individual display cells are provided. Connected to the pixel electrode 14,
A group of pixel electrodes 14 connected to one gate bus line 11 via a TFT 13 is arranged in the gate bus line direction, and an alignment film that has been subjected to an alignment process in an appropriate direction is provided.

Meanwhile, transparent on the front substrate to the two gate bus lines 11 adjacent the pixel electrodes 14 group connected through the TFT 13, pixel electrode 14 group selected alternately to the gate bus line direction in a staggered manner On the other hand, one transparent corrugated counter electrode 15 was provided, and a plurality of corrugated counter electrodes 15 were provided, and non-adjacent corrugated counter electrodes 15 were connected to each other, and orientation treatment was performed in an appropriate direction. An alignment film is provided. In addition, 15a is a portion facing the pixel electrode 14 .

The alignment films of the back substrate and the front substrate are faced to each other, aligned, an appropriate gap is provided between the two substrates, liquid crystal is injected, and the liquid crystal is sealed. A polarizing film is attached so as to be parallel or vertical.

FIG. 16 is a view showing a structure of a counter electrode of an active matrix type thin film transistor liquid crystal panel according to another embodiment of the present invention.

As shown in FIG.Fifteen
Indicates two adjacent gate bus lines11TFT13
Pixel electrode connected via14Flock from the gate Basra
Pixel electrodes alternately selected in a zigzag pattern in the in direction14Vs group
And one transparent counter electrodeFifteenTo provide as
As shown in the pattern configuration 1 of FIG.
Book gate bus line11Is formed. This
Therefore, in the pattern 1 configuration, the pixel pitch is fine.
Gate busLine 11Two lines
And the electrical resistance increases,
There is a possibility that there will be a potential difference enough to recognize display unevenness.
is there.

In the pattern configuration 2 shown in FIG. 16B, the counter electrode junction 15b is made of aluminum or the like having a low electric resistance so as to be able to cope with a fine pixel pitch.

FIG. 17 is a schematic block diagram of an active matrix thin film transistor liquid crystal panel according to another embodiment of the present invention. The data circuit of the active matrix thin film transistor liquid crystal panel according to another embodiment of the present invention is the same as that of FIG. Same as 3.

As shown in FIG. 17, gate bus line 1
Assuming that the number of 1s is N and the number of drain bus lines 12 is M, the scanning circuit 20 is connected to the N gate bus lines 11 and sequentially turned on sequentially from the first gate bus lines 11.
Supplying t _on time corresponding to the voltage V _{G (+)} 'to one scan time,
As shown in FIG. 3, the M drain bus lines 12
A data circuit 30 composed of a data generating unit 31, a data inverting unit A32, a data inverting unit B33, a data output unit A34, and a data output unit B35 is connected to supply voltage data including luminance data and polarity data. as shown in, buffer 4 to the counter electrode 15 group is divided into two systems
1, 42, operational amplifiers 43, 44, MOSFET 45,
46 and a common fluctuation circuit 40 composed of
A voltage signal including polarity data corresponding to the voltage data supplied to the drain bus line 12, an offset voltage corresponding to the threshold voltage of the liquid crystal 16, and an effective voltage correction voltage is supplied.

FIG. 18 is a diagram showing the timing of voltage data supplied to the drain bus of an active matrix type thin film transistor liquid crystal panel according to another embodiment of the present invention. FIG. 18 (a) shows the voltage of the odd drain bus. FIG. 18B is a data waveform diagram of the even-numbered drain bus.

In this embodiment, in the data generating section 31 of the data circuit 30 shown in FIG. 3, the luminance data of one line is converted into the data of the odd-numbered display cells in the direction of the gate bus line 11 , and Data 1 and data 2 are created by dividing the data into even-numbered display cells.

Further, as an alternating signal, the polarity is inverted every twice the scanning line period in which the odd and even drain buses have different write polarities and adjacent counter electrodes have different polarities. An alternating signal 1 corresponding to the odd-numbered drain bus and an alternating signal 2 corresponding to the even-numbered drain bus are created.

The data 1 and the alternating signal 1 are supplied to the data inverting section A
32, voltage data including luminance data and polarity data, data 3 are generated, and output to the odd-numbered drain buses D ₁ , D _3, ..., D _M-1 by the data output unit A34. Similarly, the data 2 and the alternating signal 2 are operated by the data inverting section B33 to generate voltage data and data 4 including luminance data and polarity data, and the data output section B35 to generate even-numbered drain buses D ₂ and D ₂ . ₄ ,…, D _M
Output to

The conditions for setting the voltage data of each drain bus output from the data circuit 30 are as follows: in the writing of the positive polarity, the ON voltage V _{D (+)} ′, the OFF voltage V _{D (−)} ′, and the negative voltage. In the write operation, the ON voltage VD _(-) 'and the OFF voltage VD ₍₊₎ ', the voltage amplitude can be set to be equal to ΔV shown in FIG. 14, and VD ₍₊₎ '-V
_{D (-)} '= V _SAT -V _TH = ΔV
The amplitude of the drain voltage is V _TH ×
It can be reduced by 2 + ΔV.

FIG. 19 is a timing chart of a common variation circuit of an active matrix thin film transistor liquid crystal panel according to another embodiment of the present invention.

In this embodiment, instead of setting the amplitude of the drain voltage to be equal to ΔV, a voltage such as an offset voltage of the liquid crystal is supplied by a voltage signal of the counter electrode. Since each counter electrode is arranged as described in detail with reference to FIGS. 15, 16 and 17, with respect to the odd-numbered counter electrodes 15 group, at the write timing of the odd-numbered gate bus line 11 , the offset voltage of the write polarity of the odd drain bus line 12 or the like, in the write timing of the even-numbered gate bus line 11, and supplies the V _COM a indicating the offset voltage of the write polarity of the even drain bus line 12 or the like, also, For the even-numbered counter electrode 15 , at the write timing of the odd-numbered gate bus line 11 , the offset voltage of the write polarity of the even-numbered drain bus line 12 and the like, and at the write timing of the even-numbered gate bus line 11 , , the offset voltage of the write polarity of the odd drain bus line 12 or the like Ing to be supplied to V _COM B.

Since the write polarity of the odd drain bus line 12 and the write drain of the even drain bus line 12 are set to different write polarities at the same write timing, the voltage signals V _COM A and V _COM B are also set at the same write timing. The write polarities are set to be different from each other.

An inverted signal DF satisfying the above conditions is created and supplied to the non-inverted logic buffer 41 and the inverted logic buffer 42 of the common variation circuit 40 shown in FIG. The resistance values R ₁ and R ₂ are set so as to have amplitudes, amplified by R ₂ / R ₁ times, and output by the MOSFETs 45 and 46, respectively, are V _COM A and V _COM B.

The equivalent circuit of the liquid crystal cell of the active matrix type thin film transistor liquid crystal panel is the same as that of FIG.
In the case of the above-described driving method, the fluctuation of the pixel voltage in the charge holding state of the liquid crystal cell occurs under at least three conditions.

First, immediately after the writing of the TFT connected to the pixel electrode, ΔV ₁ ′ = ΔV ₁ ′ due to the parasitic capacitance C _gs of the TFT.
[C _gs / (C _gs + C _LC + C _DP1 + C _DP2 )] × (V
_{G (+)} ′ ₋ V _{G (−)} ′), and then 2
Are _drained from the voltage at the time of writing by ΔV _D1 ′, ΔV
Due to the capacitances C _DP1 and C _DP2 between the pixel electrode and the two drain buses when the voltage changes by V _D2 ′, ΔV ₂ ′ = (C
_DP1 / C _gs + C _LC + C _DP1 + C _DP2 ) × ΔV _D1 '-(C
_{DP2 / C gs + C LC +} C DP1 + C DP2) × ΔV D2 ' , and the further, when the voltage of the common electrode to perform charge accumulation between the pixel electrode is varied only [Delta] V _COM, a liquid crystal capacitance C _LC, [Delta] V ₃ '= [C _LC / (C _gs + C _LC + C _DP1 + C
_DP2 )] × ΔV _COM .

If the same TFT is formed in all pixel electrodes, the potential fluctuation ΔV ₁ ′ has the same polarity and the same potential regardless of the writing voltage and the writing timing. By setting the voltage to be shifted by ΔV ₁ ′, the effective voltage can be maintained in the same state in all the liquid crystal cells.

Further, the potential fluctuations ΔV ₂ ′ and ΔV ₃ ′ have different polarities of the pixel voltage fluctuation depending on the polarity at the time of writing.
The amount of the fluctuation shows the largest voltage fluctuation when the polarities of the two drain bus lines sandwiching the pixel electrode and the counter electrode change between the time of writing and the time of writing.

Therefore, if each pixel electrode has a short period and a long period during which both polarities are changed with respect to the polarity at the time of writing, the average effective voltage is different.
Display unevenness occurs.

FIG. 20 is a timing chart showing a drive voltage and a pixel voltage change of a TFT connected to an odd drain bus of an active matrix type thin film transistor liquid crystal panel showing another embodiment of the present invention, and FIG. 21 is another embodiment of the present invention. 6 is a timing chart showing a drive voltage and a pixel voltage change of a TFT connected to an even drain bus of an active matrix thin film transistor liquid crystal panel according to an embodiment.

In this embodiment, the voltage signals V _COM A and V _COM B supplied to the common electrodes are shifted by the voltage variation ΔV ₁ ′ to set the voltage, and the polarity of each drain bus line and each common electrode is set. Since the AC driving is performed in which the polarity is inverted twice as long as one scanning line period,
For all the pixel electrodes, the periods during which the polarities of the two drain bus lines and the counter electrode sandwiching the pixel electrode are changed during writing are the same, and the average effective voltage becomes uniform.

Further, V _COM A and V _COM supplied to the opposite electrode
The average voltage variation ΔV of ΔV ₂ ′ for all pixel electrodes calculated by analogy with the display signal to the voltage signal of _COM B
₂ ′ (average value) is defined as an effective voltage loss caused by a voltage change of ΔV ₂ ′, and V _{COM in} a state including correction data.
In order to supply added [Delta] V ₃ calculated from voltage amplitude of the A and V _COM B 'average voltage fluctuation amount [Delta] V _3' (average value) as the effective voltage loss in caused by the voltage fluctuation of ΔV ₃ ', V _COM When writing the voltage waveforms of A and V _COM B to the positive polarity, V _{D (+)} ′ − ΔV−V _TH −ΔV ₁ ′ −
At the time of writing the negative polarity to the voltage level of [ΔV ₂ ′ (average value)] − [ΔV ₃ ′ (average value)], V _{D (−)} ′ + Δ
V + V _TH −ΔV ₁ ′ + [ΔV ₂ ′ (average value)] + [ΔV
ΔV + 2V _TH set to the voltage level of ₃ '(average value)]
When supplied as a voltage signal having a fluctuation amplitude of + 2 × [ΔV ₂ ′ (average value)] + 2 × [ΔV ₃ ′ (average value)], when the amplitude of the voltage data output from the data circuit is set to ΔV Also, the average effective voltage of all pixels is ΔV +
It can be made to be about the same as V _TH .

[0082] Further, the equivalent circuit diagram of an active matrix thin film transistor liquid crystal panel is similar to FIG. 8,
As shown in FIGS. 15 and 16, since a large number of electrical wirings are provided in the TFT-LCD, a wiring capacitance exists as a configuration condition of the liquid crystal panel, and writing to the liquid crystal capacitance _CLC of each display cell is performed. , A loss current is generated. Capacitance C _GD created by the intersection of the drain bus lines and gate bus lines, each time the voltage of the drain bus lines varies, the gate bus line and the drain bus loss current proportional to the voltage variation of the drain bus line is generated, and the drain bus line and the counter electrode for each capacitance C _DC that is created between the drain bus line and the counter electrode via the liquid crystal layer, which likewise voltage of the drain bus lines varies, the drain bus line A loss current proportional to the amount of voltage fluctuation is generated.

The C existing in each display cell unit shown here
Without large so much amount of current generated by _GD and C _DC, for considering the whole wire is fairly large current, short duration loss current, in order to release, for example, in line periods outside the panel, the drain bus The resistance of the line, the gate bus line and the counter electrode must be reduced, and the current capacity of the external driver connected to each wiring must be increased.

In the embodiment of the present invention, the adjacent drain bus lines have different polarities, and when the polarity fluctuates, the adjacent drain bus lines always have voltage changes of different polarities, for example, one of the polarity changes from positive to negative. If it fluctuates, the other will fluctuate from negative polarity to positive polarity.
Therefore, the adjacent capacitance C _GD on one gate bus line
Since the loss currents generated by the capacitors C _DC adjacent to each other or on each corrugated counter electrode are currents flowing in opposite directions, the loss currents tend to cancel each other.

Also, in each of the corrugated electrodes, when the polarity fluctuates, similarly, adjacent counter electrodes always undergo voltage fluctuations of different polarities. Therefore, a tendency that the loss current between generated by the capacitance C _DC between adjacent on one drain bus lines also cancel each other.

For this reason, the loss current flowing through one gate line and drain bus line and the counter electrode of each wave type is extremely small, and the resistance of each wiring is reduced and the size of the external driver connected to each wiring is large. It is possible to provide a liquid crystal panel that does not require capacity increase,
Suitable for high definition.

The present invention is not limited to the above embodiments, but various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0088]

As described above in detail, according to the present invention, pixel electrode groups connected to one gate bus line via thin film transistors are alternately arranged in a staggered manner in the gate bus line direction. The one gate bus line
Odd-numbered pixel electrode groups connected to the gate bus
Even number connected to the gate bus line adjacent to the line
Lined up in the gate bus line direction by the pixel electrode group of the eye
Constitute a group of pixel electrodes arranged in a row, and
The counter electrode is opposed to the pixel electrode group arranged in a line.
One, and the odd-numbered
Connect the opposing electrodes and the even-numbered opposing electrodes
The odd-numbered counter electrode group and the even-numbered counter electrode group
Circuit for switching the
The polarity of the voltage data of the in-bus line is different and one scan line
The polarity of the voltage data is inverted at twice the period of the in period,
And the voltage data of the positive polarity and the negative polarity were inverted with each other.
Supply voltage signal indicating voltage to each drain bus line
The polarity of adjacent counter electrodes is different and each counter electrode
Data of pixel electrode group and threshold voltage of liquid crystal corresponding to
Includes offset voltage and effective voltage correction voltage equivalent to
A voltage signal is supplied to each counter electrode to select a gate bus line.
By performing voltage writing on the pixel electrode by the selection signal , the average effective voltage of the liquid crystal cell can be made uniform and the withstand voltage of the switching driver for the gate bus line and the drain bus line can be reduced.

Further, this driving method is suitable for a large-capacity, high-definition display, since the occurrence of a loss current caused by the wiring capacitance in the panel can be reduced. In addition, since this driving method can provide the same effect even when an analog voltage is input to the drain bus line, it can be sufficiently applied to gradation driving of an active matrix thin film transistor liquid crystal panel.

Further, according to the present invention, a group of pixel electrodes connected to one gate bus line via a thin film transistor is arranged in one row in the direction of the gate bus line, and two adjacent gate bus lines are provided with a TFT. 2 connected via
In the pixel electrode group of the column, the two gate bus lines
Odd-numbered connected to one of the gate bus lines
Even number connected to the pixel electrode group and the other gate bus line
To th facing the pixel electrode group provided one corrugated counter electrode structure, and is connected non-adjacent corrugated counter electrode to each other, respectively a circuit for switching provided, adjacent
The polarity of the drain bus line voltage data is different
The polarity of the voltage data is inverted twice as long as the inspection line cycle
And the voltage data of the positive polarity and the negative polarity are inverted with each other.
Voltage signal indicating the applied voltage to each drain bus line.
And the adjacent counter electrodes have different polarities and
Polarity data of the pixel electrode group corresponding to the pole and the threshold voltage of the liquid crystal
Voltage and the effective voltage correction voltage.
Voltage signal to each opposing electrode,
By writing a voltage to the pixel electrode by the selection signal , the average effective voltage of the liquid crystal cell can be made uniform and the withstand voltage of the switching driver of the drain bus line can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic perspective view of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 3 is a schematic block diagram of a data circuit of an active matrix thin film transistor liquid crystal panel according to an embodiment of the present invention.

FIG. 4 is a diagram showing a common variation circuit of an active matrix type thin film transistor liquid crystal panel according to an embodiment of the present invention.

FIG. 5 is a diagram showing timing of voltage data supplied to a drain bus of an active matrix thin film transistor liquid crystal panel according to the embodiment of the present invention.

FIG. 6 is an operation timing chart of a common variation circuit of an active matrix thin film transistor liquid crystal panel according to an embodiment of the present invention.

FIG. 7 is an equivalent circuit diagram of a liquid crystal cell of an active matrix thin film transistor liquid crystal panel according to an embodiment of the present invention.

FIG. 8 is an equivalent circuit diagram of an active matrix thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 9 is a timing chart showing a drive voltage and a pixel voltage change of a TFT connected to an odd drain bus of an active matrix thin film transistor liquid crystal panel according to an embodiment of the present invention.

FIG. 10 is a timing chart showing a drive voltage and a pixel voltage change of a TFT connected to an even drain bus of an active matrix thin film transistor liquid crystal panel according to an embodiment of the present invention.

FIG. 11 is a schematic configuration diagram of an active matrix type thin film transistor liquid crystal panel showing a modified embodiment of the present invention.

FIG. 12 is a configuration diagram of a conventional active matrix type thin film transistor liquid crystal panel.

FIG. 13 is a diagram showing a drive timing chart of a conventional active matrix type thin film transistor liquid crystal panel.

FIG. 14 is a diagram showing electro-optical characteristics of a conventional TN liquid crystal cell.

FIG. 15 is a schematic perspective view of an active matrix type thin film transistor liquid crystal panel showing another embodiment of the present invention.

FIG. 16 is a view showing a configuration of a counter electrode of an active matrix type thin film transistor liquid crystal panel according to another embodiment of the present invention.

FIG. 17 is a schematic block diagram of an active matrix thin film transistor liquid crystal panel showing another embodiment of the present invention.

FIG. 18 is a diagram showing timing of voltage data supplied to a drain bus of an active matrix thin film transistor liquid crystal panel according to another embodiment of the present invention.

FIG. 19 is a timing chart of a common variation circuit of an active matrix thin film transistor liquid crystal panel according to another embodiment of the present invention.

FIG. 20 is a timing chart showing a drive voltage and a pixel voltage change of a TFT connected to an odd drain bus of an active matrix type thin film transistor liquid crystal panel according to another embodiment of the present invention.

FIG. 21 is a timing chart showing a drive voltage and a pixel voltage change of a TFT connected to an even drain bus of an active matrix type thin film transistor liquid crystal panel according to another embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 11 gate bus line 12 drain bus line 13 TFT (thin film transistor) 14 pixel electrode 15 counter electrode 15 a portion facing pixel electrode 15 b counter electrode junction 16 liquid crystal 17 auxiliary capacitance 18 auxiliary capacitance line 19 gap 20 scanning circuit 30 data circuit 31 data Generation unit 32 Data inversion unit A 33 Data inversion unit B 34 Data output unit A 35 Data output unit B 40 Common variation circuit 41, 42 Buffer 43, 44 Operational amplifier 45, 46 MOSFET

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Atsushi Takahashi 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Hiroshi Hamano 1-7-112 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (58) Field surveyed (Int. Cl. ⁷ , DB name) G09G 3/36 G02F 1/133 G09G 3/20

Claims (5)

(57) [Claims] A gate bus line and a drain bus line which are orthogonally arranged on a rear substrate; a thin film transistor corresponding to each pixel electrode is provided at an intersection of the gate bus line and the drain bus line; Providing a counter electrode, providing an alignment film oriented in an appropriate direction on the surfaces of the back substrate and the front substrate, aligning the alignment films of both substrates to face each other via a liquid crystal layer, and bonding the substrates. And a method of driving an active matrix type thin film transistor liquid crystal panel in which a polarizing film is adhered to the back surface of the front substrate, wherein a group of pixel electrodes connected to one gate bus line via a thin film transistor are alternately staggered in the gate bus line direction. And connected to the one gate bus line.
Adjacent to the odd-numbered pixel electrode group
Even-numbered pixel electrodes connected to the adjacent gate bus line
Configure the image <br/> pixel electrode group arranged in a row in the gate bus line direction by pole group, the gate bus line direction arranged in a row
Opposite to have been the pixel electrode group opposing electrode provided one by,
The odd-numbered counter electrodes and the even-numbered counter electrodes are connected to each other among the plurality of provided counter electrodes, and the odd-numbered counter electrode group and the even-numbered counter electrode group are respectively connected.
A switching circuit is provided, the polarity of the voltage data of the adjacent drain bus line is different, the polarity of the voltage data is inverted in a cycle twice as long as one scanning line cycle, and the positive and negative voltage data are mutually A voltage signal indicating the inverted voltage is supplied to each drain bus line, the polarity of the adjacent counter electrode is different, and the offset voltage corresponding to the polarity data of the pixel electrode group corresponding to each counter electrode and the threshold voltage of the liquid crystal. And a voltage signal including an effective voltage correction voltage is supplied to each counter electrode, and a voltage is written to a pixel electrode by a selection signal of a gate bus line, thereby driving the active matrix thin film transistor liquid crystal panel. 2. The active matrix type thin film transistor according to claim 1, wherein impedance components including capacitances C _DP1 and C _DP2 existing between said pixel electrode and an adjacent drain bus line are made equal to operate. How to drive a liquid crystal panel. 3. The active matrix type thin film transistor according to claim 1, wherein an auxiliary capacitance _CS is provided electrically in parallel with the liquid crystal capacitance _CLC between the pixel electrode and the counter electrode, and is operated. How to drive a liquid crystal panel. 4. A gate bus line and a drain bus line which are orthogonally arranged on a rear substrate, thin film transistors corresponding to respective pixel electrodes are provided at intersections of the gate bus lines and the drain bus lines, and a transparent substrate is provided on the front substrate. Providing a counter electrode, providing an alignment film oriented in an appropriate direction on the surfaces of the back substrate and the front substrate, aligning the alignment films of both substrates to face each other via a liquid crystal layer, and bonding the substrates. And a method of driving an active matrix type thin film transistor liquid crystal panel having a polarizing film attached to the back surface of the front substrate, wherein pixel electrodes connected to one gate bus line via the thin film transistor are arranged in a line in the gate bus line direction. br /> is location, the pixel electrode group of two rows which are connected via a thin film transistor adjacent two gate bus lines those
One gate bus line of the two gate bus lines
Odd-numbered pixel electrode groups connected to
Opposite the even-numbered pixel electrode group connected to Surain to be provided with a single corrugated counter electrode, and connecting the corrugated counter electrode to each other which are not adjacent, to switch the respective
That the circuit is provided, different polarities of the voltage data of the adjacent drain bus lines, first polarity of said voltage data to twice the period of the scan line period is inverted, and the inverted positive and negative polarities of the voltage data from each other A voltage signal indicating the applied voltage is supplied to each drain bus line, the polarity of the adjacent counter electrode is different, and the offset voltage and the polarity data of the pixel electrode group corresponding to each counter electrode and the threshold voltage of the liquid crystal. A method for driving an active matrix type thin film transistor liquid crystal panel, characterized in that a voltage signal including an effective voltage correction voltage is supplied to each counter electrode, and a voltage is written to a pixel electrode by a selection signal of a gate bus line. 5. An operation in which impedance components including capacitances C _DP1 and C _DP2 existing between the pixel electrode and an adjacent drain bus are equalized and operated.
5. The method for driving an active matrix thin film transistor liquid crystal panel according to 4 .