KR100627308B1 - Data driver and light emitting display using the same - Google Patents

Abstract

An organic light emitting display device of a current writing method provides a data driver which converts grayscale data input from the outside into a data current and transfers the data current to a data line. The digital / analog converter of the data driver converts the gradation data sequentially input into the data current and transfers the data current to the data output unit. The data output unit simultaneously outputs the data current after sampling the data current. Here, the wiring is precharged to the average voltage of the power supply voltage before the data current is transferred from the digital / analog converter to the data output unit. The data current can then be delivered to the data output without loss.

Emission, Organic, Current Entry, Precharge, Analog, Gray

Description

DATA DRIVER AND LIGHT EMITTING DISPLAY USING THE SAME}

1 is a schematic plan view of a light emitting display device according to an exemplary embodiment of the present invention.

2 is a schematic block diagram of a data driver according to a first exemplary embodiment of the present invention.

3 is a schematic block diagram of a multiplexing processor of the data driver of FIG. 2.

4 is a diagram illustrating an example of a D / A converter of the data driver of FIG. 3.

5 is a diagram illustrating an output terminal of a D / A converter and an input terminal of a data output unit in the data driver according to the first exemplary embodiment of the present invention.

6 is a diagram illustrating an output terminal of a D / A converter, an input terminal of a data output unit, and a precharge unit in a data driver according to a second exemplary embodiment of the present invention.

7 is a switching timing diagram of the precharge unit of FIG. 6.

8 is a schematic block diagram of a data driver according to a third exemplary embodiment of the present invention.

The present invention relates to a light emitting display device, and more particularly, to a data driving device for supplying a data signal in the form of a current and a light emitting display device using the same.

BACKGROUND ART A light emitting display device is a display device that displays an image using an element that emits light corresponding to a magnitude of an applied current, and an organic light emitting display device using light emission of an organic material has recently been used. The organic light emitting diode display is a display device that electrically excites an organic material to emit light, and may display an image by voltage writing or current writing N × M organic light emitting cells. The organic light emitting cell has a structure of an anode layer, an organic thin film layer and a cathode layer.

The method of driving the organic light emitting cell formed as described above includes a passive matrix method and an active matrix method according to the addressing method. In the passive matrix method, the anode and the cathode are formed to be orthogonal and the lines are selected and driven, whereas the active matrix method is a driving method in which a thin film transistor and a capacitor are connected to each pixel electrode to maintain a voltage by the capacitor. At this time, the active matrix method is divided into a voltage write method and a current write method according to the type of the signal applied to maintain the voltage to the capacitor.

However, the conventional pixel circuit of the voltage writing method has a problem in that it is difficult to obtain a high gradation due to variations in the threshold voltage of the thin film transistor and the mobility of the carrier caused by the nonuniformity of the manufacturing process. On the other hand, in the pixel circuit of the current writing method, even if the current source for supplying current to the pixel circuit is uniform through the entire panel, even if the driving transistors in each pixel have uneven voltage / current characteristics, uniform display characteristics can be obtained.

When the display device is implemented using the pixel of the current write method, a current generation circuit for converting the data signal representing the gray level into a current and applying the same to the pixel is required. That is, there is a need for a data driving device that converts and applies gradation data applied from the outside into a data signal in the form of current (hereinafter, referred to as "data current").

Such a data driving apparatus requires a digital / analog converter for converting grayscale data into an analog data current and a data output unit for buffering the converted data current and transferring the data current to a data line. In general, the data current must be transferred to the data line once during one horizontal period. As the resolution of the organic light emitting diode display increases, the horizontal period becomes shorter. Therefore, the data current should be buffered at the data output section for a short horizontal period. When the level of the current used to emit light of the organic light emitting device is low, the data current is not sufficiently buffered for one horizontal period, so that normal data current is transferred to the data line. It may not be.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a data driving device that converts grayscale data into a data current and transfers the data to a data line.

Another technical problem of the present invention is to provide a data driving device capable of normally transferring a data current to a data output unit.

In order to solve this problem, the present invention precharges before receiving the data current at the data output unit of the data driving device.

According to one aspect of the present invention, a data driving apparatus is provided which sequentially receives a plurality of data signals indicating gray scale and applies data currents to a plurality of data lines formed on a display unit of a light emitting display device. The data driving apparatus of the present invention includes at least one converter for converting the data signal into a data current, a data output unit for receiving the data current output from the converter and transferring the data current to the plurality of data lines, and the data current. And a precharge unit for charging the wiring between the converter and the data output unit to a constant voltage independent of the data current before the data is transferred to the data output unit.

According to an embodiment of the present invention, the conversion unit includes a first transistor connected to the wiring to transfer a current corresponding to the data current to the wiring and to supply a first voltage, wherein the output The unit includes a second transistor connected to the wiring and connected to a second power source for receiving a current from the first transistor and supplying a second voltage. The precharge unit charges the wiring with a third voltage between the second voltage and the first voltage. In this case, the third voltage may be an average voltage of the second voltage and the first voltage.

According to another embodiment of the present invention, the precharge unit includes first and second resistors connected in series between the first power source and the second power source, and the contact point of the first resistor and the second resistor is Is connected to the wiring.

According to another feature of the present invention, there is provided a light emitting display device including a display unit, a scan driver, and a data driver. The display unit includes a plurality of data lines formed in one direction, a plurality of first and second scan lines formed in a direction crossing the data lines, and a plurality of pixel regions defined by the data lines and the first scan lines and each having light emitting elements. It includes. The scan driver selectively transmits a selection signal for selecting a pixel region in which data is to be written to the plurality of first scan lines, and selectively transmits a light emission signal for selecting a pixel region in which a light emitting element emits light to the plurality of second scan lines. do. The data driver receives a plurality of data signals sequentially input and converts the data signal into a data current, and a data output for temporarily storing the converted data current in the converter and then transferring the data current to the plurality of data lines. Have wealth In this case, before the data current is transferred from the converter to the data output part, the wiring between the converter and the data output part is charged with a third voltage between the first voltage and the second voltage.

According to an embodiment of the present invention, the third voltage is a constant voltage regardless of the data current delivered to the data output unit.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification. When a part is connected to another part, this includes not only a directly connected part but also an electrically connected part with another element in between.

1 is a schematic plan view of a light emitting display device according to an exemplary embodiment of the present invention.

As illustrated in FIG. 1, a light emitting display device according to an exemplary embodiment of the present invention includes a display unit 100, a scan driver 200, and a data driver 300.

The display unit 100 includes a plurality of data lines D _{1 to} D _m , a plurality of selected scan lines S _{1 to} S _n , a plurality of light emitting scan lines E _{1 to} E _n , and a plurality of subpixels 110. do. The plurality of data lines D _{1 to} D _m extend in the column direction and transmit a data current representing an image. The selection scan lines S ₁ -S _n extend in a row direction and transmit a selection signal for selecting a pixel to which a data current is applied among the plurality of subpixels, and the plurality of light emission scan lines E ₁ -E _n in the row direction. It extends and transmits a light emission signal for selecting a subpixel to emit light among the plurality of subpixels.

The pixel region is defined by two neighboring selection scan lines S ₁ -S _n and two neighboring data lines D ₁ -D _m , and a subpixel 110 having light emitting elements is formed in the pixel region. For example, from the i-th selection scan lines (S _i) and j th data lines (D _j) the sub-pixels 110 to the data lines (D _j) when subjected to a selection signal from the selection scan line (S _i) connected to the The data current is written, and when the light emission signal is applied from the light emission scan line E _i , the light emitting element emits light with a gray level corresponding to the data current written. In addition, in an embodiment of the present invention, there are subpixels emitting light of R (red) color, subpixels emitting light of G (green) color, and subpixels emitting light of B (blue) color, It is assumed that the pixels representing one color are formed by the three subpixels.

The data driver 200 applies a data current to the data lines D _{1 to} D _m . The scan driver 300 sequentially applies selection signals to the plurality of selection scan lines S _{1 to} S _n , and sequentially applies light emission signals to the plurality of emission scan lines E _{1 to} E _n .

In this case, the scan driver 200 and / or the data driver 300 may be directly mounted in the form of an integrated circuit on the substrate on which the display unit 100 is formed. Alternatively, these driving units 200 and / or 300 may be formed on the substrate on which the display unit 100 is formed by scanning lines S ₁ -S _n , E ₁ -E _n , data lines D ₁ -D _m , and pixels 110. It may be formed of the same layers as the layer forming the transistor. Alternatively, the driving units 200 and / or 300 may be formed on a substrate separate from the substrate on which the display unit 100 is formed, and the substrates may be electrically connected to the substrate on which the display unit 100 is formed. In addition, the driving units 200 and / or 300 may be in the form of a chip in a tape carrier package (TCP), a flexible printed circuit (FPC), or a tape automatic bonding (TAB), which are bonded to and electrically connected to a substrate on which the display unit 100 is formed. It may be mounted as.

Next, the data driver 300 of FIG. 1 will be described in detail with reference to FIG. 2. 2 is a schematic block diagram of a data driver 300 according to a first embodiment of the present invention, and FIG. 3 is a schematic block diagram of the multiplexing processor 330 of the data driver 300 of FIG. 2.

As shown in FIG. 2, the data driver 300 according to the first exemplary embodiment may include a shift register 310, a latch 320, a multiplexing processor 330, and a digital / analog converter (hereinafter, “D /”). A conversion unit "340, a control signal generation unit 350 and a data output unit 360. 2, for convenience of description, 300 data lines D _{1 to} D _m , that is, 100 data lines corresponding to R subpixels, 100 data lines corresponding to G subpixels, and 100 corresponding to B subpixels. It is assumed that the data output unit has 300 channels corresponding to the data line. In addition, it is assumed that grayscale data corresponding to 100 pixels formed in one row are sequentially input, and R, G, and B grayscale data of one pixel are input in parallel.

The shift register unit 310 generates a sampling signal that is sequentially shifted and transmits it to the latch unit 320, and the latch unit 320 samples and stores R, G, and B grayscale data sequentially input according to the sampling signal. And a sampling latch portion 321 and a holding latch portion 322.

In detail, the shift register unit 310 generates a sampling signal according to the activation signal IE, and outputs the sampling signal while sequentially shifting the sampling signal in synchronization with the clock CLKH. Here, 100 signals are generated so that the sampling signals SRH0 to SRH99 correspond to 100 pixels in a row.

The sampling latch unit 321 samples the input R, G, and B gray scale data DR0 to DR99, DG0 to DG99, and DB0 to DB99 in response to the sampling signals SRH0 to SRH99. That is, in response to the sampling signal SRHi, the sampling latch unit 321 samples the R, G, and B grayscale data DRi, DGi, and DBi corresponding to the (i + 1) th pixel in the row direction. Here, if the R, G, and B grayscale data are composed of 10 bits of digital data, the sampling latch unit 321 samples the data for each bit to sample a total of 30 bits of data. Next, the holding latch unit 322 maintains the gradation data sequentially sampled by the sampling latch unit 321 until the gradation data corresponding to one row is sampled, and then is sampled in response to the holding activation signal DH. One row of gradation data DR0 to DR99, DG0 to DG99, and DB0 to DB99 is output.

3, the multiplexing unit 330 includes a shift register 331 and a multiplexing unit 332. The shift register 331 of the multiplexing processor 330 receives the clock CLKL and the activation signal DAS and sequentially outputs the multiplexed signals MSW0 to MSW99 and the shift signals SRL0 to SRL99. In this case, the clock CLKL of the shift register 331 may have a lower frequency than the clock CLKH of the shift register 310, and the activation signal DAS may be different from the holding activation signal DH of the holding latch unit 322. Have the same timing. The multiplexed signals MSW0 to MSW99 and the shift signals SRL0 to SRL99 are output in synchronization with the clock CLKL. The multiplexed signals MSW0 to MSW99 are applied to the multiplexer 332 of the multiplexed processor 330, and the shift signals SRL0 to SRL99 are output to the control signal generator 350.

The multiplexing unit 332 of the multiplexing processing unit 330 outputs R, G, and B data (DR0 to DR99, DG0 to DG99, and DB0 to DB99) output from the holding latch unit 322 based on the multiplexing signals MSW0 to MSW99. Multiplexing and sequentially transmitting to the D / A converter 340. That is, when the multiplexer 332 receives the multiplexed signal MSWi, the multiplexer 332 transfers the R, G, and B data DRi, DGi, and DBi to the D / A converter 340.

The D / A converter 340 receives the R, G, and B data (DR0 to DR99, DG0 to DG99, and DB0 to DB99) sequentially input from the multiplexer 332, respectively, in analog form. D0 to D99 and B0 to B99 are sequentially converted to the data output unit 360. In this case, the D / A converter 340 includes R, G, and BD / A converters 341, 342, and 343, and the R, G, and BD / A converters 341, 342, and 343 are R and G, respectively. , Converts B data to analog current.

The control signal generator 350 receives the shift signals SRL0 to SRL99 of the multiplexing processor 330, generates the sampling signals CHS0 to CHS99, and outputs them to the data outputter 360. At this time, the sampling signal CHSi is converted into R, G, and B data (Ri, Bi, Gi) converted from the R, G, and B data (DRi, DBi, DGi), which are multiplexed by the multiplexed signal MSWi. It is generated by the shift signal SRi to be synchronized with the time point transmitted to the data output unit 360.

The data output unit 360 sequentially processes the R, G, and B data currents R0 to R99, D0 to D99, and B0 to B99 input from the D / A converter 340 in response to the sampling signals CHS0 to CHS99. Sample with That is, the data output unit 360 samples the R, G, and B data currents Ri, Gi, and Bi which are converted into an analog form by the D / A converter 340 in response to the sampling signal CSHi. . And a data output unit 360 R corresponding to the pixels on a line, G, B data, and then samples the current (R0~R99, D0~D99, B0~B99) data corresponding to the respective current line data (D ₁ To D _m ) at the same time.

In the above, the process of outputting the R, G, B grayscale data corresponding to one row of pixels into the data driver 300 to be converted into a data current and outputting the data lines to the data line of the display unit 100 has been described. This process may be repeated for the R, G, and B gray data of the pixels of all rows so that gray data of one frame may be converted into a data current and transferred to the display unit 100. According to the first embodiment, since the D / A converter is not formed for each data line and the D / A converter is formed for each of R, G, and B, the area occupied by the D / A converter can be reduced.

Next, an example of the D / A converter 340 used in the data driver 300 will be described with reference to FIG. 4. 4 is a diagram illustrating an example of the D / A converter 340 of the data driver 300 of FIG. 3. In FIG. 4, only the RD / A converter 341 of the D / A converter 340 is illustrated, and the G and BD / A converters 342 and 343 have the same structure as the RD / A converter 341. And description is omitted.

As shown in FIG. 4, the RD / A converter 341 includes a transistor TB connected to the current source I _B , ten mirror transistors T0 to T9, and switching elements SW0 to SW9. The transistor TB and the mirror transistors T0 to T9 are connected in the form of current mirrors, respectively, and the size of the mirror transistors T0 to T9 is 2 ⁰ to 2 ⁹ times the size of the transistor TB, respectively. The size of the transistor refers to the ratio (W / L) of the channel width (W) and the channel length (L) of the transistor. Specifically, the transistor TB is connected in the form of a diode so that the source of the transistor TB is connected to the power supply voltage VDD and the drain of the transistor TB is connected to the current source I _B. The transistor Tj (where j is an integer between 0 and 9) has a source connected to the power voltage VDD and a gate connected to the gate of the transistor TB. In addition, a switch SWj is connected between the drain of the transistor Tj and the output signal line of the RD / A converter 341.

Then, 2 ⁰ to 2 ⁹ times the current (2 ⁰ I _B to 2 ⁹ I _B ) of the current I _B flowing through the drain of the transistor TB is output to the drain of the mirror transistors T0 to T9, respectively. The switching elements SW0 to SW9 are turned on corresponding to 10 bits of the R data sequentially input from the multiplexer 331 of the multiplexer 330. That is, when the R data is sequentially " 0101000101 " starting from the upper bit, the switching elements SW0, SW2, SW6, and SW8 corresponding to '1' are turned on, and the current flowing through the output signal line of the RD / A converter 341 is (2 ⁰ +2 ² +2 ⁶ +2 ⁸ ) I _B In this manner, the R, G, and B grayscale data are converted into data currents by the RD / A converter 341 and transferred to the data output unit 360 through the output signal line. In addition, the D / A converter 340 converts the R, G, and B data sequentially input from the multiplexing processor 330 into R, G, and B data currents through the process, and sequentially converts the data into the data output unit 360. Output

5 is a diagram illustrating an output terminal of the R D / A converter 341 of the D / A converter 340 and an input terminal of the data output unit 360 in the data driver 300 according to the first exemplary embodiment of the present invention. In FIG. 5, only an output terminal of the RD / A converter 341 and an input terminal of the data output unit 360 connected to the RD / A converter 341 are illustrated. The same structure is also applied to the G and BD / A converters 342 and 343. The output terminal of is formed and the input terminal of the data output unit 360 of the same structure is connected.

5, the output terminal of the D / A converter 341 includes current mirrors M1 and M2, and the input terminal of the data output unit 360 also includes current mirrors M3 and M4. In FIG. 5, transistors M1 and M2 forming current mirrors M1 and M2 are illustrated as n-channel field effect transistors, and transistors M3 and M4 forming current mirrors M3 and M4 are p-channel field effectd. Shown as a transistor.

The data current I _in output from the D / A converter 341 is applied to the drain of the transistor M1 connected in the form of a diode in the current mirrors M1 and M2, and the source of the transistor M1 is connected to the ground voltage. It is connected. The transistor M2 has a source connected to a reference voltage, a gate connected to a gate of the transistor M1, and a drain of the transistor M2 connected to the data output unit 360 through a wire 370.

A drain of the transistor M3 connected in the form of a diode in the current mirrors M3 and M4 is connected to the D / A converter 341 through the wiring 370, and a power supply voltage VDD is connected to the source of the transistor M3. It is. The transistor M4 has a source connected to the power supply voltage VDD and a gate connected to the gate of the transistor M3. The current flowing through the drain of the transistor M4 becomes the input current of the data output unit 360.

In this manner, when the R, G, and B data currents corresponding to one row are sequentially output from the D / A converter 340, the data output unit 360 receives the current as an input current and sequentially. Sample. At this time, the time for transmitting the R, G, and B data currents corresponding to one row to the data output unit 360 is substantially equal to one horizontal period. That is, a time (hereinafter, referred to as a "data transfer period") for transmitting a data current corresponding to one pixel to the data output unit 360 is a short time corresponding to one hundredth of a horizontal period. However, when the magnitude of the data current is small and the parasitic components present in the wiring 370 between the D / A converter 340 and the data output unit 360 are large, the data current may not be sufficiently delivered during such a short time. It may not be possible to sample the desired current at the output 360.

Hereinafter, an embodiment in which the data output unit 360 can sample the data current within a short time will be described in detail with reference to FIGS. 6 and 7.

6 illustrates an output terminal of the RD / A converter 341 of the D / A converter 340, an input terminal of the data output unit 360, and a precharge unit in the data driver 300 according to the second exemplary embodiment of the present invention. Drawing.

Referring to FIG. 6, the data driver 300 according to the second exemplary embodiment of the present invention has an output terminal and a data output unit 360 of the R, G, and BD / A converters 341, 342, and 343 as compared with the first exemplary embodiment. It further comprises a precharge unit connected to the input terminal of each. In FIG. 6, only the precharge unit 380 connected to the input terminal of the data output unit 360 connected to the RD / A converter 341 and the D / A converter 341 is illustrated, and the G and BD / A converters 342, Also for 343, a precharge portion having the same structure is formed.

As shown in FIG. 6, the precharge unit 380 includes resistors R1 and R2 and switches SW11, SW12, and SW13. The resistors R1 and R2 are connected in series between the power supply voltage VDD and the ground voltage, and the two resistors R1 and R2 have the same size. The switch SW11 is connected between the gate of the transistor M1 and the gate of the transistor M2, and the switch SW12 is connected between the wiring 370 and the drain of the transistor M3. In addition, the switch SW12 is connected between the contacts of the two resistors R1 and R2 and the wiring 370.

Next, the operation of the precharge unit 380 of FIG. 6 will be described with reference to FIG. 7. 7 is a switching timing diagram of the precharge unit 380 of FIG. 6. In FIG. 7, only a data transfer period corresponding to one pixel is illustrated. In the timing diagram, a high level represents an on state of a switch and a low level represents an off state.

As shown in FIG. 7, the data transfer period includes a precharge period Tp and a mirroring period Tm. In the precharge period Tp, the switch SW13 is turned on while the switches SW11 and SW12 are turned off. Then, the voltage VDD corresponding to the difference between the power supply voltage VDD and the ground voltage is distributed by the resistors R1 and R2 so that the voltage VDD / 2 corresponding to half of the power supply voltage VDD is connected to the wiring 370. Is applied.

Next, in the mirroring period Tm, the switch SW13 is turned off and the switches SW11 and SW12 are turned on. At this time, the drain of the transistor M3 and the drain of the transistor M2 are precharged to the voltage (VDD / 2). In order for the same current as the data current I _in transmitted to the drain of the transistor M1 to be transferred to the drain of the transistor M2, the same current as the data current I _in flows to the drains of the transistors M2 and M3. The drain voltages of transistors M2 and M3 should be set. However, since the drain voltages of the transistors M2 and M3 are determined between the power supply voltage VDD and the ground voltage according to the data current I _in , the drain voltages of the transistors M2 and M3 are set to the voltage VDD / 2. If precharged, the drain voltages of the transistors M2 and M3 can be quickly charged to a desired voltage on average. Therefore, the time for delivering the desired data current to the drain of the transistor M3 is shortened on average.

As described above, according to the second exemplary embodiment of the present invention, even if the data transfer time is short, the data current output from the D / A converter 340 may be transferred to the data output unit 360 through precharge.

As described above, in the first and second embodiments of the present invention, the D / A converter is separately provided for each of R, G, and B in the D / A converter 340. However, in contrast, R, G, You can also process B data. In this case, the multiplexing processor 330 may sequentially output R, G, and B data corresponding to one pixel and transmit the data to the D / A converter 340.

In addition, in the first and second embodiments of the present invention, the D / A converter 340 including the R, G, and BD / A converters 341, 342, and 343 has been described as one. Plural portions 340 may be formed. That is, the plurality of data lines D _{1 to} D _m can be divided into a plurality of groups, and a D / A converter can be formed for each group. Hereinafter, such an embodiment will be described with reference to FIG. 8.

8 is a schematic block diagram of a data driver according to a third exemplary embodiment of the present invention. 8 illustrates a case in which two D / A converters are formed in the data driver of FIG. 2 for convenience.

Referring to FIG. 8, the data driver 300 according to the third embodiment of the present invention includes two D / A converters 340a and 340b, multiplexing processors 330a and 330b, and data output units 360a and 360b, respectively. Except that formed one by one has the same structure as the data driver of FIG.

Specifically, the shift register (not shown) of the multiplexing unit 330a sequentially outputs 50 multiplexing signals MSW0 to MSW49 and the shift signals SRL0 to SRL49, and the multiplexing unit (not shown) of the multiplexing unit 330a. (Not shown) is half of the R, G, and B data (R0, DR99, DG0, DG99, DB0, and DB99) output from the latch unit 320 in response to the multiplexed signals MSW0 through MSW49. (DR0 to DR49, DG0 to DG49, and DB0 to DB49) are sequentially multiplexed and transferred to the D / A converter 340a. Similarly, the shift register (not shown) of the multiplexing processor 330b sequentially outputs 50 multiplexed signals MSW50 to MSW99 and shift signals SRL50 to SRL99, and the multiplexer (not shown) of the multiplexing processor 330b. (Not shown) is the R, G, and B data of the other half of the R, G, and B data (DR0 to DR99, DG0 to DG99, and DB0 to DB99) output from the latch unit 320 in response to the multiplexed signals MSW50 to MSW99. (DR50 to DR99, DG50 to DG99, and DB0 to DB99) are sequentially multiplexed and transferred to the D / A converter 340b.

The D / A converter 340a converts the R, G, and B data (DR0 to DR49, DG0 to D49, and DB0 to DB49) sequentially input from the multiplexing processor 330a into data currents to sequentially output the data output unit ( 360a). In addition, the D / A converter 340b converts the R, G, and B data (DR50 to DR99, DG50 to DG99, and DB0 to DB99) sequentially input from the multiplexing processor 330b to output data sequentially. Output to the unit 360b.

The control signal generator 350 receives the shift signals SRL0 to SRL49 and SRL50 to SRL99, respectively, and generates sampling signals CHS0 to CHS49 and CHS50 to CHS99 and outputs them to the data output units 360a and 360b, respectively. . The data output unit 360a samples the R, G, and B data currents sequentially input from the D / A converter 360a in response to the sampling signals CHS0 to CHS49. The R, G, and B data currents sequentially input from the / A converter 360b are sampled in response to the sampling signals CHS50 to CHS99.

According to the third embodiment described above, since all data is not processed sequentially but some data is processed in parallel, the data transfer period can be extended. Therefore, the desired data current can be transferred from the D / A converter to the data output unit. In the third embodiment, the precharge described in the second embodiment may be applied, and a detailed description thereof will be omitted.

In the exemplary embodiment of the present invention, a voltage corresponding to half of the power supply voltage VDD is used as the precharge voltage. Alternatively, a voltage corresponding to an arbitrary current level may be used as the precharge voltage.

In the embodiment of the present invention, a data driver for outputting data currents corresponding to 300 data lines has been described as an example. However, the present invention is not limited to the number of data lines. In addition, the data driver described in the embodiment of the present invention may be manufactured in the form of one chip, and in the light emitting display device, there may be several such chips. In addition, although the embodiments of the present invention have been described as forming pixels of R, G, and B colors, pixels of two or more colors may be formed differently, and in the case of representing mono, only one color pixel may be formed. have.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

According to the present invention, grayscale data can be converted into a data current and transferred to a data line, and the area of the D / A converter can be minimized by sharing a single D / A converter. In addition, the data current output from the D / A converter may be transferred to the data output unit without loss through the precharge. By using the data current, the problem of luminance unevenness caused by the variation of the threshold voltage of the driving transistor in the voltage writing method can be eliminated.

Claims (18)

A data driving device for sequentially receiving a plurality of data signals indicating a gray level and applying a data current to a plurality of data lines formed on a display unit of a light emitting display device. At least one converter converting the data signal into a data current; A data output unit receiving the data current output from the converter and transferring the data current to the plurality of data lines; And a precharge unit configured to charge the wiring between the converter and the data output unit to a constant voltage independent of the data current before the data current is transferred to the data output unit. The method of claim 1, The converting unit includes a first transistor connected to the wiring to transfer a current corresponding to the data current to the wiring and to supply a first voltage. The output unit includes a second transistor connected to the wire and connected to a second power source for receiving a current from the first transistor and supplying a second voltage. And the precharge unit charges the wiring with a third voltage between the second voltage and the first voltage. The method of claim 2, And the third voltage is an average voltage of the second voltage and the first voltage. The method of claim 2, The precharge unit includes first and second resistors connected in series between the first power supply and the second power supply. And a contact point of the first resistor and the second resistor is connected to the wiring. The method of claim 4, wherein And a data driving device having the same magnitude as that of the first resistor. The method of claim 4, wherein The converter further includes a third transistor connected to the first transistor in the form of a current mirror to transfer the data current. The method of claim 6, The precharge unit may include a first switch connected between a gate of the third transistor and a gate of the first transistor, a second switch connected between the wiring and the second transistor, and the wiring and the first and second electrodes. Further comprising a third switch connected between the contacts of the resistor, The third switch is turned on, the first and second switches are turned off, the wiring is charged to the predetermined voltage, the third switch is turned off, and the first and second switches are turned on, so that the data current of the converter is A data driving device delivered to the data output unit. The method according to any one of claims 1 to 7, The converter converts a plurality of data signals sequentially transmitted into data currents and sequentially transmits the data signals to the data output unit. And the data output unit sequentially samples and sequentially stores the data currents sequentially input and transfers the data currents to the plurality of data lines. The method of claim 8, A latch unit for sequentially sampling and storing the plurality of sequentially input data signals; And a multiplexing processor configured to multiplex the plurality of data signals transmitted from the latch unit and sequentially transmit the multiplexed data signals to the converter. The method of claim 9, The data signal includes a data signal of at least two colors, The converting unit includes at least two transducers for converting the at least two color data signals into data currents, respectively. The method of claim 9, And in the case of dividing the plurality of data lines into at least one group, the at least one converter corresponds to the at least one group, respectively. A plurality of data lines formed in one direction, a plurality of first and second scan lines formed in a direction crossing the data lines, and a plurality of pixel regions defined by the data lines and the first scan lines and each having a light emitting element. Display, A scan driver selectively transmitting a selection signal for selecting a pixel region in which data is to be written to the plurality of first scan lines, and selectively transmitting a light emission signal for selecting a pixel region in which a light emitting element emits light to the plurality of second scan lines , And Data having a converter for receiving a plurality of data signals sequentially input and converting the data signal to a data current and a data output unit for temporarily storing the converted data current in the converter and then transfers the data current to the plurality of data lines Includes the former eastern part, And a wire between the converter and the data output part is charged with a third voltage between a first voltage and a second voltage before the data current is transferred from the converter to the data output part. The method of claim 12, The converter includes a first transistor connected between the wiring and a first power supply for supplying the first voltage, and outputting a current corresponding to the data current. The data output unit includes a second transistor connected between the wiring and a second power supply for supplying the second voltage to receive a current flowing through the first transistor. The method of claim 13, The data driver further includes a precharge unit having first and second resistors connected in series between the first power supply and the second power supply and whose contacts are connected to the wiring. The method of claim 14, A light emitting display device having the same size of the first and second resistors. The method of claim 13, The converter further includes a third transistor connected to the first transistor in the form of a current mirror to transfer the data current. The method according to any one of claims 12 to 16, The converter sequentially receives the plurality of data signals, converts the data signals into data currents, and sequentially outputs the plurality of data currents to the data output unit. And the precharge unit charges the wiring to the third voltage before the data current is output to the data output unit. The method of claim 17, And the third voltage is a constant voltage regardless of the data current transmitted to the data output unit.

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